drm/radeon: update DISPCLK programming for DCE8
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -743,7 +743,7 @@ static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
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* SetPixelClock provides the dividers
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* SetPixelClock provides the dividers
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*/
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*/
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args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
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args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
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if (ASIC_IS_DCE61(rdev))
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if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
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args.v6.ucPpll = ATOM_EXT_PLL1;
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args.v6.ucPpll = ATOM_EXT_PLL1;
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else if (ASIC_IS_DCE6(rdev))
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else if (ASIC_IS_DCE6(rdev))
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args.v6.ucPpll = ATOM_PPLL0;
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args.v6.ucPpll = ATOM_PPLL0;
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