[MIPS] SMTC: Fix SMTC dyntick support.
Rework of SMTC support to make it work with the new clock event system, allowing "tickless" operation, and to make it compatible with the use of the "wait_irqoff" idle loop. The new clocking scheme means that the previously optional IPI instant replay mechanism is now required, and has been made more robust. Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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committed by
Ralf Baechle

parent
d2bb01b042
commit
8531a35e5e
@@ -38,8 +38,17 @@ __asm__(
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" .set pop \n"
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" .endm");
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extern void smtc_ipi_replay(void);
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static inline void raw_local_irq_enable(void)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* SMTC kernel needs to do a software replay of queued
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* IPIs, at the cost of call overhead on each local_irq_enable()
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*/
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smtc_ipi_replay();
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#endif
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__asm__ __volatile__(
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"raw_local_irq_enable"
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: /* no outputs */
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@@ -47,6 +56,7 @@ static inline void raw_local_irq_enable(void)
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: "memory");
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}
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/*
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* For cli() we have to insert nops to make sure that the new value
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* has actually arrived in the status register before the end of this
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@@ -185,15 +195,14 @@ __asm__(
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" .set pop \n"
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" .endm \n");
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extern void smtc_ipi_replay(void);
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static inline void raw_local_irq_restore(unsigned long flags)
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{
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unsigned long __tmp1;
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#ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred
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* SMTC kernel needs to do a software replay of queued
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* IPIs, at the cost of branch and call overhead on each
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* local_irq_restore()
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*/
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@@ -208,6 +217,17 @@ static inline void raw_local_irq_restore(unsigned long flags)
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: "memory");
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}
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static inline void __raw_local_irq_restore(unsigned long flags)
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{
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unsigned long __tmp1;
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__asm__ __volatile__(
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"raw_local_irq_restore\t%0"
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: "=r" (__tmp1)
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: "0" (flags)
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: "memory");
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}
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static inline int raw_irqs_disabled_flags(unsigned long flags)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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