powerpc/mpc85xx: Add MDIO bus muxing support to the board device tree(s)
Describe the PHY topology for all configurations supported by each board Based on prior work by Andy Fleming <afleming@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Signed-off-by: Scott Wood <oss@buserror.net>
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committed by
Scott Wood

parent
334479d1cc
commit
84e0f1c138
@@ -111,6 +111,47 @@
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shunt-resistor = <1000>;
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};
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};
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fman@400000 {
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fm1mac1: ethernet@e0000 {
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phy-handle = <&sgmii_rtk_phy2>;
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phy-connection-type = "sgmii";
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sleep = <&rcpm 0x80000000>;
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};
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fm1mac2: ethernet@e2000 {
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sleep = <&rcpm 0x40000000>;
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};
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fm1mac3: ethernet@e4000 {
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phy-handle = <&sgmii_aqr_phy3>;
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phy-connection-type = "sgmii-2500";
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sleep = <&rcpm 0x20000000>;
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};
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fm1mac4: ethernet@e6000 {
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phy-handle = <&rgmii_rtk_phy1>;
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phy-connection-type = "rgmii";
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sleep = <&rcpm 0x10000000>;
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};
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mdio0: mdio@fc000 {
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rgmii_rtk_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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sgmii_rtk_phy2: ethernet-phy@3 {
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reg = <0x3>;
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};
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};
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xmdio0: mdio@fd000 {
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sgmii_aqr_phy3: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x2>;
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};
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};
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};
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};
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pci0: pcie@ffe240000 {
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