powerpc/mpc85xx: Add MDIO bus muxing support to the board device tree(s)
Describe the PHY topology for all configurations supported by each board Based on prior work by Andy Fleming <afleming@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Signed-off-by: Scott Wood <oss@buserror.net>
This commit is contained in:
Igal Liberman
committed by
Scott Wood
Scott Wood
parent
334479d1cc
commit
84e0f1c138
@@ -1,7 +1,7 @@
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/*
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* P5040DS Device Tree Source
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*
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* Copyright 2012 - 2014 Freescale Semiconductor Inc.
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* Copyright 2012 - 2015 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@@ -41,6 +41,32 @@
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases{
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phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
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phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
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phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
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phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
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phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
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phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
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phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
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phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
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phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
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phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
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phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
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phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
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phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
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phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
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phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
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phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
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hydra_rg = &hydra_rg;
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hydra_sg_slot2 = &hydra_sg_slot2;
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hydra_sg_slot3 = &hydra_sg_slot3;
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hydra_sg_slot5 = &hydra_sg_slot5;
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hydra_sg_slot6 = &hydra_sg_slot6;
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hydra_xg_slot1 = &hydra_xg_slot1;
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hydra_xg_slot2 = &hydra_xg_slot2;
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};
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memory {
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device_type = "memory";
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};
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@@ -147,6 +173,62 @@
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reg = <0x4c>;
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};
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};
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fman@400000 {
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ethernet@e0000 {
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-connection-type = "sgmii";
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};
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ethernet@e8000 {
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phy-handle = <&phy_rgmii_0>;
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phy-connection-type = "rgmii";
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};
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ethernet@f0000 {
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phy-handle = <&phy_xgmii_slot_2>;
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phy-connection-type = "xgmii";
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};
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};
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fman@500000 {
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ethernet@e0000 {
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-connection-type = "sgmii";
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};
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ethernet@e8000 {
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phy-handle = <&phy_rgmii_1>;
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phy-connection-type = "rgmii";
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};
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ethernet@f0000 {
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phy-handle = <&phy_xgmii_slot_1>;
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phy-connection-type = "xgmii";
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};
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};
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};
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lbc: localbus@ffe124000 {
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@@ -200,8 +282,158 @@
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};
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board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
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reg = <3 0 0x40>;
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ranges = <0 3 0 0x40>;
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mdio-mux-emi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&mdio0>;
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reg = <9 1>;
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mux-mask = <0x78>;
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hydra_rg:rgmii-mdio@8 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <8>;
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status = "disabled";
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phy_rgmii_0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy_rgmii_1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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hydra_sg_slot2: sgmii-mdio@28 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x28>;
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status = "disabled";
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phy_sgmii_slot2_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_slot2_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_slot2_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_slot2_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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hydra_sg_slot3: sgmii-mdio@68 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x68>;
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status = "disabled";
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phy_sgmii_slot3_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_slot3_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_slot3_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_slot3_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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hydra_sg_slot5: sgmii-mdio@38 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x38>;
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status = "disabled";
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phy_sgmii_slot5_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_slot5_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_slot5_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_slot5_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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hydra_sg_slot6: sgmii-mdio@48 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x48>;
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status = "disabled";
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phy_sgmii_slot6_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_slot6_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_slot6_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_slot6_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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};
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mdio-mux-emi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&xmdio0>;
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reg = <9 1>;
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mux-mask = <0x06>;
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hydra_xg_slot1: hydra-xg-slot1@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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status = "disabled";
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phy_xgmii_slot_1: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <4>;
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};
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};
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hydra_xg_slot2: hydra-xg-slot2@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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phy_xgmii_slot_2: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0>;
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};
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};
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};
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};
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};
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