ARM: OMAP4: PM: Make OMAP3 Clock-domain framework compatible for OMAP4.
Here the ".clkstctrl_reg" field is added to the clockdomain stucture as the module offsets for OMAP4 do not map one to one for powerdomains and clockdomains as it used to for OMAP3. Hence we need to use absolute addresses to access the control registers. Some of the clock domains have modules falling in the address space of PRM partition. Hence necessitating the use of absolute adresses. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
This commit is contained in:
Abhijit Pagare
committed by
Paul Walmsley
Paul Walmsley
parent
3a759f09d7
commit
84c0c39aec
@@ -11,6 +11,8 @@
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#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
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#include <plat/clockdomain.h>
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#include "cm.h"
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#include "prm44xx.h"
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/*
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* OMAP2/3-common clockdomains
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@@ -50,6 +52,7 @@ static struct clockdomain mpu_2420_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clkstctrl_reg = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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@@ -58,11 +61,59 @@ static struct clockdomain iva1_2420_clkdm = {
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.name = "iva1_clkdm",
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.pwrdm = { .name = "dsp_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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#endif /* CONFIG_ARCH_OMAP2420 */
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static struct clockdomain dsp_2420_clkdm = {
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.name = "dsp_clkdm",
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.pwrdm = { .name = "dsp_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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static struct clockdomain gfx_2420_clkdm = {
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.name = "gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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static struct clockdomain core_l3_2420_clkdm = {
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.name = "core_l3_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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static struct clockdomain core_l4_2420_clkdm = {
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.name = "core_l4_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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static struct clockdomain dss_2420_clkdm = {
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.name = "dss_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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#endif /* CONFIG_ARCH_OMAP2420 */
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/*
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@@ -75,6 +126,8 @@ static struct clockdomain mpu_2430_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP2430_CM_REGADDR(MPU_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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@@ -83,60 +136,59 @@ static struct clockdomain mdm_clkdm = {
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.name = "mdm_clkdm",
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.pwrdm = { .name = "mdm_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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#endif /* CONFIG_ARCH_OMAP2430 */
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/*
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* 24XX-only clockdomains
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*/
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#if defined(CONFIG_ARCH_OMAP24XX)
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static struct clockdomain dsp_clkdm = {
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static struct clockdomain dsp_2430_clkdm = {
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.name = "dsp_clkdm",
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.pwrdm = { .name = "dsp_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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static struct clockdomain gfx_24xx_clkdm = {
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static struct clockdomain gfx_2430_clkdm = {
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.name = "gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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static struct clockdomain core_l3_24xx_clkdm = {
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static struct clockdomain core_l3_2430_clkdm = {
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.name = "core_l3_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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static struct clockdomain core_l4_24xx_clkdm = {
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static struct clockdomain core_l4_2430_clkdm = {
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.name = "core_l4_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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static struct clockdomain dss_24xx_clkdm = {
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static struct clockdomain dss_2430_clkdm = {
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.name = "dss_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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#endif /* CONFIG_ARCH_OMAP24XX */
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#endif /* CONFIG_ARCH_OMAP2430 */
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/*
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@@ -149,6 +201,7 @@ static struct clockdomain mpu_34xx_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -157,6 +210,8 @@ static struct clockdomain neon_clkdm = {
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.name = "neon_clkdm",
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.pwrdm = { .name = "neon_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -165,6 +220,8 @@ static struct clockdomain iva2_clkdm = {
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.name = "iva2_clkdm",
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.pwrdm = { .name = "iva2_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -173,6 +230,7 @@ static struct clockdomain gfx_3430es1_clkdm = {
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.name = "gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
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};
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@@ -181,6 +239,8 @@ static struct clockdomain sgx_clkdm = {
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.name = "sgx_clkdm",
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.pwrdm = { .name = "sgx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
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};
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@@ -196,6 +256,7 @@ static struct clockdomain d2d_clkdm = {
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.name = "d2d_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -204,6 +265,7 @@ static struct clockdomain core_l3_34xx_clkdm = {
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.name = "core_l3_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -212,6 +274,7 @@ static struct clockdomain core_l4_34xx_clkdm = {
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.name = "core_l4_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -220,6 +283,8 @@ static struct clockdomain dss_34xx_clkdm = {
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.name = "dss_clkdm",
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.pwrdm = { .name = "dss_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -228,6 +293,8 @@ static struct clockdomain cam_clkdm = {
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.name = "cam_clkdm",
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.pwrdm = { .name = "cam_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -236,6 +303,8 @@ static struct clockdomain usbhost_clkdm = {
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.name = "usbhost_clkdm",
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.pwrdm = { .name = "usbhost_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
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};
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@@ -244,6 +313,8 @@ static struct clockdomain per_clkdm = {
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.name = "per_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -256,6 +327,8 @@ static struct clockdomain emu_clkdm = {
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.name = "emu_clkdm",
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.pwrdm = { .name = "emu_pwrdm" },
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.flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
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.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
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OMAP2_CM_CLKSTCTRL),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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@@ -323,19 +396,21 @@ static struct clockdomain *clockdomains_omap[] = {
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#ifdef CONFIG_ARCH_OMAP2420
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&mpu_2420_clkdm,
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&iva1_2420_clkdm,
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&dsp_2420_clkdm,
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&gfx_2420_clkdm,
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&core_l3_2420_clkdm,
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&core_l4_2420_clkdm,
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&dss_2420_clkdm,
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#endif
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#ifdef CONFIG_ARCH_OMAP2430
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&mpu_2430_clkdm,
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&mdm_clkdm,
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#endif
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#ifdef CONFIG_ARCH_OMAP24XX
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&dsp_clkdm,
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&gfx_24xx_clkdm,
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&core_l3_24xx_clkdm,
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&core_l4_24xx_clkdm,
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&dss_24xx_clkdm,
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&dsp_2430_clkdm,
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&gfx_2430_clkdm,
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&core_l3_2430_clkdm,
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&core_l4_2430_clkdm,
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&dss_2430_clkdm,
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#endif
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#ifdef CONFIG_ARCH_OMAP34XX
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