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MIPS: Emulate the new MIPS R6 branch compact (BC) instruction

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MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras
2014-11-26 13:56:51 +00:00
parent f1b44067c1
commit 8467ca0122
3 changed files with 23 additions and 1 deletions
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2
arch/mips/include/uapi/asm/inst.h
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@@ -31,7 +31,7 @@ enum major_op {
lbu_op, lhu_op, lwr_op, lwu_op,
sb_op, sh_op, swl_op, sw_op,
sdl_op, sdr_op, swr_op, cache_op,
ll_op, lwc1_op, lwc2_op, pref_op,
ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
lld_op, ldc1_op, ldc2_op, ld_op,
sc_op, swc1_op, swc2_op, major_3b_op,
scd_op, sdc1_op, sdc2_op, sd_op