drm/radeon: Add CP init for CIK (v7)
Sets up the GFX ring and loads ucode for GFX and Compute. Todo: - handle compute queue setup. v2: add documentation v3: integrate with latest reset changes v4: additional init fixes v5: scratch reg write back no longer supported on CIK v6: properly set CP_RB0_BASE_HI v7: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
@@ -263,11 +263,18 @@
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#define MEC_ME2_HALT (1 << 28)
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#define MEC_ME1_HALT (1 << 30)
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#define CP_MEC_CNTL 0x8234
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#define MEC_ME2_HALT (1 << 28)
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#define MEC_ME1_HALT (1 << 30)
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#define CP_ME_CNTL 0x86D8
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#define CP_CE_HALT (1 << 24)
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#define CP_PFP_HALT (1 << 26)
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#define CP_ME_HALT (1 << 28)
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#define CP_RB0_RPTR 0x8700
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#define CP_RB_WPTR_DELAY 0x8704
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#define CP_MEQ_THRESHOLDS 0x8764
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#define MEQ1_START(x) ((x) << 0)
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#define MEQ2_START(x) ((x) << 8)
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@@ -445,12 +452,62 @@
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#define TC_CFG_L1_VOLATILE 0xAC88
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#define TC_CFG_L2_VOLATILE 0xAC8C
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#define CP_RB0_BASE 0xC100
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#define CP_RB0_CNTL 0xC104
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#define RB_BUFSZ(x) ((x) << 0)
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#define RB_BLKSZ(x) ((x) << 8)
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#define BUF_SWAP_32BIT (2 << 16)
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#define RB_NO_UPDATE (1 << 27)
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#define RB_RPTR_WR_ENA (1 << 31)
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#define CP_RB0_RPTR_ADDR 0xC10C
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#define RB_RPTR_SWAP_32BIT (2 << 0)
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#define CP_RB0_RPTR_ADDR_HI 0xC110
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#define CP_RB0_WPTR 0xC114
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#define CP_DEVICE_ID 0xC12C
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#define CP_ENDIAN_SWAP 0xC140
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#define CP_RB_VMID 0xC144
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#define CP_PFP_UCODE_ADDR 0xC150
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#define CP_PFP_UCODE_DATA 0xC154
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#define CP_ME_RAM_RADDR 0xC158
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#define CP_ME_RAM_WADDR 0xC15C
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#define CP_ME_RAM_DATA 0xC160
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#define CP_CE_UCODE_ADDR 0xC168
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#define CP_CE_UCODE_DATA 0xC16C
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#define CP_MEC_ME1_UCODE_ADDR 0xC170
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#define CP_MEC_ME1_UCODE_DATA 0xC174
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#define CP_MEC_ME2_UCODE_ADDR 0xC178
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#define CP_MEC_ME2_UCODE_DATA 0xC17C
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#define CP_MAX_CONTEXT 0xC2B8
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#define CP_RB0_BASE_HI 0xC2C4
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#define PA_SC_RASTER_CONFIG 0x28350
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# define RASTER_CONFIG_RB_MAP_0 0
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# define RASTER_CONFIG_RB_MAP_1 1
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# define RASTER_CONFIG_RB_MAP_2 2
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# define RASTER_CONFIG_RB_MAP_3 3
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#define SCRATCH_REG0 0x30100
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#define SCRATCH_REG1 0x30104
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#define SCRATCH_REG2 0x30108
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#define SCRATCH_REG3 0x3010C
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#define SCRATCH_REG4 0x30110
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#define SCRATCH_REG5 0x30114
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#define SCRATCH_REG6 0x30118
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#define SCRATCH_REG7 0x3011C
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#define SCRATCH_UMSK 0x30140
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#define SCRATCH_ADDR 0x30144
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#define CP_SEM_WAIT_TIMER 0x301BC
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#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
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#define GRBM_GFX_INDEX 0x30800
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#define INSTANCE_INDEX(x) ((x) << 0)
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#define SH_INDEX(x) ((x) << 8)
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@@ -482,4 +539,169 @@
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#define TCC_DISABLE_MASK 0xFFFF0000
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#define TCC_DISABLE_SHIFT 16
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/*
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* PM4
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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(((reg) >> 2) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
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#define CP_PACKET2 0x80000000
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#define PACKET2_PAD_SHIFT 0
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#define PACKET2_PAD_MASK (0x3fffffff << 0)
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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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/* Packet 3 types */
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#define PACKET3_NOP 0x10
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#define PACKET3_SET_BASE 0x11
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#define PACKET3_BASE_INDEX(x) ((x) << 0)
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#define CE_PARTITION_BASE 3
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#define PACKET3_CLEAR_STATE 0x12
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#define PACKET3_INDEX_BUFFER_SIZE 0x13
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#define PACKET3_DISPATCH_DIRECT 0x15
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#define PACKET3_DISPATCH_INDIRECT 0x16
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#define PACKET3_ATOMIC_GDS 0x1D
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#define PACKET3_ATOMIC_MEM 0x1E
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#define PACKET3_OCCLUSION_QUERY 0x1F
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#define PACKET3_SET_PREDICATION 0x20
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#define PACKET3_REG_RMW 0x21
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#define PACKET3_COND_EXEC 0x22
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#define PACKET3_PRED_EXEC 0x23
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#define PACKET3_DRAW_INDIRECT 0x24
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#define PACKET3_DRAW_INDEX_INDIRECT 0x25
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#define PACKET3_INDEX_BASE 0x26
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#define PACKET3_DRAW_INDEX_2 0x27
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#define PACKET3_CONTEXT_CONTROL 0x28
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#define PACKET3_INDEX_TYPE 0x2A
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#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
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#define PACKET3_DRAW_INDEX_AUTO 0x2D
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#define PACKET3_NUM_INSTANCES 0x2F
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#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
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#define PACKET3_INDIRECT_BUFFER_CONST 0x33
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#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
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#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
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#define PACKET3_DRAW_PREAMBLE 0x36
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#define PACKET3_WRITE_DATA 0x37
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#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
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#define PACKET3_MEM_SEMAPHORE 0x39
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#define PACKET3_COPY_DW 0x3B
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define PACKET3_INDIRECT_BUFFER 0x3F
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#define PACKET3_COPY_DATA 0x40
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#define PACKET3_PFP_SYNC_ME 0x42
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#define PACKET3_SURFACE_SYNC 0x43
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# define PACKET3_DEST_BASE_0_ENA (1 << 0)
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# define PACKET3_DEST_BASE_1_ENA (1 << 1)
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
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# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
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# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
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# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
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# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
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# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
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# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
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# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
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# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
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# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
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# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
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# define PACKET3_DEST_BASE_2_ENA (1 << 19)
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# define PACKET3_DEST_BASE_3_ENA (1 << 21)
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# define PACKET3_TCL1_ACTION_ENA (1 << 22)
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# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
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# define PACKET3_CB_ACTION_ENA (1 << 25)
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# define PACKET3_DB_ACTION_ENA (1 << 26)
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# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
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# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
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# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
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#define PACKET3_COND_WRITE 0x45
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#define PACKET3_EVENT_WRITE 0x46
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#define EVENT_TYPE(x) ((x) << 0)
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#define EVENT_INDEX(x) ((x) << 8)
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/* 0 - any non-TS event
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* 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
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* 2 - SAMPLE_PIPELINESTAT
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* 3 - SAMPLE_STREAMOUTSTAT*
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* 4 - *S_PARTIAL_FLUSH
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* 5 - EOP events
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* 6 - EOS events
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*/
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#define PACKET3_EVENT_WRITE_EOP 0x47
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#define EOP_TCL1_VOL_ACTION_EN (1 << 12)
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#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
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#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
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#define EOP_TCL1_ACTION_EN (1 << 16)
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#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
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#define CACHE_POLICY(x) ((x) << 25)
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/* 0 - LRU
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* 1 - Stream
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* 2 - Bypass
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*/
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#define TCL2_VOLATILE (1 << 27)
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#define DATA_SEL(x) ((x) << 29)
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/* 0 - discard
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* 1 - send low 32bit data
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* 2 - send 64bit data
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* 3 - send 64bit GPU counter value
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* 4 - send 64bit sys counter value
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*/
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#define INT_SEL(x) ((x) << 24)
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/* 0 - none
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* 1 - interrupt only (DATA_SEL = 0)
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* 2 - interrupt when data write is confirmed
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*/
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#define DST_SEL(x) ((x) << 16)
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/* 0 - MC
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* 1 - TC/L2
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*/
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#define PACKET3_EVENT_WRITE_EOS 0x48
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#define PACKET3_RELEASE_MEM 0x49
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#define PACKET3_PREAMBLE_CNTL 0x4A
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# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
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# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
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#define PACKET3_DMA_DATA 0x50
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#define PACKET3_AQUIRE_MEM 0x58
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#define PACKET3_REWIND 0x59
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#define PACKET3_LOAD_UCONFIG_REG 0x5E
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#define PACKET3_LOAD_SH_REG 0x5F
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#define PACKET3_LOAD_CONFIG_REG 0x60
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#define PACKET3_LOAD_CONTEXT_REG 0x61
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#define PACKET3_SET_CONFIG_REG 0x68
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#define PACKET3_SET_CONFIG_REG_START 0x00008000
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#define PACKET3_SET_CONFIG_REG_END 0x0000b000
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#define PACKET3_SET_CONTEXT_REG 0x69
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#define PACKET3_SET_CONTEXT_REG_START 0x00028000
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#define PACKET3_SET_CONTEXT_REG_END 0x00029000
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#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
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#define PACKET3_SET_SH_REG 0x76
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#define PACKET3_SET_SH_REG_START 0x0000b000
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#define PACKET3_SET_SH_REG_END 0x0000c000
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#define PACKET3_SET_SH_REG_OFFSET 0x77
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#define PACKET3_SET_QUEUE_REG 0x78
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#define PACKET3_SET_UCONFIG_REG 0x79
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#define PACKET3_SCRATCH_RAM_WRITE 0x7D
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#define PACKET3_SCRATCH_RAM_READ 0x7E
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#define PACKET3_LOAD_CONST_RAM 0x80
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#define PACKET3_WRITE_CONST_RAM 0x81
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#define PACKET3_DUMP_CONST_RAM 0x83
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#define PACKET3_INCREMENT_CE_COUNTER 0x84
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#define PACKET3_INCREMENT_DE_COUNTER 0x85
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#define PACKET3_WAIT_ON_CE_COUNTER 0x86
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#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
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#endif
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