Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
reset: remove redundant null check on pointer dev
soc: rockchip: work around clang warning
dt-bindings: reset: imx7: Fix the spelling of 'indices'
soc: imx: Add i.MX8MN SoC driver support
soc: aspeed: lpc-ctrl: Fix probe error handling
soc: qcom: geni: Add support for ACPI
firmware: ti_sci: Fix gcc unused-but-set-variable warning
firmware: ti_sci: Use the correct style for SPDX License Identifier
soc: imx8: Use existing of_root directly
soc: imx8: Fix potential kernel dump in error path
firmware/psci: psci_checker: Park kthreads before stopping them
memory: move jedec_ddr.h from include/memory to drivers/memory/
memory: move jedec_ddr_data.c from lib/ to drivers/memory/
MAINTAINERS: Remove myself as qcom maintainer
soc: aspeed: lpc-ctrl: make parameter optional
soc: qcom: apr: Don't use reg for domain id
soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
memory: tegra: Fix -Wunused-const-variable
firmware: tegra: Early resume BPMP
soc/tegra: Select pinctrl for Tegra194
...
This commit is contained in:
Linus Torvalds
@@ -42,6 +42,43 @@
|
||||
#define TI_SCI_MSG_SET_IRQ 0x1000
|
||||
#define TI_SCI_MSG_FREE_IRQ 0x1001
|
||||
|
||||
/* NAVSS resource management */
|
||||
/* Ringacc requests */
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#define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100
|
||||
#define TI_SCI_MSG_RM_RING_FREE 0x1101
|
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#define TI_SCI_MSG_RM_RING_RECONFIG 0x1102
|
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#define TI_SCI_MSG_RM_RING_RESET 0x1103
|
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#define TI_SCI_MSG_RM_RING_CFG 0x1110
|
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#define TI_SCI_MSG_RM_RING_GET_CFG 0x1111
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|
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/* PSI-L requests */
|
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#define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
|
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#define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
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#define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
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#define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
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#define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
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#define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
|
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#define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
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#define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
|
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#define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
|
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#define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206
|
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#define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
|
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#define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216
|
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#define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
|
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#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
|
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#define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232
|
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#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233
|
||||
|
||||
/* Processor Control requests */
|
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#define TI_SCI_MSG_PROC_REQUEST 0xc000
|
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#define TI_SCI_MSG_PROC_RELEASE 0xc001
|
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#define TI_SCI_MSG_PROC_HANDOVER 0xc005
|
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#define TI_SCI_MSG_SET_CONFIG 0xc100
|
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#define TI_SCI_MSG_SET_CTRL 0xc101
|
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#define TI_SCI_MSG_GET_STATUS 0xc400
|
||||
|
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/**
|
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* struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
|
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* @type: Type of messages: One of TI_SCI_MSG* values
|
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@@ -604,4 +641,777 @@ struct ti_sci_msg_req_manage_irq {
|
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u8 secondary_host;
|
||||
} __packed;
|
||||
|
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/**
|
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* struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
|
||||
*
|
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* Configures the non-real-time registers of a Navigator Subsystem ring.
|
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* @hdr: Generic Header
|
||||
* @valid_params: Bitfield defining validity of ring configuration parameters.
|
||||
* The ring configuration fields are not valid, and will not be used for
|
||||
* ring configuration, if their corresponding valid bit is zero.
|
||||
* Valid bit usage:
|
||||
* 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
|
||||
* 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
|
||||
* 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
|
||||
* 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
|
||||
* 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
|
||||
* 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
|
||||
* @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
|
||||
* @index: ring index to be configured.
|
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* @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
|
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* RING_BA_LO register
|
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* @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
|
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* RING_BA_HI register.
|
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* @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
|
||||
* modes.
|
||||
* @mode: Specifies the mode the ring is to be configured.
|
||||
* @size: Specifies encoded ring element size. To calculate the encoded size use
|
||||
* the formula (log2(size_bytes) - 2), where size_bytes cannot be
|
||||
* greater than 256.
|
||||
* @order_id: Specifies the ring's bus order ID.
|
||||
*/
|
||||
struct ti_sci_msg_rm_ring_cfg_req {
|
||||
struct ti_sci_msg_hdr hdr;
|
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u32 valid_params;
|
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u16 nav_id;
|
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u16 index;
|
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u32 addr_lo;
|
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u32 addr_hi;
|
||||
u32 count;
|
||||
u8 mode;
|
||||
u8 size;
|
||||
u8 order_id;
|
||||
} __packed;
|
||||
|
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/**
|
||||
* struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
|
||||
*
|
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* Gets the configuration of the non-real-time register fields of a ring. The
|
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* host, or a supervisor of the host, who owns the ring must be the requesting
|
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* host. The values of the non-real-time registers are returned in
|
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* @ti_sci_msg_rm_ring_get_cfg_resp.
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*
|
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* @hdr: Generic Header
|
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* @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
|
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* @index: ring index.
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*/
|
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struct ti_sci_msg_rm_ring_get_cfg_req {
|
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struct ti_sci_msg_hdr hdr;
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
} __packed;
|
||||
|
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/**
|
||||
* struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
|
||||
*
|
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* Response received by host processor after RM has handled
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* @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
|
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* non-real-time register values.
|
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*
|
||||
* @hdr: Generic Header
|
||||
* @addr_lo: Ring 32 LSBs of base address
|
||||
* @addr_hi: Ring 16 MSBs of base address.
|
||||
* @count: Ring number of elements.
|
||||
* @mode: Ring mode.
|
||||
* @size: encoded Ring element size
|
||||
* @order_id: ing order ID.
|
||||
*/
|
||||
struct ti_sci_msg_rm_ring_get_cfg_resp {
|
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struct ti_sci_msg_hdr hdr;
|
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u32 addr_lo;
|
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u32 addr_hi;
|
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u32 count;
|
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u8 mode;
|
||||
u8 size;
|
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u8 order_id;
|
||||
} __packed;
|
||||
|
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/**
|
||||
* struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
|
||||
* thread
|
||||
* @hdr: Generic Header
|
||||
* @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
|
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* used to pair the source and destination threads.
|
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* @src_thread: PSI-L source thread ID within the PSI-L System thread map.
|
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*
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* UDMAP transmit channels mapped to source threads will have their
|
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* TCHAN_THRD_ID register programmed with the destination thread if the pairing
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* is successful.
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* @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
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* PSI-L destination threads start at index 0x8000. The request is NACK'd if
|
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* the destination thread is not greater than or equal to 0x8000.
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*
|
||||
* UDMAP receive channels mapped to destination threads will have their
|
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* RCHAN_THRD_ID register programmed with the source thread if the pairing
|
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* is successful.
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*
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* Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
|
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* message.
|
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*/
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struct ti_sci_msg_psil_pair {
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struct ti_sci_msg_hdr hdr;
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u32 nav_id;
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u32 src_thread;
|
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u32 dst_thread;
|
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} __packed;
|
||||
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||||
/**
|
||||
* struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
|
||||
* destination thread
|
||||
* @hdr: Generic Header
|
||||
* @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
|
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* used to unpair the source and destination threads.
|
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* @src_thread: PSI-L source thread ID within the PSI-L System thread map.
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*
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* UDMAP transmit channels mapped to source threads will have their
|
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* TCHAN_THRD_ID register cleared if the unpairing is successful.
|
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*
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* @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
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||||
* PSI-L destination threads start at index 0x8000. The request is NACK'd if
|
||||
* the destination thread is not greater than or equal to 0x8000.
|
||||
*
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||||
* UDMAP receive channels mapped to destination threads will have their
|
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* RCHAN_THRD_ID register cleared if the unpairing is successful.
|
||||
*
|
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* Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
|
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* message.
|
||||
*/
|
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struct ti_sci_msg_psil_unpair {
|
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struct ti_sci_msg_hdr hdr;
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||||
u32 nav_id;
|
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u32 src_thread;
|
||||
u32 dst_thread;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration
|
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* message
|
||||
* @hdr: Generic Header
|
||||
* @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
|
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* allocated
|
||||
* @flow_index: UDMAP receive flow index for non-optional configuration.
|
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* @rx_ch_index: Specifies the index of the receive channel using the flow_index
|
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* @rx_einfo_present: UDMAP receive flow extended packet info present.
|
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* @rx_psinfo_present: UDMAP receive flow PS words present.
|
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* @rx_error_handling: UDMAP receive flow error handling configuration. Valid
|
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* values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY.
|
||||
* @rx_desc_type: UDMAP receive flow descriptor type. It can be one of
|
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* TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO.
|
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* @rx_sop_offset: UDMAP receive flow start of packet offset.
|
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* @rx_dest_qnum: UDMAP receive flow destination queue number.
|
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* @rx_ps_location: UDMAP receive flow PS words location.
|
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* 0 - end of packet descriptor
|
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* 1 - Beginning of the data buffer
|
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* @rx_src_tag_hi: UDMAP receive flow source tag high byte constant
|
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* @rx_src_tag_lo: UDMAP receive flow source tag low byte constant
|
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* @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant
|
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* @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant
|
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* @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector
|
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* @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector
|
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* @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector
|
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* @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector
|
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* @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue
|
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* enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be
|
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* configured and sent.
|
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* @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0.
|
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* @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1.
|
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* @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2.
|
||||
* @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3.
|
||||
*
|
||||
* For detailed information on the settings, see the UDMAP section of the TRM.
|
||||
*/
|
||||
struct ti_sci_msg_udmap_rx_flow_cfg {
|
||||
struct ti_sci_msg_hdr hdr;
|
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u32 nav_id;
|
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u32 flow_index;
|
||||
u32 rx_ch_index;
|
||||
u8 rx_einfo_present;
|
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u8 rx_psinfo_present;
|
||||
u8 rx_error_handling;
|
||||
u8 rx_desc_type;
|
||||
u16 rx_sop_offset;
|
||||
u16 rx_dest_qnum;
|
||||
u8 rx_ps_location;
|
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u8 rx_src_tag_hi;
|
||||
u8 rx_src_tag_lo;
|
||||
u8 rx_dest_tag_hi;
|
||||
u8 rx_dest_tag_lo;
|
||||
u8 rx_src_tag_hi_sel;
|
||||
u8 rx_src_tag_lo_sel;
|
||||
u8 rx_dest_tag_hi_sel;
|
||||
u8 rx_dest_tag_lo_sel;
|
||||
u8 rx_size_thresh_en;
|
||||
u16 rx_fdq0_sz0_qnum;
|
||||
u16 rx_fdq1_qnum;
|
||||
u16 rx_fdq2_qnum;
|
||||
u16 rx_fdq3_qnum;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive
|
||||
* flow optional configuration
|
||||
* @hdr: Generic Header
|
||||
* @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
|
||||
* allocated
|
||||
* @flow_index: UDMAP receive flow index for optional configuration.
|
||||
* @rx_ch_index: Specifies the index of the receive channel using the flow_index
|
||||
* @rx_size_thresh0: UDMAP receive flow packet size threshold 0.
|
||||
* @rx_size_thresh1: UDMAP receive flow packet size threshold 1.
|
||||
* @rx_size_thresh2: UDMAP receive flow packet size threshold 2.
|
||||
* @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size
|
||||
* threshold 1.
|
||||
* @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size
|
||||
* threshold 2.
|
||||
* @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size
|
||||
* threshold 3.
|
||||
*
|
||||
* For detailed information on the settings, see the UDMAP section of the TRM.
|
||||
*/
|
||||
struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u32 nav_id;
|
||||
u32 flow_index;
|
||||
u32 rx_ch_index;
|
||||
u16 rx_size_thresh0;
|
||||
u16 rx_size_thresh1;
|
||||
u16 rx_size_thresh2;
|
||||
u16 rx_fdq0_sz1_qnum;
|
||||
u16 rx_fdq0_sz2_qnum;
|
||||
u16 rx_fdq0_sz3_qnum;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* Configures a Navigator Subsystem UDMAP transmit channel
|
||||
*
|
||||
* Configures the non-real-time registers of a Navigator Subsystem UDMAP
|
||||
* transmit channel. The channel index must be assigned to the host defined
|
||||
* in the TISCI header via the RM board configuration resource assignment
|
||||
* range list.
|
||||
*
|
||||
* @hdr: Generic Header
|
||||
*
|
||||
* @valid_params: Bitfield defining validity of tx channel configuration
|
||||
* parameters. The tx channel configuration fields are not valid, and will not
|
||||
* be used for ch configuration, if their corresponding valid bit is zero.
|
||||
* Valid bit usage:
|
||||
* 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
|
||||
* 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
|
||||
* 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
|
||||
* 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
|
||||
* 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
|
||||
* 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
|
||||
* 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
|
||||
* 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
|
||||
* 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
|
||||
* 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
|
||||
* 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
|
||||
* 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
|
||||
* 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
|
||||
* 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
|
||||
* 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
|
||||
*
|
||||
* @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
|
||||
*
|
||||
* @index: UDMAP transmit channel index.
|
||||
*
|
||||
* @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
|
||||
* be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
|
||||
* register.
|
||||
*
|
||||
* @tx_filt_einfo: UDMAP transmit channel extended packet information passing
|
||||
* configuration to be programmed into the tx_filt_einfo field of the
|
||||
* channel's TCHAN_TCFG register.
|
||||
*
|
||||
* @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
|
||||
* configuration to be programmed into the tx_filt_pswords field of the
|
||||
* channel's TCHAN_TCFG register.
|
||||
*
|
||||
* @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
|
||||
* interpretation configuration to be programmed into the tx_atype field of
|
||||
* the channel's TCHAN_TCFG register.
|
||||
*
|
||||
* @tx_chan_type: UDMAP transmit channel functional channel type and work
|
||||
* passing mechanism configuration to be programmed into the tx_chan_type
|
||||
* field of the channel's TCHAN_TCFG register.
|
||||
*
|
||||
* @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
|
||||
* configuration to be programmed into the tx_supr_tdpkt field of the channel's
|
||||
* TCHAN_TCFG register.
|
||||
*
|
||||
* @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
|
||||
* fetch configuration to be programmed into the tx_fetch_size field of the
|
||||
* channel's TCHAN_TCFG register. The user must make sure to set the maximum
|
||||
* word count that can pass through the channel for any allowed descriptor type.
|
||||
*
|
||||
* @tx_credit_count: UDMAP transmit channel transfer request credit count
|
||||
* configuration to be programmed into the count field of the TCHAN_TCREDIT
|
||||
* register. Specifies how many credits for complete TRs are available.
|
||||
*
|
||||
* @txcq_qnum: UDMAP transmit channel completion queue configuration to be
|
||||
* programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
|
||||
* completion queue must be assigned to the host, or a subordinate of the host,
|
||||
* requesting configuration of the transmit channel.
|
||||
*
|
||||
* @tx_priority: UDMAP transmit channel transmit priority value to be programmed
|
||||
* into the priority field of the channel's TCHAN_TPRI_CTRL register.
|
||||
*
|
||||
* @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
|
||||
* qos field of the channel's TCHAN_TPRI_CTRL register.
|
||||
*
|
||||
* @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
|
||||
* the orderid field of the channel's TCHAN_TPRI_CTRL register.
|
||||
*
|
||||
* @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
|
||||
* into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
|
||||
* Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
|
||||
* section of the TRM for restrictions regarding this parameter.
|
||||
*
|
||||
* @tx_sched_priority: UDMAP transmit channel tx scheduling priority
|
||||
* configuration to be programmed into the priority field of the channel's
|
||||
* TCHAN_TST_SCHED register.
|
||||
*
|
||||
* @tx_burst_size: UDMAP transmit channel burst size configuration to be
|
||||
* programmed into the tx_burst_size field of the TCHAN_TCFG register.
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u32 valid_params;
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
u8 tx_pause_on_err;
|
||||
u8 tx_filt_einfo;
|
||||
u8 tx_filt_pswords;
|
||||
u8 tx_atype;
|
||||
u8 tx_chan_type;
|
||||
u8 tx_supr_tdpkt;
|
||||
u16 tx_fetch_size;
|
||||
u8 tx_credit_count;
|
||||
u16 txcq_qnum;
|
||||
u8 tx_priority;
|
||||
u8 tx_qos;
|
||||
u8 tx_orderid;
|
||||
u16 fdepth;
|
||||
u8 tx_sched_priority;
|
||||
u8 tx_burst_size;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* Configures a Navigator Subsystem UDMAP receive channel
|
||||
*
|
||||
* Configures the non-real-time registers of a Navigator Subsystem UDMAP
|
||||
* receive channel. The channel index must be assigned to the host defined
|
||||
* in the TISCI header via the RM board configuration resource assignment
|
||||
* range list.
|
||||
*
|
||||
* @hdr: Generic Header
|
||||
*
|
||||
* @valid_params: Bitfield defining validity of rx channel configuration
|
||||
* parameters.
|
||||
* The rx channel configuration fields are not valid, and will not be used for
|
||||
* ch configuration, if their corresponding valid bit is zero.
|
||||
* Valid bit usage:
|
||||
* 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
|
||||
* 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
|
||||
* 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
|
||||
* 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
|
||||
* 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
|
||||
* 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
|
||||
* 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
|
||||
* 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
|
||||
* 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
|
||||
* 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
|
||||
* 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
|
||||
* 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
|
||||
* 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
|
||||
* 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
|
||||
*
|
||||
* @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
|
||||
*
|
||||
* @index: UDMAP receive channel index.
|
||||
*
|
||||
* @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
|
||||
* fetch configuration to be programmed into the rx_fetch_size field of the
|
||||
* channel's RCHAN_RCFG register.
|
||||
*
|
||||
* @rxcq_qnum: UDMAP receive channel completion queue configuration to be
|
||||
* programmed into the rxcq_qnum field of the RCHAN_RCQ register.
|
||||
* The specified completion queue must be assigned to the host, or a subordinate
|
||||
* of the host, requesting configuration of the receive channel.
|
||||
*
|
||||
* @rx_priority: UDMAP receive channel receive priority value to be programmed
|
||||
* into the priority field of the channel's RCHAN_RPRI_CTRL register.
|
||||
*
|
||||
* @rx_qos: UDMAP receive channel receive qos value to be programmed into the
|
||||
* qos field of the channel's RCHAN_RPRI_CTRL register.
|
||||
*
|
||||
* @rx_orderid: UDMAP receive channel bus order id value to be programmed into
|
||||
* the orderid field of the channel's RCHAN_RPRI_CTRL register.
|
||||
*
|
||||
* @rx_sched_priority: UDMAP receive channel rx scheduling priority
|
||||
* configuration to be programmed into the priority field of the channel's
|
||||
* RCHAN_RST_SCHED register.
|
||||
*
|
||||
* @flowid_start: UDMAP receive channel additional flows starting index
|
||||
* configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
|
||||
* register. Specifies the starting index for flow IDs the receive channel is to
|
||||
* make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
|
||||
* set as valid and configured together. The starting flow ID set by
|
||||
* @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
|
||||
* of flows beyond the default flows statically mapped to receive channels.
|
||||
* The additional flows must be assigned to the host, or a subordinate of the
|
||||
* host, requesting configuration of the receive channel.
|
||||
*
|
||||
* @flowid_cnt: UDMAP receive channel additional flows count configuration to
|
||||
* program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
|
||||
* This field specifies how many flow IDs are in the additional contiguous range
|
||||
* of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
|
||||
* set as valid and configured together. Disabling the valid_params field bit
|
||||
* for flowid_cnt indicates no flow IDs other than the default are to be
|
||||
* allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
|
||||
* cannot be greater than the number of receive flows in the receive channel's
|
||||
* Navigator Subsystem. The additional flows must be assigned to the host, or a
|
||||
* subordinate of the host, requesting configuration of the receive channel.
|
||||
*
|
||||
* @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
|
||||
* programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
|
||||
* register.
|
||||
*
|
||||
* @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
|
||||
* interpretation configuration to be programmed into the rx_atype field of the
|
||||
* channel's RCHAN_RCFG register.
|
||||
*
|
||||
* @rx_chan_type: UDMAP receive channel functional channel type and work passing
|
||||
* mechanism configuration to be programmed into the rx_chan_type field of the
|
||||
* channel's RCHAN_RCFG register.
|
||||
*
|
||||
* @rx_ignore_short: UDMAP receive channel short packet treatment configuration
|
||||
* to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
|
||||
*
|
||||
* @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
|
||||
* be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
|
||||
*
|
||||
* @rx_burst_size: UDMAP receive channel burst size configuration to be
|
||||
* programmed into the rx_burst_size field of the RCHAN_RCFG register.
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u32 valid_params;
|
||||
u16 nav_id;
|
||||
u16 index;
|
||||
u16 rx_fetch_size;
|
||||
u16 rxcq_qnum;
|
||||
u8 rx_priority;
|
||||
u8 rx_qos;
|
||||
u8 rx_orderid;
|
||||
u8 rx_sched_priority;
|
||||
u16 flowid_start;
|
||||
u16 flowid_cnt;
|
||||
u8 rx_pause_on_err;
|
||||
u8 rx_atype;
|
||||
u8 rx_chan_type;
|
||||
u8 rx_ignore_short;
|
||||
u8 rx_ignore_long;
|
||||
u8 rx_burst_size;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* Configures a Navigator Subsystem UDMAP receive flow
|
||||
*
|
||||
* Configures a Navigator Subsystem UDMAP receive flow's registers.
|
||||
* Configuration does not include the flow registers which handle size-based
|
||||
* free descriptor queue routing.
|
||||
*
|
||||
* The flow index must be assigned to the host defined in the TISCI header via
|
||||
* the RM board configuration resource assignment range list.
|
||||
*
|
||||
* @hdr: Standard TISCI header
|
||||
*
|
||||
* @valid_params
|
||||
* Bitfield defining validity of rx flow configuration parameters. The
|
||||
* rx flow configuration fields are not valid, and will not be used for flow
|
||||
* configuration, if their corresponding valid bit is zero. Valid bit usage:
|
||||
* 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
|
||||
* 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
|
||||
* 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
|
||||
* 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
|
||||
* 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
|
||||
* 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
|
||||
* 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
|
||||
* 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
|
||||
* 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
|
||||
* 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
|
||||
* 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
|
||||
* 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
|
||||
* 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
|
||||
* 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
|
||||
* 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
|
||||
* 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
|
||||
* 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
|
||||
* 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
|
||||
* 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
|
||||
*
|
||||
* @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
|
||||
* allocated
|
||||
*
|
||||
* @flow_index: UDMAP receive flow index for non-optional configuration.
|
||||
*
|
||||
* @rx_einfo_present:
|
||||
* UDMAP receive flow extended packet info present configuration to be
|
||||
* programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
|
||||
*
|
||||
* @rx_psinfo_present:
|
||||
* UDMAP receive flow PS words present configuration to be programmed into the
|
||||
* rx_psinfo_present field of the flow's RFLOW_RFA register.
|
||||
*
|
||||
* @rx_error_handling:
|
||||
* UDMAP receive flow error handling configuration to be programmed into the
|
||||
* rx_error_handling field of the flow's RFLOW_RFA register.
|
||||
*
|
||||
* @rx_desc_type:
|
||||
* UDMAP receive flow descriptor type configuration to be programmed into the
|
||||
* rx_desc_type field field of the flow's RFLOW_RFA register.
|
||||
*
|
||||
* @rx_sop_offset:
|
||||
* UDMAP receive flow start of packet offset configuration to be programmed
|
||||
* into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
|
||||
* section of the TRM for more information on this setting. Valid values for
|
||||
* this field are 0-255 bytes.
|
||||
*
|
||||
* @rx_dest_qnum:
|
||||
* UDMAP receive flow destination queue configuration to be programmed into the
|
||||
* rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
|
||||
* destination queue must be valid within the Navigator Subsystem and must be
|
||||
* owned by the host, or a subordinate of the host, requesting allocation and
|
||||
* configuration of the receive flow.
|
||||
*
|
||||
* @rx_src_tag_hi:
|
||||
* UDMAP receive flow source tag high byte constant configuration to be
|
||||
* programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
|
||||
* See the UDMAP section of the TRM for more information on this setting.
|
||||
*
|
||||
* @rx_src_tag_lo:
|
||||
* UDMAP receive flow source tag low byte constant configuration to be
|
||||
* programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
|
||||
* See the UDMAP section of the TRM for more information on this setting.
|
||||
*
|
||||
* @rx_dest_tag_hi:
|
||||
* UDMAP receive flow destination tag high byte constant configuration to be
|
||||
* programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
|
||||
* See the UDMAP section of the TRM for more information on this setting.
|
||||
*
|
||||
* @rx_dest_tag_lo:
|
||||
* UDMAP receive flow destination tag low byte constant configuration to be
|
||||
* programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
|
||||
* See the UDMAP section of the TRM for more information on this setting.
|
||||
*
|
||||
* @rx_src_tag_hi_sel:
|
||||
* UDMAP receive flow source tag high byte selector configuration to be
|
||||
* programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
|
||||
* the UDMAP section of the TRM for more information on this setting.
|
||||
*
|
||||
* @rx_src_tag_lo_sel:
|
||||
* UDMAP receive flow source tag low byte selector configuration to be
|
||||
* programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
|
||||
* the UDMAP section of the TRM for more information on this setting.
|
||||
*
|
||||
* @rx_dest_tag_hi_sel:
|
||||
* UDMAP receive flow destination tag high byte selector configuration to be
|
||||
* programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
|
||||
* the UDMAP section of the TRM for more information on this setting.
|
||||
*
|
||||
* @rx_dest_tag_lo_sel:
|
||||
* UDMAP receive flow destination tag low byte selector configuration to be
|
||||
* programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
|
||||
* the UDMAP section of the TRM for more information on this setting.
|
||||
*
|
||||
* @rx_fdq0_sz0_qnum:
|
||||
* UDMAP receive flow free descriptor queue 0 configuration to be programmed
|
||||
* into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
|
||||
* UDMAP section of the TRM for more information on this setting. The specified
|
||||
* free queue must be valid within the Navigator Subsystem and must be owned
|
||||
* by the host, or a subordinate of the host, requesting allocation and
|
||||
* configuration of the receive flow.
|
||||
*
|
||||
* @rx_fdq1_qnum:
|
||||
* UDMAP receive flow free descriptor queue 1 configuration to be programmed
|
||||
* into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
|
||||
* UDMAP section of the TRM for more information on this setting. The specified
|
||||
* free queue must be valid within the Navigator Subsystem and must be owned
|
||||
* by the host, or a subordinate of the host, requesting allocation and
|
||||
* configuration of the receive flow.
|
||||
*
|
||||
* @rx_fdq2_qnum:
|
||||
* UDMAP receive flow free descriptor queue 2 configuration to be programmed
|
||||
* into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
|
||||
* UDMAP section of the TRM for more information on this setting. The specified
|
||||
* free queue must be valid within the Navigator Subsystem and must be owned
|
||||
* by the host, or a subordinate of the host, requesting allocation and
|
||||
* configuration of the receive flow.
|
||||
*
|
||||
* @rx_fdq3_qnum:
|
||||
* UDMAP receive flow free descriptor queue 3 configuration to be programmed
|
||||
* into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
|
||||
* UDMAP section of the TRM for more information on this setting. The specified
|
||||
* free queue must be valid within the Navigator Subsystem and must be owned
|
||||
* by the host, or a subordinate of the host, requesting allocation and
|
||||
* configuration of the receive flow.
|
||||
*
|
||||
* @rx_ps_location:
|
||||
* UDMAP receive flow PS words location configuration to be programmed into the
|
||||
* rx_ps_location field of the flow's RFLOW_RFA register.
|
||||
*/
|
||||
struct ti_sci_msg_rm_udmap_flow_cfg_req {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u32 valid_params;
|
||||
u16 nav_id;
|
||||
u16 flow_index;
|
||||
u8 rx_einfo_present;
|
||||
u8 rx_psinfo_present;
|
||||
u8 rx_error_handling;
|
||||
u8 rx_desc_type;
|
||||
u16 rx_sop_offset;
|
||||
u16 rx_dest_qnum;
|
||||
u8 rx_src_tag_hi;
|
||||
u8 rx_src_tag_lo;
|
||||
u8 rx_dest_tag_hi;
|
||||
u8 rx_dest_tag_lo;
|
||||
u8 rx_src_tag_hi_sel;
|
||||
u8 rx_src_tag_lo_sel;
|
||||
u8 rx_dest_tag_hi_sel;
|
||||
u8 rx_dest_tag_lo_sel;
|
||||
u16 rx_fdq0_sz0_qnum;
|
||||
u16 rx_fdq1_qnum;
|
||||
u16 rx_fdq2_qnum;
|
||||
u16 rx_fdq3_qnum;
|
||||
u8 rx_ps_location;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_proc_request - Request a processor
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor being requested
|
||||
*
|
||||
* Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_proc_request {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u8 processor_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_proc_release - Release a processor
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor being released
|
||||
*
|
||||
* Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_proc_release {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u8 processor_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_proc_handover - Handover a processor to a host
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor being handed over
|
||||
* @host_id: Host ID the control needs to be transferred to
|
||||
*
|
||||
* Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_proc_handover {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u8 processor_id;
|
||||
u8 host_id;
|
||||
} __packed;
|
||||
|
||||
/* Boot Vector masks */
|
||||
#define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
|
||||
#define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
|
||||
#define TI_SCI_ADDR_HIGH_SHIFT 32
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_set_config - Set Processor boot configuration
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor being configured
|
||||
* @bootvector_low: Lower 32 bit address (Little Endian) of boot vector
|
||||
* @bootvector_high: Higher 32 bit address (Little Endian) of boot vector
|
||||
* @config_flags_set: Optional Processor specific Config Flags to set.
|
||||
* Setting a bit here implies the corresponding mode
|
||||
* will be set
|
||||
* @config_flags_clear: Optional Processor specific Config Flags to clear.
|
||||
* Setting a bit here implies the corresponding mode
|
||||
* will be cleared
|
||||
*
|
||||
* Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_set_config {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u8 processor_id;
|
||||
u32 bootvector_low;
|
||||
u32 bootvector_high;
|
||||
u32 config_flags_set;
|
||||
u32 config_flags_clear;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor being configured
|
||||
* @control_flags_set: Optional Processor specific Control Flags to set.
|
||||
* Setting a bit here implies the corresponding mode
|
||||
* will be set
|
||||
* @control_flags_clear:Optional Processor specific Control Flags to clear.
|
||||
* Setting a bit here implies the corresponding mode
|
||||
* will be cleared
|
||||
*
|
||||
* Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_set_ctrl {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u8 processor_id;
|
||||
u32 control_flags_set;
|
||||
u32 control_flags_clear;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_get_status - Processor boot status request
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor whose status is being requested
|
||||
*
|
||||
* Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate
|
||||
* message, or NACK in case of inability to satisfy request.
|
||||
*/
|
||||
struct ti_sci_msg_req_get_status {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u8 processor_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_resp_get_status - Processor boot status response
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor whose status is returned
|
||||
* @bootvector_low: Lower 32 bit address (Little Endian) of boot vector
|
||||
* @bootvector_high: Higher 32 bit address (Little Endian) of boot vector
|
||||
* @config_flags: Optional Processor specific Config Flags set currently
|
||||
* @control_flags: Optional Processor specific Control Flags set currently
|
||||
* @status_flags: Optional Processor specific Status Flags set currently
|
||||
*
|
||||
* Response structure to a TI_SCI_MSG_GET_STATUS request.
|
||||
*/
|
||||
struct ti_sci_msg_resp_get_status {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
u8 processor_id;
|
||||
u32 bootvector_low;
|
||||
u32 bootvector_high;
|
||||
u32 config_flags;
|
||||
u32 control_flags;
|
||||
u32 status_flags;
|
||||
} __packed;
|
||||
|
||||
#endif /* __TI_SCI_H */
|
||||
|
||||
Reference in New Issue
Block a user