PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
commit8963106eab
("PCI: endpoint: Add MSI-X interfaces") while adding support to raise MSI-X interrupts from endpoint didn't include BAR Indicator register (BIR) configuration and MSI-X table offset as arguments in pci_epc_set_msix(). This would result in endpoint controller register using random BAR indicator register, the memory for which might not be allocated by the endpoint function driver. Add BAR indicator register and MSI-X table offset as arguments in pci_epc_set_msix() and allocate space for MSI-X table and pending bit array (PBA) in pci-epf-test endpoint function driver. Fixes:8963106eab
("PCI: endpoint: Add MSI-X interfaces") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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committed by
Lorenzo Pieralisi

parent
cf376b4b59
commit
83153d9f36
@@ -278,7 +278,8 @@ static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
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return val;
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}
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static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
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static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
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enum pci_barno bir, u32 offset)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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@@ -287,12 +288,22 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
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if (!ep->msix_cap)
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return -EINVAL;
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dw_pcie_dbi_ro_wr_en(pci);
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reg = ep->msix_cap + PCI_MSIX_FLAGS;
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val = dw_pcie_readw_dbi(pci, reg);
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val &= ~PCI_MSIX_FLAGS_QSIZE;
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val |= interrupts;
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dw_pcie_dbi_ro_wr_en(pci);
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dw_pcie_writew_dbi(pci, reg, val);
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reg = ep->msix_cap + PCI_MSIX_TABLE;
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val = offset | bir;
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dw_pcie_writel_dbi(pci, reg, val);
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reg = ep->msix_cap + PCI_MSIX_PBA;
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val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
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dw_pcie_writel_dbi(pci, reg, val);
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dw_pcie_dbi_ro_wr_dis(pci);
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return 0;
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