Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu updates from Greg Ungerer: "The main change is the removal of the bit-rotten 68360 support. Also a fix to always make the ethernet FEC platform info available" * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: m68knommu: remove obsolete 68360 support m68knommu: fix FEC platform device registration when driver is modular
This commit is contained in:
Linus Torvalds
@@ -1,664 +0,0 @@
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/*
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* 68360 Communication Processor Module.
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* Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after:
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* Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx)
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*
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* This file contains structures and information for the communication
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* processor channels. Some CPM control and status is available
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* through the 68360 internal memory map. See include/asm/360_immap.h for details.
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* This file is not a complete map of all of the 360 QUICC's capabilities
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*
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* On the MBX board, EPPC-Bug loads CPM microcode into the first 512
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* bytes of the DP RAM and relocates the I2C parameter area to the
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* IDMA1 space. The remaining DP RAM is available for buffer descriptors
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* or other use.
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*/
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#ifndef __CPM_360__
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#define __CPM_360__
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/* CPM Command register masks: */
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#define CPM_CR_RST ((ushort)0x8000)
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#define CPM_CR_OPCODE ((ushort)0x0f00)
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#define CPM_CR_CHAN ((ushort)0x00f0)
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#define CPM_CR_FLG ((ushort)0x0001)
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/* CPM Command set (opcodes): */
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#define CPM_CR_INIT_TRX ((ushort)0x0000)
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#define CPM_CR_INIT_RX ((ushort)0x0001)
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#define CPM_CR_INIT_TX ((ushort)0x0002)
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#define CPM_CR_HUNT_MODE ((ushort)0x0003)
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#define CPM_CR_STOP_TX ((ushort)0x0004)
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#define CPM_CR_GRSTOP_TX ((ushort)0x0005)
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#define CPM_CR_RESTART_TX ((ushort)0x0006)
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#define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
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#define CPM_CR_SET_GADDR ((ushort)0x0008)
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#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009)
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#define CPM_CR_GCI_ABORT ((ushort)0x000a)
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#define CPM_CR_RESET_BCS ((ushort)0x000a)
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/* CPM Channel numbers. */
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#define CPM_CR_CH_SCC1 ((ushort)0x0000)
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#define CPM_CR_CH_SCC2 ((ushort)0x0004)
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#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */
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#define CPM_CR_CH_TMR ((ushort)0x0005)
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#define CPM_CR_CH_SCC3 ((ushort)0x0008)
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#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */
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#define CPM_CR_CH_IDMA1 ((ushort)0x0009)
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#define CPM_CR_CH_SCC4 ((ushort)0x000c)
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#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */
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#define CPM_CR_CH_IDMA2 ((ushort)0x000d)
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#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
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#if 1 /* mleslie: I dinna think we have any such restrictions on
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* DP RAM aboard the 360 board - see the MC68360UM p.3-3 */
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/* The dual ported RAM is multi-functional. Some areas can be (and are
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* being) used for microcode. There is an area that can only be used
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* as data ram for buffer descriptors, which is all we use right now.
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* Currently the first 512 and last 256 bytes are used for microcode.
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*/
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/* mleslie: The uCquicc board is using no extra microcode in DPRAM */
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#define CPM_DATAONLY_BASE ((uint)0x0000)
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#define CPM_DATAONLY_SIZE ((uint)0x0800)
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#define CPM_DP_NOSPACE ((uint)0x7fffffff)
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#endif
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/* Export the base address of the communication processor registers
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* and dual port ram. */
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/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */
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extern QUICC *pquicc;
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uint m360_cpm_dpalloc(uint size);
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/* void *m360_cpm_hostalloc(uint size); */
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void m360_cpm_setbrg(uint brg, uint rate);
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#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */
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/* Buffer descriptors used by many of the CPM protocols. */
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typedef struct cpm_buf_desc {
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ushort cbd_sc; /* Status and Control */
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ushort cbd_datlen; /* Data length in buffer */
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uint cbd_bufaddr; /* Buffer address in host memory */
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} cbd_t;
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#endif
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/* rx bd status/control bits */
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#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
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#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
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#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
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#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
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#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
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#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
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#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
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#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
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#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
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#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */
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#define BD_SC_BR ((ushort)0x0020) /* Break received */
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#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */
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#define BD_SC_FR ((ushort)0x0010) /* Framing error */
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#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */
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#define BD_SC_PR ((ushort)0x0008) /* Parity error */
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#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */
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#define BD_SC_OV ((ushort)0x0002) /* Overrun */
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#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
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/* tx bd status/control bits (as differ from rx bd) */
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#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
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#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
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#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
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#define BD_SC_UN ((ushort)0x0002) /* Underrun */
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/* Parameter RAM offsets. */
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/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM.
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* In 2.0, we use a more structured C struct map of DPRAM, and so
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* instead, we need only a parameter ram `slot' */
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#define PRSLOT_SCC1 0
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#define PRSLOT_SCC2 1
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#define PRSLOT_SCC3 2
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#define PRSLOT_SMC1 2
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#define PRSLOT_SCC4 3
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#define PRSLOT_SMC2 3
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/* #define PROFF_SCC1 ((uint)0x0000) */
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/* #define PROFF_SCC2 ((uint)0x0100) */
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/* #define PROFF_SCC3 ((uint)0x0200) */
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/* #define PROFF_SMC1 ((uint)0x0280) */
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/* #define PROFF_SCC4 ((uint)0x0300) */
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/* #define PROFF_SMC2 ((uint)0x0380) */
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/* Define enough so I can at least use the serial port as a UART.
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* The MBX uses SMC1 as the host serial port.
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*/
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typedef struct smc_uart {
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ushort smc_rbase; /* Rx Buffer descriptor base address */
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ushort smc_tbase; /* Tx Buffer descriptor base address */
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u_char smc_rfcr; /* Rx function code */
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u_char smc_tfcr; /* Tx function code */
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ushort smc_mrblr; /* Max receive buffer length */
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uint smc_rstate; /* Internal */
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uint smc_idp; /* Internal */
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ushort smc_rbptr; /* Internal */
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ushort smc_ibc; /* Internal */
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uint smc_rxtmp; /* Internal */
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uint smc_tstate; /* Internal */
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uint smc_tdp; /* Internal */
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ushort smc_tbptr; /* Internal */
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ushort smc_tbc; /* Internal */
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uint smc_txtmp; /* Internal */
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ushort smc_maxidl; /* Maximum idle characters */
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ushort smc_tmpidl; /* Temporary idle counter */
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ushort smc_brklen; /* Last received break length */
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ushort smc_brkec; /* rcv'd break condition counter */
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ushort smc_brkcr; /* xmt break count register */
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ushort smc_rmask; /* Temporary bit mask */
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} smc_uart_t;
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/* Function code bits.
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*/
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#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
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/* SMC uart mode register.
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*/
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#define SMCMR_REN ((ushort)0x0001)
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#define SMCMR_TEN ((ushort)0x0002)
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#define SMCMR_DM ((ushort)0x000c)
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#define SMCMR_SM_GCI ((ushort)0x0000)
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#define SMCMR_SM_UART ((ushort)0x0020)
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#define SMCMR_SM_TRANS ((ushort)0x0030)
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#define SMCMR_SM_MASK ((ushort)0x0030)
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#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
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#define SMCMR_REVD SMCMR_PM_EVEN
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#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
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#define SMCMR_BS SMCMR_PEN
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#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
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#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
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#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
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/* SMC2 as Centronics parallel printer. It is half duplex, in that
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* it can only receive or transmit. The parameter ram values for
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* each direction are either unique or properly overlap, so we can
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* include them in one structure.
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*/
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typedef struct smc_centronics {
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ushort scent_rbase;
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ushort scent_tbase;
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u_char scent_cfcr;
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u_char scent_smask;
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ushort scent_mrblr;
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uint scent_rstate;
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uint scent_r_ptr;
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ushort scent_rbptr;
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ushort scent_r_cnt;
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uint scent_rtemp;
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uint scent_tstate;
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uint scent_t_ptr;
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ushort scent_tbptr;
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ushort scent_t_cnt;
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uint scent_ttemp;
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ushort scent_max_sl;
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ushort scent_sl_cnt;
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ushort scent_character1;
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ushort scent_character2;
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ushort scent_character3;
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ushort scent_character4;
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ushort scent_character5;
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ushort scent_character6;
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ushort scent_character7;
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ushort scent_character8;
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ushort scent_rccm;
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ushort scent_rccr;
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} smc_cent_t;
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/* Centronics Status Mask Register.
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*/
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#define SMC_CENT_F ((u_char)0x08)
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#define SMC_CENT_PE ((u_char)0x04)
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#define SMC_CENT_S ((u_char)0x02)
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/* SMC Event and Mask register.
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*/
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#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
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#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
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#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
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#define SMCM_BSY ((unsigned char)0x04)
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#define SMCM_TX ((unsigned char)0x02)
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#define SMCM_RX ((unsigned char)0x01)
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/* Baud rate generators.
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*/
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#define CPM_BRG_RST ((uint)0x00020000)
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#define CPM_BRG_EN ((uint)0x00010000)
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#define CPM_BRG_EXTC_INT ((uint)0x00000000)
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#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
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#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
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#define CPM_BRG_ATB ((uint)0x00002000)
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#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
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#define CPM_BRG_DIV16 ((uint)0x00000001)
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/* SCCs.
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*/
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#define SCC_GSMRH_IRP ((uint)0x00040000)
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#define SCC_GSMRH_GDE ((uint)0x00010000)
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#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
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#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
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#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
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#define SCC_GSMRH_REVD ((uint)0x00002000)
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#define SCC_GSMRH_TRX ((uint)0x00001000)
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#define SCC_GSMRH_TTX ((uint)0x00000800)
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#define SCC_GSMRH_CDP ((uint)0x00000400)
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#define SCC_GSMRH_CTSP ((uint)0x00000200)
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#define SCC_GSMRH_CDS ((uint)0x00000100)
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#define SCC_GSMRH_CTSS ((uint)0x00000080)
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#define SCC_GSMRH_TFL ((uint)0x00000040)
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#define SCC_GSMRH_RFW ((uint)0x00000020)
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#define SCC_GSMRH_TXSY ((uint)0x00000010)
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#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
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#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
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#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
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#define SCC_GSMRH_RTSM ((uint)0x00000002)
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#define SCC_GSMRH_RSYN ((uint)0x00000001)
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#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
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#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
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#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
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#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
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#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
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#define SCC_GSMRL_TCI ((uint)0x10000000)
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#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
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#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
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#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
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#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
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#define SCC_GSMRL_RINV ((uint)0x02000000)
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#define SCC_GSMRL_TINV ((uint)0x01000000)
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#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
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#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
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#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
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#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
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#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
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#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
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#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
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#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
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#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
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#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
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#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
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#define SCC_GSMRL_TEND ((uint)0x00040000)
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#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
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#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
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#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
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#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
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#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
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#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
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#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
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#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
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#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
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#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
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#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
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#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
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#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
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#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
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#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
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#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
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#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
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#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
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#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
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#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
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#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
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#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
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#define SCC_GSMRL_ENR ((uint)0x00000020)
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||||
#define SCC_GSMRL_ENT ((uint)0x00000010)
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#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
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#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
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||||
#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
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||||
#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
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||||
#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
|
||||
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
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||||
#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
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#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
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#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
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#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
|
||||
|
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#define SCC_TODR_TOD ((ushort)0x8000)
|
||||
|
||||
/* SCC Event and Mask register.
|
||||
*/
|
||||
#define SCCM_TXE ((unsigned char)0x10)
|
||||
#define SCCM_BSY ((unsigned char)0x04)
|
||||
#define SCCM_TX ((unsigned char)0x02)
|
||||
#define SCCM_RX ((unsigned char)0x01)
|
||||
|
||||
typedef struct scc_param {
|
||||
ushort scc_rbase; /* Rx Buffer descriptor base address */
|
||||
ushort scc_tbase; /* Tx Buffer descriptor base address */
|
||||
u_char scc_rfcr; /* Rx function code */
|
||||
u_char scc_tfcr; /* Tx function code */
|
||||
ushort scc_mrblr; /* Max receive buffer length */
|
||||
uint scc_rstate; /* Internal */
|
||||
uint scc_idp; /* Internal */
|
||||
ushort scc_rbptr; /* Internal */
|
||||
ushort scc_ibc; /* Internal */
|
||||
uint scc_rxtmp; /* Internal */
|
||||
uint scc_tstate; /* Internal */
|
||||
uint scc_tdp; /* Internal */
|
||||
ushort scc_tbptr; /* Internal */
|
||||
ushort scc_tbc; /* Internal */
|
||||
uint scc_txtmp; /* Internal */
|
||||
uint scc_rcrc; /* Internal */
|
||||
uint scc_tcrc; /* Internal */
|
||||
} sccp_t;
|
||||
|
||||
|
||||
/* Function code bits.
|
||||
*/
|
||||
#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
|
||||
#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */
|
||||
|
||||
/* CPM Ethernet through SCC1.
|
||||
*/
|
||||
typedef struct scc_enet {
|
||||
sccp_t sen_genscc;
|
||||
uint sen_cpres; /* Preset CRC */
|
||||
uint sen_cmask; /* Constant mask for CRC */
|
||||
uint sen_crcec; /* CRC Error counter */
|
||||
uint sen_alec; /* alignment error counter */
|
||||
uint sen_disfc; /* discard frame counter */
|
||||
ushort sen_pads; /* Tx short frame pad character */
|
||||
ushort sen_retlim; /* Retry limit threshold */
|
||||
ushort sen_retcnt; /* Retry limit counter */
|
||||
ushort sen_maxflr; /* maximum frame length register */
|
||||
ushort sen_minflr; /* minimum frame length register */
|
||||
ushort sen_maxd1; /* maximum DMA1 length */
|
||||
ushort sen_maxd2; /* maximum DMA2 length */
|
||||
ushort sen_maxd; /* Rx max DMA */
|
||||
ushort sen_dmacnt; /* Rx DMA counter */
|
||||
ushort sen_maxb; /* Max BD byte count */
|
||||
ushort sen_gaddr1; /* Group address filter */
|
||||
ushort sen_gaddr2;
|
||||
ushort sen_gaddr3;
|
||||
ushort sen_gaddr4;
|
||||
uint sen_tbuf0data0; /* Save area 0 - current frame */
|
||||
uint sen_tbuf0data1; /* Save area 1 - current frame */
|
||||
uint sen_tbuf0rba; /* Internal */
|
||||
uint sen_tbuf0crc; /* Internal */
|
||||
ushort sen_tbuf0bcnt; /* Internal */
|
||||
ushort sen_paddrh; /* physical address (MSB) */
|
||||
ushort sen_paddrm;
|
||||
ushort sen_paddrl; /* physical address (LSB) */
|
||||
ushort sen_pper; /* persistence */
|
||||
ushort sen_rfbdptr; /* Rx first BD pointer */
|
||||
ushort sen_tfbdptr; /* Tx first BD pointer */
|
||||
ushort sen_tlbdptr; /* Tx last BD pointer */
|
||||
uint sen_tbuf1data0; /* Save area 0 - current frame */
|
||||
uint sen_tbuf1data1; /* Save area 1 - current frame */
|
||||
uint sen_tbuf1rba; /* Internal */
|
||||
uint sen_tbuf1crc; /* Internal */
|
||||
ushort sen_tbuf1bcnt; /* Internal */
|
||||
ushort sen_txlen; /* Tx Frame length counter */
|
||||
ushort sen_iaddr1; /* Individual address filter */
|
||||
ushort sen_iaddr2;
|
||||
ushort sen_iaddr3;
|
||||
ushort sen_iaddr4;
|
||||
ushort sen_boffcnt; /* Backoff counter */
|
||||
|
||||
/* NOTE: Some versions of the manual have the following items
|
||||
* incorrectly documented. Below is the proper order.
|
||||
*/
|
||||
ushort sen_taddrh; /* temp address (MSB) */
|
||||
ushort sen_taddrm;
|
||||
ushort sen_taddrl; /* temp address (LSB) */
|
||||
} scc_enet_t;
|
||||
|
||||
|
||||
|
||||
#if defined (CONFIG_UCQUICC)
|
||||
/* uCquicc has the following signals connected to Ethernet:
|
||||
* 68360 - lxt905
|
||||
* PA0/RXD1 - rxd
|
||||
* PA1/TXD1 - txd
|
||||
* PA8/CLK1 - tclk
|
||||
* PA9/CLK2 - rclk
|
||||
* PC0/!RTS1 - t_en
|
||||
* PC1/!CTS1 - col
|
||||
* PC5/!CD1 - cd
|
||||
*/
|
||||
#define PA_ENET_RXD PA_RXD1
|
||||
#define PA_ENET_TXD PA_TXD1
|
||||
#define PA_ENET_TCLK PA_CLK1
|
||||
#define PA_ENET_RCLK PA_CLK2
|
||||
#define PC_ENET_TENA PC_RTS1
|
||||
#define PC_ENET_CLSN PC_CTS1
|
||||
#define PC_ENET_RENA PC_CD1
|
||||
|
||||
/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
|
||||
* SCC1.
|
||||
*/
|
||||
#define SICR_ENET_MASK ((uint)0x000000ff)
|
||||
#define SICR_ENET_CLKRT ((uint)0x0000002c)
|
||||
|
||||
#endif /* config_ucquicc */
|
||||
|
||||
|
||||
#ifdef MBX
|
||||
/* Bits in parallel I/O port registers that have to be set/cleared
|
||||
* to configure the pins for SCC1 use. The TCLK and RCLK seem unique
|
||||
* to the MBX860 board. Any two of the four available clocks could be
|
||||
* used, and the MPC860 cookbook manual has an example using different
|
||||
* clock pins.
|
||||
*/
|
||||
#define PA_ENET_RXD ((ushort)0x0001)
|
||||
#define PA_ENET_TXD ((ushort)0x0002)
|
||||
#define PA_ENET_TCLK ((ushort)0x0200)
|
||||
#define PA_ENET_RCLK ((ushort)0x0800)
|
||||
#define PC_ENET_TENA ((ushort)0x0001)
|
||||
#define PC_ENET_CLSN ((ushort)0x0010)
|
||||
#define PC_ENET_RENA ((ushort)0x0020)
|
||||
|
||||
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
|
||||
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
|
||||
*/
|
||||
#define SICR_ENET_MASK ((uint)0x000000ff)
|
||||
#define SICR_ENET_CLKRT ((uint)0x0000003d)
|
||||
#endif
|
||||
|
||||
/* SCC Event register as used by Ethernet.
|
||||
*/
|
||||
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
|
||||
#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
|
||||
#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
|
||||
#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
|
||||
#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
|
||||
#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
|
||||
|
||||
/* SCC Mode Register (PMSR) as used by Ethernet.
|
||||
*/
|
||||
#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
|
||||
#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
|
||||
#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
|
||||
#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
|
||||
#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
|
||||
#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
|
||||
#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
|
||||
#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
|
||||
#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
|
||||
#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
|
||||
#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
|
||||
#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
|
||||
#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
|
||||
|
||||
/* Buffer descriptor control/status used by Ethernet receive.
|
||||
*/
|
||||
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
|
||||
#define BD_ENET_RX_WRAP ((ushort)0x2000)
|
||||
#define BD_ENET_RX_INTR ((ushort)0x1000)
|
||||
#define BD_ENET_RX_LAST ((ushort)0x0800)
|
||||
#define BD_ENET_RX_FIRST ((ushort)0x0400)
|
||||
#define BD_ENET_RX_MISS ((ushort)0x0100)
|
||||
#define BD_ENET_RX_LG ((ushort)0x0020)
|
||||
#define BD_ENET_RX_NO ((ushort)0x0010)
|
||||
#define BD_ENET_RX_SH ((ushort)0x0008)
|
||||
#define BD_ENET_RX_CR ((ushort)0x0004)
|
||||
#define BD_ENET_RX_OV ((ushort)0x0002)
|
||||
#define BD_ENET_RX_CL ((ushort)0x0001)
|
||||
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
|
||||
|
||||
/* Buffer descriptor control/status used by Ethernet transmit.
|
||||
*/
|
||||
#define BD_ENET_TX_READY ((ushort)0x8000)
|
||||
#define BD_ENET_TX_PAD ((ushort)0x4000)
|
||||
#define BD_ENET_TX_WRAP ((ushort)0x2000)
|
||||
#define BD_ENET_TX_INTR ((ushort)0x1000)
|
||||
#define BD_ENET_TX_LAST ((ushort)0x0800)
|
||||
#define BD_ENET_TX_TC ((ushort)0x0400)
|
||||
#define BD_ENET_TX_DEF ((ushort)0x0200)
|
||||
#define BD_ENET_TX_HB ((ushort)0x0100)
|
||||
#define BD_ENET_TX_LC ((ushort)0x0080)
|
||||
#define BD_ENET_TX_RL ((ushort)0x0040)
|
||||
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
|
||||
#define BD_ENET_TX_UN ((ushort)0x0002)
|
||||
#define BD_ENET_TX_CSL ((ushort)0x0001)
|
||||
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
|
||||
|
||||
/* SCC as UART
|
||||
*/
|
||||
typedef struct scc_uart {
|
||||
sccp_t scc_genscc;
|
||||
uint scc_res1; /* Reserved */
|
||||
uint scc_res2; /* Reserved */
|
||||
ushort scc_maxidl; /* Maximum idle chars */
|
||||
ushort scc_idlc; /* temp idle counter */
|
||||
ushort scc_brkcr; /* Break count register */
|
||||
ushort scc_parec; /* receive parity error counter */
|
||||
ushort scc_frmec; /* receive framing error counter */
|
||||
ushort scc_nosec; /* receive noise counter */
|
||||
ushort scc_brkec; /* receive break condition counter */
|
||||
ushort scc_brkln; /* last received break length */
|
||||
ushort scc_uaddr1; /* UART address character 1 */
|
||||
ushort scc_uaddr2; /* UART address character 2 */
|
||||
ushort scc_rtemp; /* Temp storage */
|
||||
ushort scc_toseq; /* Transmit out of sequence char */
|
||||
ushort scc_char1; /* control character 1 */
|
||||
ushort scc_char2; /* control character 2 */
|
||||
ushort scc_char3; /* control character 3 */
|
||||
ushort scc_char4; /* control character 4 */
|
||||
ushort scc_char5; /* control character 5 */
|
||||
ushort scc_char6; /* control character 6 */
|
||||
ushort scc_char7; /* control character 7 */
|
||||
ushort scc_char8; /* control character 8 */
|
||||
ushort scc_rccm; /* receive control character mask */
|
||||
ushort scc_rccr; /* receive control character register */
|
||||
ushort scc_rlbc; /* receive last break character */
|
||||
} scc_uart_t;
|
||||
|
||||
/* SCC Event and Mask registers when it is used as a UART.
|
||||
*/
|
||||
#define UART_SCCM_GLR ((ushort)0x1000)
|
||||
#define UART_SCCM_GLT ((ushort)0x0800)
|
||||
#define UART_SCCM_AB ((ushort)0x0200)
|
||||
#define UART_SCCM_IDL ((ushort)0x0100)
|
||||
#define UART_SCCM_GRA ((ushort)0x0080)
|
||||
#define UART_SCCM_BRKE ((ushort)0x0040)
|
||||
#define UART_SCCM_BRKS ((ushort)0x0020)
|
||||
#define UART_SCCM_CCR ((ushort)0x0008)
|
||||
#define UART_SCCM_BSY ((ushort)0x0004)
|
||||
#define UART_SCCM_TX ((ushort)0x0002)
|
||||
#define UART_SCCM_RX ((ushort)0x0001)
|
||||
|
||||
/* The SCC PMSR when used as a UART.
|
||||
*/
|
||||
#define SCU_PMSR_FLC ((ushort)0x8000)
|
||||
#define SCU_PMSR_SL ((ushort)0x4000)
|
||||
#define SCU_PMSR_CL ((ushort)0x3000)
|
||||
#define SCU_PMSR_UM ((ushort)0x0c00)
|
||||
#define SCU_PMSR_FRZ ((ushort)0x0200)
|
||||
#define SCU_PMSR_RZS ((ushort)0x0100)
|
||||
#define SCU_PMSR_SYN ((ushort)0x0080)
|
||||
#define SCU_PMSR_DRT ((ushort)0x0040)
|
||||
#define SCU_PMSR_PEN ((ushort)0x0010)
|
||||
#define SCU_PMSR_RPM ((ushort)0x000c)
|
||||
#define SCU_PMSR_REVP ((ushort)0x0008)
|
||||
#define SCU_PMSR_TPM ((ushort)0x0003)
|
||||
#define SCU_PMSR_TEVP ((ushort)0x0003)
|
||||
|
||||
/* CPM Transparent mode SCC.
|
||||
*/
|
||||
typedef struct scc_trans {
|
||||
sccp_t st_genscc;
|
||||
uint st_cpres; /* Preset CRC */
|
||||
uint st_cmask; /* Constant mask for CRC */
|
||||
} scc_trans_t;
|
||||
|
||||
#define BD_SCC_TX_LAST ((ushort)0x0800)
|
||||
|
||||
|
||||
|
||||
/* CPM interrupts. There are nearly 32 interrupts generated by CPM
|
||||
* channels or devices. All of these are presented to the PPC core
|
||||
* as a single interrupt. The CPM interrupt handler dispatches its
|
||||
* own handlers, in a similar fashion to the PPC core handler. We
|
||||
* use the table as defined in the manuals (i.e. no special high
|
||||
* priority and SCC1 == SCCa, etc...).
|
||||
*/
|
||||
/* #define CPMVEC_NR 32 */
|
||||
/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */
|
||||
/* #define CPMVEC_SCC1 ((ushort)0x1e) */
|
||||
/* #define CPMVEC_SCC2 ((ushort)0x1d) */
|
||||
/* #define CPMVEC_SCC3 ((ushort)0x1c) */
|
||||
/* #define CPMVEC_SCC4 ((ushort)0x1b) */
|
||||
/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */
|
||||
/* #define CPMVEC_TIMER1 ((ushort)0x19) */
|
||||
/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */
|
||||
/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */
|
||||
/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
|
||||
/* #define CPMVEC_IDMA1 ((ushort)0x15) */
|
||||
/* #define CPMVEC_IDMA2 ((ushort)0x14) */
|
||||
/* #define CPMVEC_TIMER2 ((ushort)0x12) */
|
||||
/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
|
||||
/* #define CPMVEC_I2C ((ushort)0x10) */
|
||||
/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */
|
||||
/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */
|
||||
/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
|
||||
/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */
|
||||
/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */
|
||||
/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */
|
||||
/* #define CPMVEC_TIMER4 ((ushort)0x07) */
|
||||
/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */
|
||||
/* #define CPMVEC_SPI ((ushort)0x05) */
|
||||
/* #define CPMVEC_SMC1 ((ushort)0x04) */
|
||||
/* #define CPMVEC_SMC2 ((ushort)0x03) */
|
||||
/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */
|
||||
/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */
|
||||
/* #define CPMVEC_ERROR ((ushort)0x00) */
|
||||
|
||||
extern void cpm_install_handler(int vec, irq_handler_t handler, void *dev_id);
|
||||
|
||||
/* CPM interrupt configuration vector.
|
||||
*/
|
||||
#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
|
||||
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
|
||||
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
|
||||
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
|
||||
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
|
||||
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
|
||||
#define CICR_IEN ((uint)0x00000080) /* Int. enable */
|
||||
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
|
||||
#endif /* __CPM_360__ */
|
||||
@@ -1,13 +0,0 @@
|
||||
#include <asm/m68360_regs.h>
|
||||
#include <asm/m68360_pram.h>
|
||||
#include <asm/m68360_quicc.h>
|
||||
#include <asm/m68360_enet.h>
|
||||
|
||||
#ifdef CONFIG_M68360
|
||||
|
||||
#define CPM_INTERRUPT 4
|
||||
|
||||
/* see MC68360 User's Manual, p. 7-377 */
|
||||
#define CPM_VECTOR_BASE 0x04 /* 3 MSbits of CPM vector */
|
||||
|
||||
#endif /* CONFIG_M68360 */
|
||||
@@ -1,177 +0,0 @@
|
||||
/***********************************
|
||||
* $Id: m68360_enet.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
|
||||
***********************************
|
||||
*
|
||||
***************************************
|
||||
* Definitions for the ETHERNET controllers
|
||||
***************************************
|
||||
*/
|
||||
|
||||
#ifndef __ETHER_H
|
||||
#define __ETHER_H
|
||||
|
||||
#include <asm/quicc_simple.h>
|
||||
|
||||
/*
|
||||
* transmit BD's
|
||||
*/
|
||||
#define T_R 0x8000 /* ready bit */
|
||||
#define E_T_PAD 0x4000 /* short frame padding */
|
||||
#define T_W 0x2000 /* wrap bit */
|
||||
#define T_I 0x1000 /* interrupt on completion */
|
||||
#define T_L 0x0800 /* last in frame */
|
||||
#define T_TC 0x0400 /* transmit CRC (when last) */
|
||||
|
||||
#define T_DEF 0x0200 /* defer indication */
|
||||
#define T_HB 0x0100 /* heartbeat */
|
||||
#define T_LC 0x0080 /* error: late collision */
|
||||
#define T_RL 0x0040 /* error: retransmission limit */
|
||||
#define T_RC 0x003c /* retry count */
|
||||
#define T_UN 0x0002 /* error: underrun */
|
||||
#define T_CSL 0x0001 /* carier sense lost */
|
||||
#define T_ERROR (T_HB | T_LC | T_RL | T_UN | T_CSL)
|
||||
|
||||
/*
|
||||
* receive BD's
|
||||
*/
|
||||
#define R_E 0x8000 /* buffer empty */
|
||||
#define R_W 0x2000 /* wrap bit */
|
||||
#define R_I 0x1000 /* interrupt on reception */
|
||||
#define R_L 0x0800 /* last BD in frame */
|
||||
#define R_F 0x0400 /* first BD in frame */
|
||||
#define R_M 0x0100 /* received because of promisc. mode */
|
||||
|
||||
#define R_LG 0x0020 /* frame too long */
|
||||
#define R_NO 0x0010 /* non-octet aligned */
|
||||
#define R_SH 0x0008 /* short frame */
|
||||
#define R_CR 0x0004 /* receive CRC error */
|
||||
#define R_OV 0x0002 /* receive overrun */
|
||||
#define R_CL 0x0001 /* collision */
|
||||
#define ETHER_R_ERROR (R_LG | R_NO | R_SH | R_CR | R_OV | R_CL)
|
||||
|
||||
|
||||
/*
|
||||
* ethernet interrupts
|
||||
*/
|
||||
#define ETHERNET_GRA 0x0080 /* graceful stop complete */
|
||||
#define ETHERNET_TXE 0x0010 /* transmit error */
|
||||
#define ETHERNET_RXF 0x0008 /* receive frame */
|
||||
#define ETHERNET_BSY 0x0004 /* busy condition */
|
||||
#define ETHERNET_TXB 0x0002 /* transmit buffer */
|
||||
#define ETHERNET_RXB 0x0001 /* receive buffer */
|
||||
|
||||
/*
|
||||
* ethernet protocol specific mode register (PSMR)
|
||||
*/
|
||||
#define ETHER_HBC 0x8000 /* heartbeat checking */
|
||||
#define ETHER_FC 0x4000 /* force collision */
|
||||
#define ETHER_RSH 0x2000 /* receive short frames */
|
||||
#define ETHER_IAM 0x1000 /* individual address mode */
|
||||
#define ETHER_CRC_32 (0x2<<10) /* Enable CRC */
|
||||
#define ETHER_PRO 0x0200 /* promiscuous */
|
||||
#define ETHER_BRO 0x0100 /* broadcast address */
|
||||
#define ETHER_SBT 0x0080 /* stop backoff timer */
|
||||
#define ETHER_LPB 0x0040 /* Loop Back Mode */
|
||||
#define ETHER_SIP 0x0020 /* sample input pins */
|
||||
#define ETHER_LCW 0x0010 /* late collision window */
|
||||
#define ETHER_NIB_13 (0x0<<1) /* # of ignored bits 13 */
|
||||
#define ETHER_NIB_14 (0x1<<1) /* # of ignored bits 14 */
|
||||
#define ETHER_NIB_15 (0x2<<1) /* # of ignored bits 15 */
|
||||
#define ETHER_NIB_16 (0x3<<1) /* # of ignored bits 16 */
|
||||
#define ETHER_NIB_21 (0x4<<1) /* # of ignored bits 21 */
|
||||
#define ETHER_NIB_22 (0x5<<1) /* # of ignored bits 22 */
|
||||
#define ETHER_NIB_23 (0x6<<1) /* # of ignored bits 23 */
|
||||
#define ETHER_NIB_24 (0x7<<1) /* # of ignored bits 24 */
|
||||
|
||||
/*
|
||||
* ethernet specific parameters
|
||||
*/
|
||||
#define CRC_WORD 4 /* Length in bytes of CRC */
|
||||
#define C_PRES 0xffffffff /* preform 32 bit CRC */
|
||||
#define C_MASK 0xdebb20e3 /* comply with 32 bit CRC */
|
||||
#define CRCEC 0x00000000
|
||||
#define ALEC 0x00000000
|
||||
#define DISFC 0x00000000
|
||||
#define PADS 0x00000000
|
||||
#define RET_LIM 0x000f /* retry 15 times to send a frame before interrupt */
|
||||
#define ETH_MFLR 0x05ee /* 1518 max frame size */
|
||||
#define MINFLR 0x0040 /* Minimum frame size 64 */
|
||||
#define MAXD1 0x05ee /* Max dma count 1518 */
|
||||
#define MAXD2 0x05ee
|
||||
#define GADDR1 0x00000000 /* Clear group address */
|
||||
#define GADDR2 0x00000000
|
||||
#define GADDR3 0x00000000
|
||||
#define GADDR4 0x00000000
|
||||
#define P_PER 0x00000000 /*not used */
|
||||
#define IADDR1 0x00000000 /* Individual hash table not used */
|
||||
#define IADDR2 0x00000000
|
||||
#define IADDR3 0x00000000
|
||||
#define IADDR4 0x00000000
|
||||
#define TADDR_H 0x00000000 /* clear this regs */
|
||||
#define TADDR_M 0x00000000
|
||||
#define TADDR_L 0x00000000
|
||||
|
||||
/* SCC Parameter Ram */
|
||||
#define RFCR 0x18 /* normal operation */
|
||||
#define TFCR 0x18 /* normal operation */
|
||||
#define E_MRBLR 1518 /* Max ethernet frame length */
|
||||
|
||||
/*
|
||||
* ethernet specific structure
|
||||
*/
|
||||
typedef union {
|
||||
unsigned char b[6];
|
||||
struct {
|
||||
unsigned short high;
|
||||
unsigned short middl;
|
||||
unsigned short low;
|
||||
} w;
|
||||
} ETHER_ADDR;
|
||||
|
||||
typedef struct {
|
||||
int max_frame_length;
|
||||
int promisc_mode;
|
||||
int reject_broadcast;
|
||||
ETHER_ADDR phys_adr;
|
||||
} ETHER_SPECIFIC;
|
||||
|
||||
typedef struct {
|
||||
ETHER_ADDR dst_addr;
|
||||
ETHER_ADDR src_addr;
|
||||
unsigned short type_or_len;
|
||||
unsigned char data[1];
|
||||
} ETHER_FRAME;
|
||||
|
||||
#define MAX_DATALEN 1500
|
||||
typedef struct {
|
||||
ETHER_ADDR dst_addr;
|
||||
ETHER_ADDR src_addr;
|
||||
unsigned short type_or_len;
|
||||
unsigned char data[MAX_DATALEN];
|
||||
unsigned char fcs[CRC_WORD];
|
||||
} ETHER_MAX_FRAME;
|
||||
|
||||
|
||||
/*
|
||||
* Internal ethernet function prototypes
|
||||
*/
|
||||
void ether_interrupt(int scc_num);
|
||||
/* mleslie: debug */
|
||||
/* static void ethernet_rx_internal(int scc_num); */
|
||||
/* static void ethernet_tx_internal(int scc_num); */
|
||||
|
||||
/*
|
||||
* User callable routines prototypes (ethernet specific)
|
||||
*/
|
||||
void ethernet_init(int scc_number,
|
||||
alloc_routine *alloc_buffer,
|
||||
free_routine *free_buffer,
|
||||
store_rx_buffer_routine *store_rx_buffer,
|
||||
handle_tx_error_routine *handle_tx_error,
|
||||
handle_rx_error_routine *handle_rx_error,
|
||||
handle_lost_error_routine *handle_lost_error,
|
||||
ETHER_SPECIFIC *ether_spec);
|
||||
int ethernet_tx(int scc_number, void *buf, int length);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,431 +0,0 @@
|
||||
/***********************************
|
||||
* $Id: m68360_pram.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
|
||||
***********************************
|
||||
*
|
||||
***************************************
|
||||
* Definitions of the parameter area RAM.
|
||||
* Note that different structures are overlaid
|
||||
* at the same offsets for the different modes
|
||||
* of operation.
|
||||
***************************************
|
||||
*/
|
||||
|
||||
#ifndef __PRAM_H
|
||||
#define __PRAM_H
|
||||
|
||||
/* Time slot assignment table */
|
||||
#define VALID_SLOT 0x8000
|
||||
#define WRAP_SLOT 0x4000
|
||||
|
||||
/*****************************************************************
|
||||
Global Multichannel parameter RAM
|
||||
*****************************************************************/
|
||||
struct global_multi_pram {
|
||||
/*
|
||||
* Global Multichannel parameter RAM
|
||||
*/
|
||||
unsigned long mcbase; /* Multichannel Base pointer */
|
||||
unsigned short qmcstate; /* Multichannel Controller state */
|
||||
unsigned short mrblr; /* Maximum Receive Buffer Length */
|
||||
unsigned short tx_s_ptr; /* TSTATx Pointer */
|
||||
unsigned short rxptr; /* Current Time slot entry in TSATRx */
|
||||
unsigned short grfthr; /* Global Receive frame threshold */
|
||||
unsigned short grfcnt; /* Global Receive Frame Count */
|
||||
unsigned long intbase; /* Multichannel Base address */
|
||||
unsigned long iintptr; /* Pointer to interrupt queue */
|
||||
unsigned short rx_s_ptr; /* TSTARx Pointer */
|
||||
|
||||
unsigned short txptr; /* Current Time slot entry in TSATTx */
|
||||
unsigned long c_mask32; /* CRC Constant (debb20e3) */
|
||||
unsigned short tsatrx[32]; /* Time Slot Assignment Table Rx */
|
||||
unsigned short tsattx[32]; /* Time Slot Assignment Table Tx */
|
||||
unsigned short c_mask16; /* CRC Constant (f0b8) */
|
||||
};
|
||||
|
||||
/*****************************************************************
|
||||
Quicc32 HDLC parameter RAM
|
||||
*****************************************************************/
|
||||
struct quicc32_pram {
|
||||
|
||||
unsigned short tbase; /* Tx Buffer Descriptors Base Address */
|
||||
unsigned short chamr; /* Channel Mode Register */
|
||||
unsigned long tstate; /* Tx Internal State */
|
||||
unsigned long txintr; /* Tx Internal Data Pointer */
|
||||
unsigned short tbptr; /* Tx Buffer Descriptor Pointer */
|
||||
unsigned short txcntr; /* Tx Internal Byte Count */
|
||||
unsigned long tupack; /* (Tx Temp) */
|
||||
unsigned long zistate; /* Zero Insertion machine state */
|
||||
unsigned long tcrc; /* Temp Transmit CRC */
|
||||
unsigned short intmask; /* Channel's interrupt mask flags */
|
||||
unsigned short bdflags;
|
||||
unsigned short rbase; /* Rx Buffer Descriptors Base Address */
|
||||
unsigned short mflr; /* Max Frame Length Register */
|
||||
unsigned long rstate; /* Rx Internal State */
|
||||
unsigned long rxintr; /* Rx Internal Data Pointer */
|
||||
unsigned short rbptr; /* Rx Buffer Descriptor Pointer */
|
||||
unsigned short rxbyc; /* Rx Internal Byte Count */
|
||||
unsigned long rpack; /* (Rx Temp) */
|
||||
unsigned long zdstate; /* Zero Deletion machine state */
|
||||
unsigned long rcrc; /* Temp Transmit CRC */
|
||||
unsigned short maxc; /* Max_length counter */
|
||||
unsigned short tmp_mb; /* Temp */
|
||||
};
|
||||
|
||||
|
||||
/*****************************************************************
|
||||
HDLC parameter RAM
|
||||
*****************************************************************/
|
||||
|
||||
struct hdlc_pram {
|
||||
/*
|
||||
* SCC parameter RAM
|
||||
*/
|
||||
unsigned short rbase; /* RX BD base address */
|
||||
unsigned short tbase; /* TX BD base address */
|
||||
unsigned char rfcr; /* Rx function code */
|
||||
unsigned char tfcr; /* Tx function code */
|
||||
unsigned short mrblr; /* Rx buffer length */
|
||||
unsigned long rstate; /* Rx internal state */
|
||||
unsigned long rptr; /* Rx internal data pointer */
|
||||
unsigned short rbptr; /* rb BD Pointer */
|
||||
unsigned short rcount; /* Rx internal byte count */
|
||||
unsigned long rtemp; /* Rx temp */
|
||||
unsigned long tstate; /* Tx internal state */
|
||||
unsigned long tptr; /* Tx internal data pointer */
|
||||
unsigned short tbptr; /* Tx BD pointer */
|
||||
unsigned short tcount; /* Tx byte count */
|
||||
unsigned long ttemp; /* Tx temp */
|
||||
unsigned long rcrc; /* temp receive CRC */
|
||||
unsigned long tcrc; /* temp transmit CRC */
|
||||
|
||||
/*
|
||||
* HDLC specific parameter RAM
|
||||
*/
|
||||
unsigned char RESERVED1[4]; /* Reserved area */
|
||||
unsigned long c_mask; /* CRC constant */
|
||||
unsigned long c_pres; /* CRC preset */
|
||||
unsigned short disfc; /* discarded frame counter */
|
||||
unsigned short crcec; /* CRC error counter */
|
||||
unsigned short abtsc; /* abort sequence counter */
|
||||
unsigned short nmarc; /* nonmatching address rx cnt */
|
||||
unsigned short retrc; /* frame retransmission cnt */
|
||||
unsigned short mflr; /* maximum frame length reg */
|
||||
unsigned short max_cnt; /* maximum length counter */
|
||||
unsigned short rfthr; /* received frames threshold */
|
||||
unsigned short rfcnt; /* received frames count */
|
||||
unsigned short hmask; /* user defined frm addr mask */
|
||||
unsigned short haddr1; /* user defined frm address 1 */
|
||||
unsigned short haddr2; /* user defined frm address 2 */
|
||||
unsigned short haddr3; /* user defined frm address 3 */
|
||||
unsigned short haddr4; /* user defined frm address 4 */
|
||||
unsigned short tmp; /* temp */
|
||||
unsigned short tmp_mb; /* temp */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*****************************************************************
|
||||
UART parameter RAM
|
||||
*****************************************************************/
|
||||
|
||||
/*
|
||||
* bits in uart control characters table
|
||||
*/
|
||||
#define CC_INVALID 0x8000 /* control character is valid */
|
||||
#define CC_REJ 0x4000 /* don't store char in buffer */
|
||||
#define CC_CHAR 0x00ff /* control character */
|
||||
|
||||
/* UART */
|
||||
struct uart_pram {
|
||||
/*
|
||||
* SCC parameter RAM
|
||||
*/
|
||||
unsigned short rbase; /* RX BD base address */
|
||||
unsigned short tbase; /* TX BD base address */
|
||||
unsigned char rfcr; /* Rx function code */
|
||||
unsigned char tfcr; /* Tx function code */
|
||||
unsigned short mrblr; /* Rx buffer length */
|
||||
unsigned long rstate; /* Rx internal state */
|
||||
unsigned long rptr; /* Rx internal data pointer */
|
||||
unsigned short rbptr; /* rb BD Pointer */
|
||||
unsigned short rcount; /* Rx internal byte count */
|
||||
unsigned long rx_temp; /* Rx temp */
|
||||
unsigned long tstate; /* Tx internal state */
|
||||
unsigned long tptr; /* Tx internal data pointer */
|
||||
unsigned short tbptr; /* Tx BD pointer */
|
||||
unsigned short tcount; /* Tx byte count */
|
||||
unsigned long ttemp; /* Tx temp */
|
||||
unsigned long rcrc; /* temp receive CRC */
|
||||
unsigned long tcrc; /* temp transmit CRC */
|
||||
|
||||
/*
|
||||
* UART specific parameter RAM
|
||||
*/
|
||||
unsigned char RESERVED1[8]; /* Reserved area */
|
||||
unsigned short max_idl; /* maximum idle characters */
|
||||
unsigned short idlc; /* rx idle counter (internal) */
|
||||
unsigned short brkcr; /* break count register */
|
||||
|
||||
unsigned short parec; /* Rx parity error counter */
|
||||
unsigned short frmer; /* Rx framing error counter */
|
||||
unsigned short nosec; /* Rx noise counter */
|
||||
unsigned short brkec; /* Rx break character counter */
|
||||
unsigned short brkln; /* Receive break length */
|
||||
|
||||
unsigned short uaddr1; /* address character 1 */
|
||||
unsigned short uaddr2; /* address character 2 */
|
||||
unsigned short rtemp; /* temp storage */
|
||||
unsigned short toseq; /* Tx out of sequence char */
|
||||
unsigned short cc[8]; /* Rx control characters */
|
||||
unsigned short rccm; /* Rx control char mask */
|
||||
unsigned short rccr; /* Rx control char register */
|
||||
unsigned short rlbc; /* Receive last break char */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*****************************************************************
|
||||
BISYNC parameter RAM
|
||||
*****************************************************************/
|
||||
|
||||
struct bisync_pram {
|
||||
/*
|
||||
* SCC parameter RAM
|
||||
*/
|
||||
unsigned short rbase; /* RX BD base address */
|
||||
unsigned short tbase; /* TX BD base address */
|
||||
unsigned char rfcr; /* Rx function code */
|
||||
unsigned char tfcr; /* Tx function code */
|
||||
unsigned short mrblr; /* Rx buffer length */
|
||||
unsigned long rstate; /* Rx internal state */
|
||||
unsigned long rptr; /* Rx internal data pointer */
|
||||
unsigned short rbptr; /* rb BD Pointer */
|
||||
unsigned short rcount; /* Rx internal byte count */
|
||||
unsigned long rtemp; /* Rx temp */
|
||||
unsigned long tstate; /* Tx internal state */
|
||||
unsigned long tptr; /* Tx internal data pointer */
|
||||
unsigned short tbptr; /* Tx BD pointer */
|
||||
unsigned short tcount; /* Tx byte count */
|
||||
unsigned long ttemp; /* Tx temp */
|
||||
unsigned long rcrc; /* temp receive CRC */
|
||||
unsigned long tcrc; /* temp transmit CRC */
|
||||
|
||||
/*
|
||||
* BISYNC specific parameter RAM
|
||||
*/
|
||||
unsigned char RESERVED1[4]; /* Reserved area */
|
||||
unsigned long crcc; /* CRC Constant Temp Value */
|
||||
unsigned short prcrc; /* Preset Receiver CRC-16/LRC */
|
||||
unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */
|
||||
unsigned short parec; /* Receive Parity Error Counter */
|
||||
unsigned short bsync; /* BISYNC SYNC Character */
|
||||
unsigned short bdle; /* BISYNC DLE Character */
|
||||
unsigned short cc[8]; /* Rx control characters */
|
||||
unsigned short rccm; /* Receive Control Character Mask */
|
||||
};
|
||||
|
||||
/*****************************************************************
|
||||
IOM2 parameter RAM
|
||||
(overlaid on tx bd[5] of SCC channel[2])
|
||||
*****************************************************************/
|
||||
struct iom2_pram {
|
||||
unsigned short ci_data; /* ci data */
|
||||
unsigned short monitor_data; /* monitor data */
|
||||
unsigned short tstate; /* transmitter state */
|
||||
unsigned short rstate; /* receiver state */
|
||||
};
|
||||
|
||||
/*****************************************************************
|
||||
SPI/SMC parameter RAM
|
||||
(overlaid on tx bd[6,7] of SCC channel[2])
|
||||
*****************************************************************/
|
||||
|
||||
#define SPI_R 0x8000 /* Ready bit in BD */
|
||||
|
||||
struct spi_pram {
|
||||
unsigned short rbase; /* Rx BD Base Address */
|
||||
unsigned short tbase; /* Tx BD Base Address */
|
||||
unsigned char rfcr; /* Rx function code */
|
||||
unsigned char tfcr; /* Tx function code */
|
||||
unsigned short mrblr; /* Rx buffer length */
|
||||
unsigned long rstate; /* Rx internal state */
|
||||
unsigned long rptr; /* Rx internal data pointer */
|
||||
unsigned short rbptr; /* rb BD Pointer */
|
||||
unsigned short rcount; /* Rx internal byte count */
|
||||
unsigned long rtemp; /* Rx temp */
|
||||
unsigned long tstate; /* Tx internal state */
|
||||
unsigned long tptr; /* Tx internal data pointer */
|
||||
unsigned short tbptr; /* Tx BD pointer */
|
||||
unsigned short tcount; /* Tx byte count */
|
||||
unsigned long ttemp; /* Tx temp */
|
||||
};
|
||||
|
||||
struct smc_uart_pram {
|
||||
unsigned short rbase; /* Rx BD Base Address */
|
||||
unsigned short tbase; /* Tx BD Base Address */
|
||||
unsigned char rfcr; /* Rx function code */
|
||||
unsigned char tfcr; /* Tx function code */
|
||||
unsigned short mrblr; /* Rx buffer length */
|
||||
unsigned long rstate; /* Rx internal state */
|
||||
unsigned long rptr; /* Rx internal data pointer */
|
||||
unsigned short rbptr; /* rb BD Pointer */
|
||||
unsigned short rcount; /* Rx internal byte count */
|
||||
unsigned long rtemp; /* Rx temp */
|
||||
unsigned long tstate; /* Tx internal state */
|
||||
unsigned long tptr; /* Tx internal data pointer */
|
||||
unsigned short tbptr; /* Tx BD pointer */
|
||||
unsigned short tcount; /* Tx byte count */
|
||||
unsigned long ttemp; /* Tx temp */
|
||||
unsigned short max_idl; /* Maximum IDLE Characters */
|
||||
unsigned short idlc; /* Temporary IDLE Counter */
|
||||
unsigned short brkln; /* Last Rx Break Length */
|
||||
unsigned short brkec; /* Rx Break Condition Counter */
|
||||
unsigned short brkcr; /* Break Count Register (Tx) */
|
||||
unsigned short r_mask; /* Temporary bit mask */
|
||||
};
|
||||
|
||||
struct smc_trnsp_pram {
|
||||
unsigned short rbase; /* rx BD Base Address */
|
||||
unsigned short tbase; /* Tx BD Base Address */
|
||||
unsigned char rfcr; /* Rx function code */
|
||||
unsigned char tfcr; /* Tx function code */
|
||||
unsigned short mrblr; /* Rx buffer length */
|
||||
unsigned long rstate; /* Rx internal state */
|
||||
unsigned long rptr; /* Rx internal data pointer */
|
||||
unsigned short rbptr; /* rb BD Pointer */
|
||||
unsigned short rcount; /* Rx internal byte count */
|
||||
unsigned long rtemp; /* Rx temp */
|
||||
unsigned long tstate; /* Tx internal state */
|
||||
unsigned long tptr; /* Tx internal data pointer */
|
||||
unsigned short tbptr; /* Tx BD pointer */
|
||||
unsigned short tcount; /* Tx byte count */
|
||||
unsigned long ttemp; /* Tx temp */
|
||||
unsigned short reserved[5]; /* Reserved */
|
||||
};
|
||||
|
||||
struct idma_pram {
|
||||
unsigned short ibase; /* IDMA BD Base Address */
|
||||
unsigned short ibptr; /* IDMA buffer descriptor pointer */
|
||||
unsigned long istate; /* IDMA internal state */
|
||||
unsigned long itemp; /* IDMA temp */
|
||||
};
|
||||
|
||||
struct ethernet_pram {
|
||||
/*
|
||||
* SCC parameter RAM
|
||||
*/
|
||||
unsigned short rbase; /* RX BD base address */
|
||||
unsigned short tbase; /* TX BD base address */
|
||||
unsigned char rfcr; /* Rx function code */
|
||||
unsigned char tfcr; /* Tx function code */
|
||||
unsigned short mrblr; /* Rx buffer length */
|
||||
unsigned long rstate; /* Rx internal state */
|
||||
unsigned long rptr; /* Rx internal data pointer */
|
||||
unsigned short rbptr; /* rb BD Pointer */
|
||||
unsigned short rcount; /* Rx internal byte count */
|
||||
unsigned long rtemp; /* Rx temp */
|
||||
unsigned long tstate; /* Tx internal state */
|
||||
unsigned long tptr; /* Tx internal data pointer */
|
||||
unsigned short tbptr; /* Tx BD pointer */
|
||||
unsigned short tcount; /* Tx byte count */
|
||||
unsigned long ttemp; /* Tx temp */
|
||||
unsigned long rcrc; /* temp receive CRC */
|
||||
unsigned long tcrc; /* temp transmit CRC */
|
||||
|
||||
/*
|
||||
* ETHERNET specific parameter RAM
|
||||
*/
|
||||
unsigned long c_pres; /* preset CRC */
|
||||
unsigned long c_mask; /* constant mask for CRC */
|
||||
unsigned long crcec; /* CRC error counter */
|
||||
unsigned long alec; /* alignment error counter */
|
||||
unsigned long disfc; /* discard frame counter */
|
||||
unsigned short pads; /* short frame PAD characters */
|
||||
unsigned short ret_lim; /* retry limit threshold */
|
||||
unsigned short ret_cnt; /* retry limit counter */
|
||||
unsigned short mflr; /* maximum frame length reg */
|
||||
unsigned short minflr; /* minimum frame length reg */
|
||||
unsigned short maxd1; /* maximum DMA1 length reg */
|
||||
unsigned short maxd2; /* maximum DMA2 length reg */
|
||||
unsigned short maxd; /* rx max DMA */
|
||||
unsigned short dma_cnt; /* rx dma counter */
|
||||
unsigned short max_b; /* max bd byte count */
|
||||
unsigned short gaddr1; /* group address filter 1 */
|
||||
unsigned short gaddr2; /* group address filter 2 */
|
||||
unsigned short gaddr3; /* group address filter 3 */
|
||||
unsigned short gaddr4; /* group address filter 4 */
|
||||
unsigned long tbuf0_data0; /* save area 0 - current frm */
|
||||
unsigned long tbuf0_data1; /* save area 1 - current frm */
|
||||
unsigned long tbuf0_rba0;
|
||||
unsigned long tbuf0_crc;
|
||||
unsigned short tbuf0_bcnt;
|
||||
union {
|
||||
unsigned char b[6];
|
||||
struct {
|
||||
unsigned short high;
|
||||
unsigned short middl;
|
||||
unsigned short low;
|
||||
} w;
|
||||
} paddr;
|
||||
unsigned short p_per; /* persistence */
|
||||
unsigned short rfbd_ptr; /* rx first bd pointer */
|
||||
unsigned short tfbd_ptr; /* tx first bd pointer */
|
||||
unsigned short tlbd_ptr; /* tx last bd pointer */
|
||||
unsigned long tbuf1_data0; /* save area 0 - next frame */
|
||||
unsigned long tbuf1_data1; /* save area 1 - next frame */
|
||||
unsigned long tbuf1_rba0;
|
||||
unsigned long tbuf1_crc;
|
||||
unsigned short tbuf1_bcnt;
|
||||
unsigned short tx_len; /* tx frame length counter */
|
||||
unsigned short iaddr1; /* individual address filter 1*/
|
||||
unsigned short iaddr2; /* individual address filter 2*/
|
||||
unsigned short iaddr3; /* individual address filter 3*/
|
||||
unsigned short iaddr4; /* individual address filter 4*/
|
||||
unsigned short boff_cnt; /* back-off counter */
|
||||
unsigned short taddr_h; /* temp address (MSB) */
|
||||
unsigned short taddr_m; /* temp address */
|
||||
unsigned short taddr_l; /* temp address (LSB) */
|
||||
};
|
||||
|
||||
struct transparent_pram {
|
||||
/*
|
||||
* SCC parameter RAM
|
||||
*/
|
||||
unsigned short rbase; /* RX BD base address */
|
||||
unsigned short tbase; /* TX BD base address */
|
||||
unsigned char rfcr; /* Rx function code */
|
||||
unsigned char tfcr; /* Tx function code */
|
||||
unsigned short mrblr; /* Rx buffer length */
|
||||
unsigned long rstate; /* Rx internal state */
|
||||
unsigned long rptr; /* Rx internal data pointer */
|
||||
unsigned short rbptr; /* rb BD Pointer */
|
||||
unsigned short rcount; /* Rx internal byte count */
|
||||
unsigned long rtemp; /* Rx temp */
|
||||
unsigned long tstate; /* Tx internal state */
|
||||
unsigned long tptr; /* Tx internal data pointer */
|
||||
unsigned short tbptr; /* Tx BD pointer */
|
||||
unsigned short tcount; /* Tx byte count */
|
||||
unsigned long ttemp; /* Tx temp */
|
||||
unsigned long rcrc; /* temp receive CRC */
|
||||
unsigned long tcrc; /* temp transmit CRC */
|
||||
|
||||
/*
|
||||
* TRANSPARENT specific parameter RAM
|
||||
*/
|
||||
unsigned long crc_p; /* CRC Preset */
|
||||
unsigned long crc_c; /* CRC constant */
|
||||
};
|
||||
|
||||
struct timer_pram {
|
||||
/*
|
||||
* RISC timers parameter RAM
|
||||
*/
|
||||
unsigned short tm_base; /* RISC timer table base adr */
|
||||
unsigned short tm_ptr; /* RISC timer table pointer */
|
||||
unsigned short r_tmr; /* RISC timer mode register */
|
||||
unsigned short r_tmv; /* RISC timer valid register */
|
||||
unsigned long tm_cmd; /* RISC timer cmd register */
|
||||
unsigned long tm_cnt; /* RISC timer internal cnt */
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -1,362 +0,0 @@
|
||||
/***********************************
|
||||
* $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
|
||||
***********************************
|
||||
*
|
||||
***************************************
|
||||
* Definitions of QUICC memory structures
|
||||
***************************************
|
||||
*/
|
||||
|
||||
#ifndef __M68360_QUICC_H
|
||||
#define __M68360_QUICC_H
|
||||
|
||||
/*
|
||||
* include registers and
|
||||
* parameter ram definitions files
|
||||
*/
|
||||
#include <asm/m68360_regs.h>
|
||||
#include <asm/m68360_pram.h>
|
||||
|
||||
|
||||
|
||||
/* Buffer Descriptors */
|
||||
typedef struct quicc_bd {
|
||||
volatile unsigned short status;
|
||||
volatile unsigned short length;
|
||||
volatile unsigned char *buf; /* WARNING: This is only true if *char is 32 bits */
|
||||
} QUICC_BD;
|
||||
|
||||
|
||||
#ifdef MOTOROLA_ORIGINAL
|
||||
struct user_data {
|
||||
/* BASE + 0x000: user data memory */
|
||||
volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
|
||||
volatile unsigned char udata_bd[0x200]; /*user data Ucode */
|
||||
volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */
|
||||
volatile unsigned char RESERVED1[0x500]; /* Reserved area */
|
||||
};
|
||||
#else
|
||||
struct user_data {
|
||||
/* BASE + 0x000: user data memory */
|
||||
volatile unsigned char udata_bd_ucode[0x400]; /* user data, bds, Ucode*/
|
||||
volatile unsigned char udata_bd1[0x200]; /* user, bds */
|
||||
volatile unsigned char ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */
|
||||
volatile unsigned char udata_bd2[0x100]; /* user, bds */
|
||||
volatile unsigned char RESERVED1[0x400]; /* Reserved area */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* internal ram
|
||||
*/
|
||||
typedef struct quicc {
|
||||
union {
|
||||
struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */
|
||||
struct user_data u;
|
||||
}ch_or_u; /* multipul or user space */
|
||||
|
||||
/* BASE + 0xc00: PARAMETER RAM */
|
||||
union {
|
||||
struct scc_pram {
|
||||
union {
|
||||
struct hdlc_pram h;
|
||||
struct uart_pram u;
|
||||
struct bisync_pram b;
|
||||
struct transparent_pram t;
|
||||
unsigned char RESERVED66[0x70];
|
||||
} pscc; /* scc parameter area (protocol dependent) */
|
||||
union {
|
||||
struct {
|
||||
unsigned char RESERVED70[0x10];
|
||||
struct spi_pram spi;
|
||||
unsigned char RESERVED72[0x8];
|
||||
struct timer_pram timer;
|
||||
} timer_spi;
|
||||
struct {
|
||||
struct idma_pram idma;
|
||||
unsigned char RESERVED67[0x4];
|
||||
union {
|
||||
struct smc_uart_pram u;
|
||||
struct smc_trnsp_pram t;
|
||||
} psmc;
|
||||
} idma_smc;
|
||||
} pothers;
|
||||
} scc;
|
||||
struct ethernet_pram enet_scc;
|
||||
struct global_multi_pram m;
|
||||
unsigned char pr[0x100];
|
||||
} pram[4];
|
||||
|
||||
/* reserved */
|
||||
|
||||
/* BASE + 0x1000: INTERNAL REGISTERS */
|
||||
/* SIM */
|
||||
volatile unsigned long sim_mcr; /* module configuration reg */
|
||||
volatile unsigned short sim_simtr; /* module test register */
|
||||
volatile unsigned char RESERVED2[0x2]; /* Reserved area */
|
||||
volatile unsigned char sim_avr; /* auto vector reg */
|
||||
volatile unsigned char sim_rsr; /* reset status reg */
|
||||
volatile unsigned char RESERVED3[0x2]; /* Reserved area */
|
||||
volatile unsigned char sim_clkocr; /* CLCO control register */
|
||||
volatile unsigned char RESERVED62[0x3]; /* Reserved area */
|
||||
volatile unsigned short sim_pllcr; /* PLL control register */
|
||||
volatile unsigned char RESERVED63[0x2]; /* Reserved area */
|
||||
volatile unsigned short sim_cdvcr; /* Clock devider control register */
|
||||
volatile unsigned short sim_pepar; /* Port E pin assignment register */
|
||||
volatile unsigned char RESERVED64[0xa]; /* Reserved area */
|
||||
volatile unsigned char sim_sypcr; /* system protection control*/
|
||||
volatile unsigned char sim_swiv; /* software interrupt vector*/
|
||||
volatile unsigned char RESERVED6[0x2]; /* Reserved area */
|
||||
volatile unsigned short sim_picr; /* periodic interrupt control reg */
|
||||
volatile unsigned char RESERVED7[0x2]; /* Reserved area */
|
||||
volatile unsigned short sim_pitr; /* periodic interrupt timing reg */
|
||||
volatile unsigned char RESERVED8[0x3]; /* Reserved area */
|
||||
volatile unsigned char sim_swsr; /* software service */
|
||||
volatile unsigned long sim_bkar; /* breakpoint address register*/
|
||||
volatile unsigned long sim_bkcr; /* breakpoint control register*/
|
||||
volatile unsigned char RESERVED10[0x8]; /* Reserved area */
|
||||
/* MEMC */
|
||||
volatile unsigned long memc_gmr; /* Global memory register */
|
||||
volatile unsigned short memc_mstat; /* MEMC status register */
|
||||
volatile unsigned char RESERVED11[0xa]; /* Reserved area */
|
||||
volatile unsigned long memc_br0; /* base register 0 */
|
||||
volatile unsigned long memc_or0; /* option register 0 */
|
||||
volatile unsigned char RESERVED12[0x8]; /* Reserved area */
|
||||
volatile unsigned long memc_br1; /* base register 1 */
|
||||
volatile unsigned long memc_or1; /* option register 1 */
|
||||
volatile unsigned char RESERVED13[0x8]; /* Reserved area */
|
||||
volatile unsigned long memc_br2; /* base register 2 */
|
||||
volatile unsigned long memc_or2; /* option register 2 */
|
||||
volatile unsigned char RESERVED14[0x8]; /* Reserved area */
|
||||
volatile unsigned long memc_br3; /* base register 3 */
|
||||
volatile unsigned long memc_or3; /* option register 3 */
|
||||
volatile unsigned char RESERVED15[0x8]; /* Reserved area */
|
||||
volatile unsigned long memc_br4; /* base register 3 */
|
||||
volatile unsigned long memc_or4; /* option register 3 */
|
||||
volatile unsigned char RESERVED16[0x8]; /* Reserved area */
|
||||
volatile unsigned long memc_br5; /* base register 3 */
|
||||
volatile unsigned long memc_or5; /* option register 3 */
|
||||
volatile unsigned char RESERVED17[0x8]; /* Reserved area */
|
||||
volatile unsigned long memc_br6; /* base register 3 */
|
||||
volatile unsigned long memc_or6; /* option register 3 */
|
||||
volatile unsigned char RESERVED18[0x8]; /* Reserved area */
|
||||
volatile unsigned long memc_br7; /* base register 3 */
|
||||
volatile unsigned long memc_or7; /* option register 3 */
|
||||
volatile unsigned char RESERVED9[0x28]; /* Reserved area */
|
||||
/* TEST */
|
||||
volatile unsigned short test_tstmra; /* master shift a */
|
||||
volatile unsigned short test_tstmrb; /* master shift b */
|
||||
volatile unsigned short test_tstsc; /* shift count */
|
||||
volatile unsigned short test_tstrc; /* repetition counter */
|
||||
volatile unsigned short test_creg; /* control */
|
||||
volatile unsigned short test_dreg; /* destributed register */
|
||||
volatile unsigned char RESERVED58[0x404]; /* Reserved area */
|
||||
/* IDMA1 */
|
||||
volatile unsigned short idma_iccr; /* channel configuration reg*/
|
||||
volatile unsigned char RESERVED19[0x2]; /* Reserved area */
|
||||
volatile unsigned short idma1_cmr; /* dma mode reg */
|
||||
volatile unsigned char RESERVED68[0x2]; /* Reserved area */
|
||||
volatile unsigned long idma1_sapr; /* dma source addr ptr */
|
||||
volatile unsigned long idma1_dapr; /* dma destination addr ptr */
|
||||
volatile unsigned long idma1_bcr; /* dma byte count reg */
|
||||
volatile unsigned char idma1_fcr; /* function code reg */
|
||||
volatile unsigned char RESERVED20; /* Reserved area */
|
||||
volatile unsigned char idma1_cmar; /* channel mask reg */
|
||||
volatile unsigned char RESERVED21; /* Reserved area */
|
||||
volatile unsigned char idma1_csr; /* channel status reg */
|
||||
volatile unsigned char RESERVED22[0x3]; /* Reserved area */
|
||||
/* SDMA */
|
||||
volatile unsigned char sdma_sdsr; /* status reg */
|
||||
volatile unsigned char RESERVED23; /* Reserved area */
|
||||
volatile unsigned short sdma_sdcr; /* configuration reg */
|
||||
volatile unsigned long sdma_sdar; /* address reg */
|
||||
/* IDMA2 */
|
||||
volatile unsigned char RESERVED69[0x2]; /* Reserved area */
|
||||
volatile unsigned short idma2_cmr; /* dma mode reg */
|
||||
volatile unsigned long idma2_sapr; /* dma source addr ptr */
|
||||
volatile unsigned long idma2_dapr; /* dma destination addr ptr */
|
||||
volatile unsigned long idma2_bcr; /* dma byte count reg */
|
||||
volatile unsigned char idma2_fcr; /* function code reg */
|
||||
volatile unsigned char RESERVED24; /* Reserved area */
|
||||
volatile unsigned char idma2_cmar; /* channel mask reg */
|
||||
volatile unsigned char RESERVED25; /* Reserved area */
|
||||
volatile unsigned char idma2_csr; /* channel status reg */
|
||||
volatile unsigned char RESERVED26[0x7]; /* Reserved area */
|
||||
/* Interrupt Controller */
|
||||
volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/
|
||||
volatile unsigned long intr_cipr; /* CP interrupt pending reg */
|
||||
volatile unsigned long intr_cimr; /* CP interrupt mask reg */
|
||||
volatile unsigned long intr_cisr; /* CP interrupt in service reg*/
|
||||
/* Parallel I/O */
|
||||
volatile unsigned short pio_padir; /* port A data direction reg */
|
||||
volatile unsigned short pio_papar; /* port A pin assignment reg */
|
||||
volatile unsigned short pio_paodr; /* port A open drain reg */
|
||||
volatile unsigned short pio_padat; /* port A data register */
|
||||
volatile unsigned char RESERVED28[0x8]; /* Reserved area */
|
||||
volatile unsigned short pio_pcdir; /* port C data direction reg*/
|
||||
volatile unsigned short pio_pcpar; /* port C pin assignment reg*/
|
||||
volatile unsigned short pio_pcso; /* port C special options */
|
||||
volatile unsigned short pio_pcdat; /* port C data register */
|
||||
volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
|
||||
volatile unsigned char RESERVED29[0x16]; /* Reserved area */
|
||||
/* Timer */
|
||||
volatile unsigned short timer_tgcr; /* timer global configuration reg */
|
||||
volatile unsigned char RESERVED30[0xe]; /* Reserved area */
|
||||
volatile unsigned short timer_tmr1; /* timer 1 mode reg */
|
||||
volatile unsigned short timer_tmr2; /* timer 2 mode reg */
|
||||
volatile unsigned short timer_trr1; /* timer 1 referance reg */
|
||||
volatile unsigned short timer_trr2; /* timer 2 referance reg */
|
||||
volatile unsigned short timer_tcr1; /* timer 1 capture reg */
|
||||
volatile unsigned short timer_tcr2; /* timer 2 capture reg */
|
||||
volatile unsigned short timer_tcn1; /* timer 1 counter reg */
|
||||
volatile unsigned short timer_tcn2; /* timer 2 counter reg */
|
||||
volatile unsigned short timer_tmr3; /* timer 3 mode reg */
|
||||
volatile unsigned short timer_tmr4; /* timer 4 mode reg */
|
||||
volatile unsigned short timer_trr3; /* timer 3 referance reg */
|
||||
volatile unsigned short timer_trr4; /* timer 4 referance reg */
|
||||
volatile unsigned short timer_tcr3; /* timer 3 capture reg */
|
||||
volatile unsigned short timer_tcr4; /* timer 4 capture reg */
|
||||
volatile unsigned short timer_tcn3; /* timer 3 counter reg */
|
||||
volatile unsigned short timer_tcn4; /* timer 4 counter reg */
|
||||
volatile unsigned short timer_ter1; /* timer 1 event reg */
|
||||
volatile unsigned short timer_ter2; /* timer 2 event reg */
|
||||
volatile unsigned short timer_ter3; /* timer 3 event reg */
|
||||
volatile unsigned short timer_ter4; /* timer 4 event reg */
|
||||
volatile unsigned char RESERVED34[0x8]; /* Reserved area */
|
||||
/* CP */
|
||||
volatile unsigned short cp_cr; /* command register */
|
||||
volatile unsigned char RESERVED35[0x2]; /* Reserved area */
|
||||
volatile unsigned short cp_rccr; /* main configuration reg */
|
||||
volatile unsigned char RESERVED37; /* Reserved area */
|
||||
volatile unsigned char cp_rmds; /* development support status reg */
|
||||
volatile unsigned long cp_rmdr; /* development support control reg */
|
||||
volatile unsigned short cp_rctr1; /* ram break register 1 */
|
||||
volatile unsigned short cp_rctr2; /* ram break register 2 */
|
||||
volatile unsigned short cp_rctr3; /* ram break register 3 */
|
||||
volatile unsigned short cp_rctr4; /* ram break register 4 */
|
||||
volatile unsigned char RESERVED59[0x2]; /* Reserved area */
|
||||
volatile unsigned short cp_rter; /* RISC timers event reg */
|
||||
volatile unsigned char RESERVED38[0x2]; /* Reserved area */
|
||||
volatile unsigned short cp_rtmr; /* RISC timers mask reg */
|
||||
volatile unsigned char RESERVED39[0x14]; /* Reserved area */
|
||||
/* BRG */
|
||||
union {
|
||||
volatile unsigned long l;
|
||||
struct {
|
||||
volatile unsigned short BRGC_RESERV:14;
|
||||
volatile unsigned short rst:1;
|
||||
volatile unsigned short en:1;
|
||||
volatile unsigned short extc:2;
|
||||
volatile unsigned short atb:1;
|
||||
volatile unsigned short cd:12;
|
||||
volatile unsigned short div16:1;
|
||||
} b;
|
||||
} brgc[4]; /* BRG1-BRG4 configuration regs*/
|
||||
/* SCC registers */
|
||||
struct scc_regs {
|
||||
union {
|
||||
struct {
|
||||
/* Low word. */
|
||||
volatile unsigned short GSMR_RESERV2:1;
|
||||
volatile unsigned short edge:2;
|
||||
volatile unsigned short tci:1;
|
||||
volatile unsigned short tsnc:2;
|
||||
volatile unsigned short rinv:1;
|
||||
volatile unsigned short tinv:1;
|
||||
volatile unsigned short tpl:3;
|
||||
volatile unsigned short tpp:2;
|
||||
volatile unsigned short tend:1;
|
||||
volatile unsigned short tdcr:2;
|
||||
volatile unsigned short rdcr:2;
|
||||
volatile unsigned short renc:3;
|
||||
volatile unsigned short tenc:3;
|
||||
volatile unsigned short diag:2;
|
||||
volatile unsigned short enr:1;
|
||||
volatile unsigned short ent:1;
|
||||
volatile unsigned short mode:4;
|
||||
/* High word. */
|
||||
volatile unsigned short GSMR_RESERV1:14;
|
||||
volatile unsigned short pri:1;
|
||||
volatile unsigned short gde:1;
|
||||
volatile unsigned short tcrc:2;
|
||||
volatile unsigned short revd:1;
|
||||
volatile unsigned short trx:1;
|
||||
volatile unsigned short ttx:1;
|
||||
volatile unsigned short cdp:1;
|
||||
volatile unsigned short ctsp:1;
|
||||
volatile unsigned short cds:1;
|
||||
volatile unsigned short ctss:1;
|
||||
volatile unsigned short tfl:1;
|
||||
volatile unsigned short rfw:1;
|
||||
volatile unsigned short txsy:1;
|
||||
volatile unsigned short synl:2;
|
||||
volatile unsigned short rtsm:1;
|
||||
volatile unsigned short rsyn:1;
|
||||
} b;
|
||||
struct {
|
||||
volatile unsigned long low;
|
||||
volatile unsigned long high;
|
||||
} w;
|
||||
} scc_gsmr; /* SCC general mode reg */
|
||||
volatile unsigned short scc_psmr; /* protocol specific mode reg */
|
||||
volatile unsigned char RESERVED42[0x2]; /* Reserved area */
|
||||
volatile unsigned short scc_todr; /* SCC transmit on demand */
|
||||
volatile unsigned short scc_dsr; /* SCC data sync reg */
|
||||
volatile unsigned short scc_scce; /* SCC event reg */
|
||||
volatile unsigned char RESERVED43[0x2];/* Reserved area */
|
||||
volatile unsigned short scc_sccm; /* SCC mask reg */
|
||||
volatile unsigned char RESERVED44[0x1];/* Reserved area */
|
||||
volatile unsigned char scc_sccs; /* SCC status reg */
|
||||
volatile unsigned char RESERVED45[0x8]; /* Reserved area */
|
||||
} scc_regs[4];
|
||||
/* SMC */
|
||||
struct smc_regs {
|
||||
volatile unsigned char RESERVED46[0x2]; /* Reserved area */
|
||||
volatile unsigned short smc_smcmr; /* SMC mode reg */
|
||||
volatile unsigned char RESERVED60[0x2]; /* Reserved area */
|
||||
volatile unsigned char smc_smce; /* SMC event reg */
|
||||
volatile unsigned char RESERVED47[0x3]; /* Reserved area */
|
||||
volatile unsigned char smc_smcm; /* SMC mask reg */
|
||||
volatile unsigned char RESERVED48[0x5]; /* Reserved area */
|
||||
} smc_regs[2];
|
||||
/* SPI */
|
||||
volatile unsigned short spi_spmode; /* SPI mode reg */
|
||||
volatile unsigned char RESERVED51[0x4]; /* Reserved area */
|
||||
volatile unsigned char spi_spie; /* SPI event reg */
|
||||
volatile unsigned char RESERVED52[0x3]; /* Reserved area */
|
||||
volatile unsigned char spi_spim; /* SPI mask reg */
|
||||
volatile unsigned char RESERVED53[0x2]; /* Reserved area */
|
||||
volatile unsigned char spi_spcom; /* SPI command reg */
|
||||
volatile unsigned char RESERVED54[0x4]; /* Reserved area */
|
||||
/* PIP */
|
||||
volatile unsigned short pip_pipc; /* pip configuration reg */
|
||||
volatile unsigned char RESERVED65[0x2]; /* Reserved area */
|
||||
volatile unsigned short pip_ptpr; /* pip timing parameters reg */
|
||||
volatile unsigned long pip_pbdir; /* port b data direction reg */
|
||||
volatile unsigned long pip_pbpar; /* port b pin assignment reg */
|
||||
volatile unsigned long pip_pbodr; /* port b open drain reg */
|
||||
volatile unsigned long pip_pbdat; /* port b data reg */
|
||||
volatile unsigned char RESERVED71[0x18]; /* Reserved area */
|
||||
/* Serial Interface */
|
||||
volatile unsigned long si_simode; /* SI mode register */
|
||||
volatile unsigned char si_sigmr; /* SI global mode register */
|
||||
volatile unsigned char RESERVED55; /* Reserved area */
|
||||
volatile unsigned char si_sistr; /* SI status register */
|
||||
volatile unsigned char si_sicmr; /* SI command register */
|
||||
volatile unsigned char RESERVED56[0x4]; /* Reserved area */
|
||||
volatile unsigned long si_sicr; /* SI clock routing */
|
||||
volatile unsigned long si_sirp; /* SI ram pointers */
|
||||
volatile unsigned char RESERVED57[0xc]; /* Reserved area */
|
||||
volatile unsigned short si_siram[0x80]; /* SI routing ram */
|
||||
} QUICC;
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Local variables:
|
||||
* c-indent-level: 4
|
||||
* c-basic-offset: 4
|
||||
* tab-width: 4
|
||||
* End:
|
||||
*/
|
||||
@@ -1,408 +0,0 @@
|
||||
/***********************************
|
||||
* $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $
|
||||
***********************************
|
||||
*
|
||||
***************************************
|
||||
* Definitions of the QUICC registers
|
||||
***************************************
|
||||
*/
|
||||
|
||||
#ifndef __REGISTERS_H
|
||||
#define __REGISTERS_H
|
||||
|
||||
#define CLEAR_BIT(x, bit) x =bit
|
||||
|
||||
/*****************************************************************
|
||||
Command Register
|
||||
*****************************************************************/
|
||||
|
||||
/* bit fields within command register */
|
||||
#define SOFTWARE_RESET 0x8000
|
||||
#define CMD_OPCODE 0x0f00
|
||||
#define CMD_CHANNEL 0x00f0
|
||||
#define CMD_FLAG 0x0001
|
||||
|
||||
/* general command opcodes */
|
||||
#define INIT_RXTX_PARAMS 0x0000
|
||||
#define INIT_RX_PARAMS 0x0100
|
||||
#define INIT_TX_PARAMS 0x0200
|
||||
#define ENTER_HUNT_MODE 0x0300
|
||||
#define STOP_TX 0x0400
|
||||
#define GR_STOP_TX 0x0500
|
||||
#define RESTART_TX 0x0600
|
||||
#define CLOSE_RX_BD 0x0700
|
||||
#define SET_ENET_GROUP 0x0800
|
||||
#define RESET_ENET_GROUP 0x0900
|
||||
|
||||
/* quicc32 CP commands */
|
||||
#define STOP_TX_32 0x0e00 /*add chan# bits 2-6 */
|
||||
#define ENTER_HUNT_MODE_32 0x1e00
|
||||
|
||||
/* quicc32 mask/event SCC register */
|
||||
#define GOV 0x01
|
||||
#define GUN 0x02
|
||||
#define GINT 0x04
|
||||
#define IQOV 0x08
|
||||
|
||||
|
||||
/* Timer commands */
|
||||
#define SET_TIMER 0x0800
|
||||
|
||||
/* Multi channel Interrupt structure */
|
||||
#define INTR_VALID 0x8000 /* Valid interrupt entry */
|
||||
#define INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */
|
||||
#define INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */
|
||||
#define INTR_MASK_BITS 0x383f
|
||||
|
||||
/*
|
||||
* General SCC mode register (GSMR)
|
||||
*/
|
||||
|
||||
#define MODE_HDLC 0x0
|
||||
#define MODE_APPLE_TALK 0x2
|
||||
#define MODE_SS7 0x3
|
||||
#define MODE_UART 0x4
|
||||
#define MODE_PROFIBUS 0x5
|
||||
#define MODE_ASYNC_HDLC 0x6
|
||||
#define MODE_V14 0x7
|
||||
#define MODE_BISYNC 0x8
|
||||
#define MODE_DDCMP 0x9
|
||||
#define MODE_MULTI_CHANNEL 0xa
|
||||
#define MODE_ETHERNET 0xc
|
||||
|
||||
#define DIAG_NORMAL 0x0
|
||||
#define DIAG_LOCAL_LPB 0x1
|
||||
#define DIAG_AUTO_ECHO 0x2
|
||||
#define DIAG_LBP_ECHO 0x3
|
||||
|
||||
/* For RENC and TENC fields in GSMR */
|
||||
#define ENC_NRZ 0x0
|
||||
#define ENC_NRZI 0x1
|
||||
#define ENC_FM0 0x2
|
||||
#define ENC_MANCH 0x4
|
||||
#define ENC_DIFF_MANC 0x6
|
||||
|
||||
/* For TDCR and RDCR fields in GSMR */
|
||||
#define CLOCK_RATE_1 0x0
|
||||
#define CLOCK_RATE_8 0x1
|
||||
#define CLOCK_RATE_16 0x2
|
||||
#define CLOCK_RATE_32 0x3
|
||||
|
||||
#define TPP_00 0x0
|
||||
#define TPP_10 0x1
|
||||
#define TPP_01 0x2
|
||||
#define TPP_11 0x3
|
||||
|
||||
#define TPL_NO 0x0
|
||||
#define TPL_8 0x1
|
||||
#define TPL_16 0x2
|
||||
#define TPL_32 0x3
|
||||
#define TPL_48 0x4
|
||||
#define TPL_64 0x5
|
||||
#define TPL_128 0x6
|
||||
|
||||
#define TSNC_INFINITE 0x0
|
||||
#define TSNC_14_65 0x1
|
||||
#define TSNC_4_15 0x2
|
||||
#define TSNC_3_1 0x3
|
||||
|
||||
#define EDGE_BOTH 0x0
|
||||
#define EDGE_POS 0x1
|
||||
#define EDGE_NEG 0x2
|
||||
#define EDGE_NO 0x3
|
||||
|
||||
#define SYNL_NO 0x0
|
||||
#define SYNL_4 0x1
|
||||
#define SYNL_8 0x2
|
||||
#define SYNL_16 0x3
|
||||
|
||||
#define TCRC_CCITT16 0x0
|
||||
#define TCRC_CRC16 0x1
|
||||
#define TCRC_CCITT32 0x2
|
||||
|
||||
|
||||
/*****************************************************************
|
||||
TODR (Transmit on demand) Register
|
||||
*****************************************************************/
|
||||
#define TODR_TOD 0x8000 /* Transmit on demand */
|
||||
|
||||
|
||||
/*****************************************************************
|
||||
CICR register settings
|
||||
*****************************************************************/
|
||||
|
||||
/* note that relative irq priorities of the SCCs can be reordered
|
||||
* if desired - see p. 7-377 of the MC68360UM */
|
||||
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
|
||||
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
|
||||
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
|
||||
#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
|
||||
|
||||
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
|
||||
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
|
||||
#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */
|
||||
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
|
||||
|
||||
|
||||
/*****************************************************************
|
||||
Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379)
|
||||
*****************************************************************/
|
||||
|
||||
#define INTR_PIO_PC0 0x80000000 /* parallel I/O C bit 0 */
|
||||
#define INTR_SCC1 0x40000000 /* SCC port 1 */
|
||||
#define INTR_SCC2 0x20000000 /* SCC port 2 */
|
||||
#define INTR_SCC3 0x10000000 /* SCC port 3 */
|
||||
#define INTR_SCC4 0x08000000 /* SCC port 4 */
|
||||
#define INTR_PIO_PC1 0x04000000 /* parallel i/o C bit 1 */
|
||||
#define INTR_TIMER1 0x02000000 /* timer 1 */
|
||||
#define INTR_PIO_PC2 0x01000000 /* parallel i/o C bit 2 */
|
||||
#define INTR_PIO_PC3 0x00800000 /* parallel i/o C bit 3 */
|
||||
#define INTR_SDMA_BERR 0x00400000 /* SDMA channel bus error */
|
||||
#define INTR_DMA1 0x00200000 /* idma 1 */
|
||||
#define INTR_DMA2 0x00100000 /* idma 2 */
|
||||
#define INTR_TIMER2 0x00040000 /* timer 2 */
|
||||
#define INTR_CP_TIMER 0x00020000 /* CP timer */
|
||||
#define INTR_PIP_STATUS 0x00010000 /* PIP status */
|
||||
#define INTR_PIO_PC4 0x00008000 /* parallel i/o C bit 4 */
|
||||
#define INTR_PIO_PC5 0x00004000 /* parallel i/o C bit 5 */
|
||||
#define INTR_TIMER3 0x00001000 /* timer 3 */
|
||||
#define INTR_PIO_PC6 0x00000800 /* parallel i/o C bit 6 */
|
||||
#define INTR_PIO_PC7 0x00000400 /* parallel i/o C bit 7 */
|
||||
#define INTR_PIO_PC8 0x00000200 /* parallel i/o C bit 8 */
|
||||
#define INTR_TIMER4 0x00000080 /* timer 4 */
|
||||
#define INTR_PIO_PC9 0x00000040 /* parallel i/o C bit 9 */
|
||||
#define INTR_SCP 0x00000020 /* SCP */
|
||||
#define INTR_SMC1 0x00000010 /* SMC 1 */
|
||||
#define INTR_SMC2 0x00000008 /* SMC 2 */
|
||||
#define INTR_PIO_PC10 0x00000004 /* parallel i/o C bit 10 */
|
||||
#define INTR_PIO_PC11 0x00000002 /* parallel i/o C bit 11 */
|
||||
#define INTR_ERR 0x00000001 /* error */
|
||||
|
||||
|
||||
/*****************************************************************
|
||||
CPM Interrupt vector encodings (MC68360UM p. 7-376)
|
||||
*****************************************************************/
|
||||
|
||||
#define CPMVEC_NR 32
|
||||
#define CPMVEC_PIO_PC0 0x1f
|
||||
#define CPMVEC_SCC1 0x1e
|
||||
#define CPMVEC_SCC2 0x1d
|
||||
#define CPMVEC_SCC3 0x1c
|
||||
#define CPMVEC_SCC4 0x1b
|
||||
#define CPMVEC_PIO_PC1 0x1a
|
||||
#define CPMVEC_TIMER1 0x19
|
||||
#define CPMVEC_PIO_PC2 0x18
|
||||
#define CPMVEC_PIO_PC3 0x17
|
||||
#define CPMVEC_SDMA_CB_ERR 0x16
|
||||
#define CPMVEC_IDMA1 0x15
|
||||
#define CPMVEC_IDMA2 0x14
|
||||
#define CPMVEC_RESERVED3 0x13
|
||||
#define CPMVEC_TIMER2 0x12
|
||||
#define CPMVEC_RISCTIMER 0x11
|
||||
#define CPMVEC_RESERVED2 0x10
|
||||
#define CPMVEC_PIO_PC4 0x0f
|
||||
#define CPMVEC_PIO_PC5 0x0e
|
||||
#define CPMVEC_TIMER3 0x0c
|
||||
#define CPMVEC_PIO_PC6 0x0b
|
||||
#define CPMVEC_PIO_PC7 0x0a
|
||||
#define CPMVEC_PIO_PC8 0x09
|
||||
#define CPMVEC_RESERVED1 0x08
|
||||
#define CPMVEC_TIMER4 0x07
|
||||
#define CPMVEC_PIO_PC9 0x06
|
||||
#define CPMVEC_SPI 0x05
|
||||
#define CPMVEC_SMC1 0x04
|
||||
#define CPMVEC_SMC2 0x03
|
||||
#define CPMVEC_PIO_PC10 0x02
|
||||
#define CPMVEC_PIO_PC11 0x01
|
||||
#define CPMVEC_ERROR 0x00
|
||||
|
||||
/* #define CPMVEC_PIO_PC0 ((ushort)0x1f) */
|
||||
/* #define CPMVEC_SCC1 ((ushort)0x1e) */
|
||||
/* #define CPMVEC_SCC2 ((ushort)0x1d) */
|
||||
/* #define CPMVEC_SCC3 ((ushort)0x1c) */
|
||||
/* #define CPMVEC_SCC4 ((ushort)0x1b) */
|
||||
/* #define CPMVEC_PIO_PC1 ((ushort)0x1a) */
|
||||
/* #define CPMVEC_TIMER1 ((ushort)0x19) */
|
||||
/* #define CPMVEC_PIO_PC2 ((ushort)0x18) */
|
||||
/* #define CPMVEC_PIO_PC3 ((ushort)0x17) */
|
||||
/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
|
||||
/* #define CPMVEC_IDMA1 ((ushort)0x15) */
|
||||
/* #define CPMVEC_IDMA2 ((ushort)0x14) */
|
||||
/* #define CPMVEC_RESERVED3 ((ushort)0x13) */
|
||||
/* #define CPMVEC_TIMER2 ((ushort)0x12) */
|
||||
/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
|
||||
/* #define CPMVEC_RESERVED2 ((ushort)0x10) */
|
||||
/* #define CPMVEC_PIO_PC4 ((ushort)0x0f) */
|
||||
/* #define CPMVEC_PIO_PC5 ((ushort)0x0e) */
|
||||
/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
|
||||
/* #define CPMVEC_PIO_PC6 ((ushort)0x0b) */
|
||||
/* #define CPMVEC_PIO_PC7 ((ushort)0x0a) */
|
||||
/* #define CPMVEC_PIO_PC8 ((ushort)0x09) */
|
||||
/* #define CPMVEC_RESERVED1 ((ushort)0x08) */
|
||||
/* #define CPMVEC_TIMER4 ((ushort)0x07) */
|
||||
/* #define CPMVEC_PIO_PC9 ((ushort)0x06) */
|
||||
/* #define CPMVEC_SPI ((ushort)0x05) */
|
||||
/* #define CPMVEC_SMC1 ((ushort)0x04) */
|
||||
/* #define CPMVEC_SMC2 ((ushort)0x03) */
|
||||
/* #define CPMVEC_PIO_PC10 ((ushort)0x02) */
|
||||
/* #define CPMVEC_PIO_PC11 ((ushort)0x01) */
|
||||
/* #define CPMVEC_ERROR ((ushort)0x00) */
|
||||
|
||||
|
||||
/*****************************************************************
|
||||
* PIO control registers
|
||||
*****************************************************************/
|
||||
|
||||
/* Port A - See 360UM p. 7-358
|
||||
*
|
||||
* Note that most of these pins have alternate functions
|
||||
*/
|
||||
|
||||
|
||||
/* The macros are nice, but there are all sorts of references to 1-indexed
|
||||
* facilities on the 68360... */
|
||||
/* #define PA_RXD(n) ((ushort)(0x01<<(2*n))) */
|
||||
/* #define PA_TXD(n) ((ushort)(0x02<<(2*n))) */
|
||||
|
||||
#define PA_RXD1 ((ushort)0x0001)
|
||||
#define PA_TXD1 ((ushort)0x0002)
|
||||
#define PA_RXD2 ((ushort)0x0004)
|
||||
#define PA_TXD2 ((ushort)0x0008)
|
||||
#define PA_RXD3 ((ushort)0x0010)
|
||||
#define PA_TXD3 ((ushort)0x0020)
|
||||
#define PA_RXD4 ((ushort)0x0040)
|
||||
#define PA_TXD4 ((ushort)0x0080)
|
||||
|
||||
#define PA_CLK1 ((ushort)0x0100)
|
||||
#define PA_CLK2 ((ushort)0x0200)
|
||||
#define PA_CLK3 ((ushort)0x0400)
|
||||
#define PA_CLK4 ((ushort)0x0800)
|
||||
#define PA_CLK5 ((ushort)0x1000)
|
||||
#define PA_CLK6 ((ushort)0x2000)
|
||||
#define PA_CLK7 ((ushort)0x4000)
|
||||
#define PA_CLK8 ((ushort)0x8000)
|
||||
|
||||
|
||||
/* Port B - See 360UM p. 7-362
|
||||
*/
|
||||
|
||||
|
||||
/* Port C - See 360UM p. 7-365
|
||||
*/
|
||||
|
||||
#define PC_RTS1 ((ushort)0x0001)
|
||||
#define PC_RTS2 ((ushort)0x0002)
|
||||
#define PC__RTS3 ((ushort)0x0004) /* !RTS3 */
|
||||
#define PC__RTS4 ((ushort)0x0008) /* !RTS4 */
|
||||
|
||||
#define PC_CTS1 ((ushort)0x0010)
|
||||
#define PC_CD1 ((ushort)0x0020)
|
||||
#define PC_CTS2 ((ushort)0x0040)
|
||||
#define PC_CD2 ((ushort)0x0080)
|
||||
#define PC_CTS3 ((ushort)0x0100)
|
||||
#define PC_CD3 ((ushort)0x0200)
|
||||
#define PC_CTS4 ((ushort)0x0400)
|
||||
#define PC_CD4 ((ushort)0x0800)
|
||||
|
||||
|
||||
|
||||
/*****************************************************************
|
||||
chip select option register
|
||||
*****************************************************************/
|
||||
#define DTACK 0xe000
|
||||
#define ADR_MASK 0x1ffc
|
||||
#define RDWR_MASK 0x0002
|
||||
#define FC_MASK 0x0001
|
||||
|
||||
/*****************************************************************
|
||||
tbase and rbase registers
|
||||
*****************************************************************/
|
||||
#define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \
|
||||
(quicc->ch_or_u.u.udata_bd_ucode + pram->tbase))
|
||||
#define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \
|
||||
(quicc->ch_or_u.u.udata_bd_ucode + pram->rbase))
|
||||
#define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
|
||||
(quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr))
|
||||
#define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
|
||||
(quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr))
|
||||
#define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \
|
||||
((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
|
||||
#define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \
|
||||
((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
|
||||
#define INCREASE_TBD(bd,quicc,pram) { \
|
||||
if((bd)->status & T_W) \
|
||||
(bd) = TBD_ADDR(quicc,pram); \
|
||||
else \
|
||||
(bd)++; \
|
||||
}
|
||||
#define DECREASE_TBD(bd,quicc,pram) { \
|
||||
if ((bd) == TBD_ADDR(quicc, pram)) \
|
||||
while (!((bd)->status & T_W)) \
|
||||
(bd)++; \
|
||||
else \
|
||||
(bd)--; \
|
||||
}
|
||||
#define INCREASE_RBD(bd,quicc,pram) { \
|
||||
if((bd)->status & R_W) \
|
||||
(bd) = RBD_ADDR(quicc,pram); \
|
||||
else \
|
||||
(bd)++; \
|
||||
}
|
||||
#define DECREASE_RBD(bd,quicc,pram) { \
|
||||
if ((bd) == RBD_ADDR(quicc, pram)) \
|
||||
while (!((bd)->status & T_W)) \
|
||||
(bd)++; \
|
||||
else \
|
||||
(bd)--; \
|
||||
}
|
||||
|
||||
/*****************************************************************
|
||||
Macros for Multi channel
|
||||
*****************************************************************/
|
||||
#define QMC_BASE(quicc,page) (struct global_multi_pram *)(&quicc->pram[page])
|
||||
#define MCBASE(quicc,page) (unsigned long)(quicc->pram[page].m.mcbase)
|
||||
#define CHANNEL_PRAM_BASE(quicc,channel) ((struct quicc32_pram *) \
|
||||
(&(quicc->ch_or_u.ch_pram_tbl[channel])))
|
||||
#define TBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
|
||||
(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase)))
|
||||
#define RBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
|
||||
(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase)))
|
||||
#define TBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
|
||||
(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr)))
|
||||
#define RBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
|
||||
(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr)))
|
||||
#define TBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
|
||||
CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \
|
||||
((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
|
||||
#define RBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
|
||||
CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \
|
||||
((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
|
||||
|
||||
#define INCREASE_TBD_32(bd,quicc,page,channel) { \
|
||||
if((bd)->status & T_W) \
|
||||
(bd) = TBD_32_ADDR(quicc,page,channel); \
|
||||
else \
|
||||
(bd)++; \
|
||||
}
|
||||
#define DECREASE_TBD_32(bd,quicc,page,channel) { \
|
||||
if ((bd) == TBD_32_ADDR(quicc, page,channel)) \
|
||||
while (!((bd)->status & T_W)) \
|
||||
(bd)++; \
|
||||
else \
|
||||
(bd)--; \
|
||||
}
|
||||
#define INCREASE_RBD_32(bd,quicc,page,channel) { \
|
||||
if((bd)->status & R_W) \
|
||||
(bd) = RBD_32_ADDR(quicc,page,channel); \
|
||||
else \
|
||||
(bd)++; \
|
||||
}
|
||||
#define DECREASE_RBD_32(bd,quicc,page,channel) { \
|
||||
if ((bd) == RBD_32_ADDR(quicc, page,channel)) \
|
||||
while (!((bd)->status & T_W)) \
|
||||
(bd)++; \
|
||||
else \
|
||||
(bd)--; \
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user