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MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shifts

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Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use
BIT/GENMASK for register fields, order & drop shifts" did for
asm/mips-cm.h.

We use BIT() & GENMASK() to simplify the definition of register fields,
drop the _SHF definitions since that information can be found in the
_MSK ones, and then drop the _MSK suffix.

Fields definitions are moved to be next to the appropriate register
definition, making it easier to link the two & keep everything ordered
by register address. Comments are added including the name of each
register & a brief description of its purpose which helps to understand
what registers are for, link them back to hardware documentation or grep
for them.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17003/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
2017-08-12 19:49:29 -07:00
committed by Ralf Baechle
parent 2c981e325f
commit 829ca2be9c
4 changed files with 49 additions and 42 deletions
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2
arch/mips/kernel/mips-cpc.c
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@@ -89,7 +89,7 @@ void mips_cpc_lock_other(unsigned int core)
curr_core = current_cpu_data.core;
spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
/*
* Ensure the core-other region reflects the appropriate core &