powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro
Currently all the low-power idle states are expected to wake up at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ that puts the CPU to an idle state and never returns. On ISA v3.0, when the ESL and EC bits in the PSSCR are zero, the CPU is expected to wake up at the next instruction of the idle instruction. This patch adds a new macro named IDLE_STATE_ENTER_SEQ_NORET for the no-return variant and reuses the name IDLE_STATE_ENTER_SEQ for a variant that allows resuming operation at the instruction next to the idle-instruction. Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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committed by
Michael Ellerman

parent
616badd2fb
commit
823b7bd515
@@ -205,7 +205,7 @@ pnv_enter_arch207_idle_mode:
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stb r3,PACA_THREAD_IDLE_STATE(r13)
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cmpwi cr3,r3,PNV_THREAD_SLEEP
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bge cr3,2f
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IDLE_STATE_ENTER_SEQ(PPC_NAP)
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IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
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/* No return */
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2:
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/* Sleep or winkle */
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@@ -239,7 +239,7 @@ pnv_fastsleep_workaround_at_entry:
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common_enter: /* common code for all the threads entering sleep or winkle */
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bgt cr3,enter_winkle
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IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
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IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
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fastsleep_workaround_at_entry:
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ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
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@@ -261,7 +261,7 @@ fastsleep_workaround_at_entry:
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enter_winkle:
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bl save_sprs_to_stack
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IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
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IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
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/*
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* r3 - requested stop state
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@@ -280,7 +280,7 @@ power_enter_stop:
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ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
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cmpd r3,r4
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bge 2f
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IDLE_STATE_ENTER_SEQ(PPC_STOP)
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IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
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2:
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/*
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* Entering deep idle state.
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@@ -302,7 +302,7 @@ lwarx_loop_stop:
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bl save_sprs_to_stack
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IDLE_STATE_ENTER_SEQ(PPC_STOP)
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IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
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_GLOBAL(power7_idle)
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/* Now check if user or arch enabled NAP mode */
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