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Merge tag 'mips_5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Просмотр исходного кода 
Pull MIPS updates from Thomas Bogendoerfer:

 - added support for MIPSr5 and P5600 cores

 - converted Loongson PCI driver into a PCI host driver using the
   generic PCI framework

 - added emulation of CPUCFG command for Loogonson64 cpus

 - removed of LASAT, PMC MSP71xx and NEC MARKEINS/EMMA

 - ioremap cleanup

 - fix for a race between two threads faulting the same page

 - various cleanups and fixes

* tag 'mips_5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (143 commits)
  MIPS: ralink: drop ralink_clk_init for mt7621
  MIPS: ralink: bootrom: mark a function as __init to save some memory
  MIPS: Loongson64: Reorder CPUCFG model match arms
  MIPS: Expose Loongson CPUCFG availability via HWCAP
  MIPS: Loongson64: Guard against future cores without CPUCFG
  MIPS: Fix build warning about "PTR_STR" redefinition
  MIPS: Loongson64: Remove not used pci.c
  MIPS: Loongson64: Define PCI_IOBASE
  MIPS: CPU_LOONGSON2EF need software to maintain cache consistency
  MIPS: DTS: Fix build errors used with various configs
  MIPS: Loongson64: select NO_EXCEPT_FILL
  MIPS: Fix IRQ tracing when call handle_fpe() and handle_msa_fpe()
  MIPS: mm: add page valid judgement in function pte_modify
  mm/memory.c: Add memory read privilege on page fault handling
  mm/memory.c: Update local TLB if PTE entry exists
  MIPS: Do not flush tlb page when updating PTE entry
  MIPS: ingenic: Default to a generic board
  MIPS: ingenic: Add support for GCW Zero prototype
  MIPS: ingenic: DTS: Add memory info of GCW Zero
  MIPS: Loongson64: Switch to generic PCI driver
  ...
Этот коммит содержится в:
Linus Torvalds
2020-06-03 13:32:21 -07:00
родитель e8f4abf8fd 9bd0bd2645
Коммит 8226f11318
333 изменённых файлов: 4676 добавлений и 13059 удалений
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2
arch/mips/include/asm/asm-eva.h
Просмотреть файл

@@ -180,7 +180,7 @@
#define user_ld(reg, addr) kernel_lw(reg, addr)
#else
#define user_sd(reg, addr) kernel_sd(reg, addr)
#define user_ld(reg, addr) kernel_sd(reg, addr)
#define user_ld(reg, addr) kernel_ld(reg, addr)
#endif /* CONFIG_32BIT */
#endif /* CONFIG_EVA */

24
arch/mips/include/asm/asm.h
Просмотреть файл

@@ -74,10 +74,15 @@ symbol: .insn
.globl symbol; \
symbol = value
#define PANIC(msg) \
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
#define ASM_PANIC(msg) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
PTR_LA a0, 8f; \
jal panic; \
9: b 9b; \
.set pop; \
@@ -87,22 +92,17 @@ symbol = value
* Print formatted string
*/
#ifdef CONFIG_PRINTK
#define PRINT(string) \
#define ASM_PRINT(string) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
PTR_LA a0, 8f; \
jal printk; \
.set pop; \
TEXT(string)
#else
#define PRINT(string)
#define ASM_PRINT(string)
#endif
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
/*
* Stack alignment
*/
@@ -202,7 +202,9 @@ symbol = value
#define LONG_SRA sra
#define LONG_SRAV srav
#ifdef __ASSEMBLY__
#define LONG .word
#endif
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
@@ -225,7 +227,9 @@ symbol = value
#define LONG_SRA dsra
#define LONG_SRAV dsrav
#ifdef __ASSEMBLY__
#define LONG .dword
#endif
#define LONGSIZE 8
#define LONGMASK 7
#define LONGLOG 3

18
arch/mips/include/asm/asmmacro.h
Просмотреть файл

@@ -44,7 +44,8 @@
.endm
#endif
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)
.macro local_irq_enable reg=t0
ei
irq_enable_hazard
@@ -54,7 +55,7 @@
di
irq_disable_hazard
.endm
#else
#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
.macro local_irq_enable reg=t0
mfc0 \reg, CP0_STATUS
ori \reg, \reg, 1
@@ -79,7 +80,7 @@
sw \reg, TI_PRE_COUNT($28)
#endif
.endm
#endif /* CONFIG_CPU_MIPSR2 */
#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
.macro fpu_save_16even thread tmp=t0
.set push
@@ -131,7 +132,7 @@
.macro fpu_save_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
defined(CONFIG_CPU_MIPSR6)
defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
sll \tmp, \status, 5
bgez \tmp, 10f
fpu_save_16odd \thread
@@ -190,7 +191,7 @@
.macro fpu_restore_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
defined(CONFIG_CPU_MIPSR6)
defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
sll \tmp, \status, 5
bgez \tmp, 10f # 16 register mode?
@@ -200,16 +201,17 @@
fpu_restore_16even \thread \tmp
.endm
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)
.macro _EXT rd, rs, p, s
ext \rd, \rs, \p, \s
.endm
#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
.macro _EXT rd, rs, p, s
srl \rd, \rs, \p
andi \rd, \rd, (1 << \s) - 1
.endm
#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
/*
* Temporary until all gas have MT ASE support

13
arch/mips/include/asm/bootinfo.h
Просмотреть файл

@@ -41,17 +41,6 @@
#define MACH_DS5800 9 /* DECsystem 5800 */
#define MACH_DS5900 10 /* DECsystem 5900 */
/*
* Valid machtype for group PMC-MSP
*/
#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */
#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */
#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */
#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */
#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
/*
* Valid machtype for group Mikrotik
*/
@@ -121,7 +110,7 @@ extern unsigned long fw_passed_dtb;
#endif
/*
* Platform memory detection hook called by setup_arch
* Platform memory detection hook called by arch_mem_init()
*/
extern void plat_mem_setup(void);

3
arch/mips/include/asm/branch.h
Просмотреть файл

@@ -27,6 +27,9 @@ extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
#define MM_POOL32A_MINOR_SHIFT 0x6
#define MM_MIPS32_COND_FC 0x30
int isBranchInstr(struct pt_regs *regs,
struct mm_decoded_insn dec_insn, unsigned long *contpc);
extern int __mm_isBranchInstr(struct pt_regs *regs,
struct mm_decoded_insn dec_insn, unsigned long *contpc);

2
arch/mips/include/asm/cacheops.h
Просмотреть файл

@@ -48,7 +48,7 @@
* R4000-specific cacheops
*/
#define Create_Dirty_Excl_D (Cache_D | 0x0c)
#define Fill (Cache_I | 0x14)
#define Fill_I (Cache_I | 0x14)
#define Hit_Writeback_I (Cache_I | Hit_Writeback)
#define Hit_Writeback_D (Cache_D | Hit_Writeback)

49
arch/mips/include/asm/clock.h
Просмотреть файл

@@ -1,49 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_MIPS_CLOCK_H
#define __ASM_MIPS_CLOCK_H
#include <linux/kref.h>
#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/clk.h>
struct clk;
struct clk_ops {
void (*init) (struct clk *clk);
void (*enable) (struct clk *clk);
void (*disable) (struct clk *clk);
void (*recalc) (struct clk *clk);
int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
long (*round_rate) (struct clk *clk, unsigned long rate);
};
struct clk {
struct list_head node;
const char *name;
int id;
struct module *owner;
struct clk *parent;
struct clk_ops *ops;
struct kref kref;
unsigned long rate;
unsigned long flags;
};
#define CLK_ALWAYS_ENABLED (1 << 0)
#define CLK_RATE_PROPAGATES (1 << 1)
int clk_init(void);
int __clk_enable(struct clk *);
void __clk_disable(struct clk *);
void clk_recalc_rate(struct clk *);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
#endif /* __ASM_MIPS_CLOCK_H */

5
arch/mips/include/asm/compiler.h
Просмотреть файл

@@ -57,6 +57,11 @@
#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
#define MIPS_ISA_LEVEL_RAW mips64r6
#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
#elif defined(CONFIG_CPU_MIPSR5)
#define MIPS_ISA_LEVEL "mips64r5"
#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
#define MIPS_ISA_LEVEL_RAW mips64r5
#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
#else
/* MIPS64 is a superset of MIPS32 */
#define MIPS_ISA_LEVEL "mips64r2"

47
arch/mips/include/asm/cpu-features.h
Просмотреть файл

@@ -284,14 +284,23 @@
#ifndef cpu_has_mips32r2
# define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
#endif
#ifndef cpu_has_mips32r5
# define cpu_has_mips32r5 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
#endif
#ifndef cpu_has_mips32r6
# define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
#endif
#ifndef cpu_has_mips64r1
# define cpu_has_mips64r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)
# define cpu_has_mips64r1 (cpu_has_64bits && \
__isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
#endif
#ifndef cpu_has_mips64r2
# define cpu_has_mips64r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)
# define cpu_has_mips64r2 (cpu_has_64bits && \
__isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
#endif
#ifndef cpu_has_mips64r5
# define cpu_has_mips64r5 (cpu_has_64bits && \
__isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
#endif
#ifndef cpu_has_mips64r6
# define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
@@ -313,19 +322,25 @@
(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
#define cpu_has_mips_4_5_64_r2_r6 \
(cpu_has_mips_4_5 | cpu_has_mips64r1 | \
cpu_has_mips_r2 | cpu_has_mips_r6)
cpu_has_mips_r2 | cpu_has_mips_r5 | \
cpu_has_mips_r6)
#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips32r5 | cpu_has_mips32r6)
#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | \
cpu_has_mips64r5 | cpu_has_mips64r6)
#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
#define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5)
#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips32r6 | cpu_has_mips64r1 | \
cpu_has_mips64r2 | cpu_has_mips64r6)
cpu_has_mips32r5 | cpu_has_mips32r6 | \
cpu_has_mips64r1 | cpu_has_mips64r2 | \
cpu_has_mips64r5 | cpu_has_mips64r6)
/* MIPSR2 and MIPSR6 have a lot of similarities */
#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
/* MIPSR2 - MIPSR6 have a lot of similarities */
#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r5 | \
cpu_has_mips_r6)
/*
* cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
@@ -435,9 +450,6 @@
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 0
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses 0
# endif
# ifndef cpu_vmbits
# define cpu_vmbits 31
# endif
@@ -456,9 +468,6 @@
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 1
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses 1
# endif
# ifndef cpu_vmbits
# define cpu_vmbits cpu_data[0].vmbits
# define __NEED_VMBITS_PROBE
@@ -620,6 +629,14 @@
# endif
#endif
#ifndef cpu_has_mm_sysad
# define cpu_has_mm_sysad __opt(MIPS_CPU_MM_SYSAD)
#endif
#ifndef cpu_has_mm_full
# define cpu_has_mm_full __opt(MIPS_CPU_MM_FULL)
#endif
/*
* Guest capabilities
*/

11
arch/mips/include/asm/cpu-info.h
Просмотреть файл

@@ -105,6 +105,15 @@ struct cpuinfo_mips {
unsigned int gtoffset_mask;
unsigned int guestid_mask;
unsigned int guestid_cache;
#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
/* CPUCFG data for this CPU, synthesized at probe time.
*
* CPUCFG select 0 is PRId, 4 and above are unimplemented for now.
* So the only stored values are for CPUCFG selects 1-3 inclusive.
*/
u32 loongson3_cpucfg_data[3];
#endif
} __attribute__((aligned(SMP_CACHE_BYTES)));
extern struct cpuinfo_mips cpu_data[];
@@ -142,7 +151,7 @@ struct proc_cpuinfo_notifier_args {
static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
{
/* Optimisation for systems where multiple clusters aren't used */
if (!IS_ENABLED(CONFIG_CPU_MIPSR6))
if (!IS_ENABLED(CONFIG_CPU_MIPSR5) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
return 0;
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>

7
arch/mips/include/asm/cpu-type.h
Просмотреть файл

@@ -51,13 +51,18 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_M14KEC:
case CPU_INTERAPTIV:
case CPU_PROAPTIV:
case CPU_P5600:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R5
case CPU_M5150:
case CPU_P5600:
#endif
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \
defined(CONFIG_SYS_HAS_CPU_MIPS32_R5) || \
defined(CONFIG_SYS_HAS_CPU_MIPS32_R6) || \
defined(CONFIG_SYS_HAS_CPU_MIPS64_R2) || \
defined(CONFIG_SYS_HAS_CPU_MIPS64_R5) || \
defined(CONFIG_SYS_HAS_CPU_MIPS64_R6)
case CPU_QEMU_GENERIC:
#endif

18
arch/mips/include/asm/cpu.h
Просмотреть файл

@@ -250,6 +250,10 @@
#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
#define PRID_REV_LOONGSON2K_R1_0 0x0000
#define PRID_REV_LOONGSON2K_R1_1 0x0001
#define PRID_REV_LOONGSON2K_R1_2 0x0002
#define PRID_REV_LOONGSON2K_R1_3 0x0003
#define PRID_REV_LOONGSON3A_R1 0x0005
#define PRID_REV_LOONGSON3B_R1 0x0006
#define PRID_REV_LOONGSON3B_R2 0x0007
@@ -343,14 +347,16 @@ enum cpu_type_enum {
#define MIPS_CPU_ISA_M32R2 0x00000020
#define MIPS_CPU_ISA_M64R1 0x00000040
#define MIPS_CPU_ISA_M64R2 0x00000080
#define MIPS_CPU_ISA_M32R6 0x00000100
#define MIPS_CPU_ISA_M64R6 0x00000200
#define MIPS_CPU_ISA_M32R5 0x00000100
#define MIPS_CPU_ISA_M64R5 0x00000200
#define MIPS_CPU_ISA_M32R6 0x00000400
#define MIPS_CPU_ISA_M64R6 0x00000800
#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M32R6)
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
MIPS_CPU_ISA_M64R6)
MIPS_CPU_ISA_M64R5 | MIPS_CPU_ISA_M64R6)
/*
* CPU Option encodings
@@ -416,7 +422,9 @@ enum cpu_type_enum {
#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(58) /* CPU Only support MAC2008 Fused multiply-add instruction */
#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
/*
* CPU ASE encodings

248
arch/mips/include/asm/emma/emma2rh.h
Просмотреть файл

@@ -1,248 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
*/
#ifndef __ASM_EMMA_EMMA2RH_H
#define __ASM_EMMA_EMMA2RH_H
#include <irq.h>
/*
* EMMA2RH registers
*/
#define REGBASE 0x10000000
#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE)
#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)
#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE)
#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE)
#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE)
#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE)
#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE)
#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE)
#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE)
#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE)
#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE)
#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE)
#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE)
#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE)
#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE)
#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE)
#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE)
#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE)
#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE)
#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE)
#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE)
#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE)
#define EMMA2RH_PCI_INT (0x200020+REGBASE)
#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE)
#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE)
#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE)
#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE)
#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE)
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
/* the actual ram size is detected at run-time */
#define EMMA2RH_RAM_BASE 0x00000000
#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */
#define EMMA2RH_IO_BASE 0x10000000
#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */
#define EMMA2RH_GENERALIO_BASE 0x11000000
#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */
#define EMMA2RH_PCI_IO_BASE 0x12000000
#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define EMMA2RH_PCI_MEM_BASE 0x14000000
#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define EMMA2RH_ROM_BASE 0x1c000000
#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */
#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
#define NUM_EMMA2RH_IRQ 96
#define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/*
* emma2rh irq defs
*/
#define EMMA2RH_IRQ_INT(n) (EMMA2RH_IRQ_BASE + (n))
#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT(49)
#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT(50)
#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT(51)
#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT(56)
#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT(57)
#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT(58)
/*
* EMMA2RH Register Access
*/
#define EMMA2RH_BASE (0xa0000000)
static inline void emma2rh_sync(void)
{
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
}
static inline void emma2rh_out32(u32 offset, u32 val)
{
*(volatile u32 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u32 emma2rh_in32(u32 offset)
{
u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
return val;
}
static inline void emma2rh_out16(u32 offset, u16 val)
{
*(volatile u16 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u16 emma2rh_in16(u32 offset)
{
u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
return val;
}
static inline void emma2rh_out8(u32 offset, u8 val)
{
*(volatile u8 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u8 emma2rh_in8(u32 offset)
{
u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
return val;
}
/**
* IIC registers map
**/
/*---------------------------------------------------------------------------*/
/* CNT - Control register (00H R/W) */
/*---------------------------------------------------------------------------*/
#define SPT 0x00000001
#define STT 0x00000002
#define ACKE 0x00000004
#define WTIM 0x00000008
#define SPIE 0x00000010
#define WREL 0x00000020
#define LREL 0x00000040
#define IICE 0x00000080
#define CNT_RESERVED 0x000000ff /* reserved bit 0 */
#define I2C_EMMA_START (IICE | STT)
#define I2C_EMMA_STOP (IICE | SPT)
#define I2C_EMMA_REPSTART I2C_EMMA_START
/*---------------------------------------------------------------------------*/
/* STA - Status register (10H Read) */
/*---------------------------------------------------------------------------*/
#define MSTS 0x00000080
#define ALD 0x00000040
#define EXC 0x00000020
#define COI 0x00000010
#define TRC 0x00000008
#define ACKD 0x00000004
#define STD 0x00000002
#define SPD 0x00000001
/*---------------------------------------------------------------------------*/
/* CSEL - Clock select register (20H R/W) */
/*---------------------------------------------------------------------------*/
#define FCL 0x00000080
#define ND50 0x00000040
#define CLD 0x00000020
#define DAD 0x00000010
#define SMC 0x00000008
#define DFC 0x00000004
#define CL 0x00000003
#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */
#define FAST397 0x0000008b
#define FAST297 0x0000008a
#define FAST347 0x0000000b
#define FAST260 0x0000000a
#define FAST130 0x00000008
#define STANDARD108 0x00000083
#define STANDARD83 0x00000082
#define STANDARD95 0x00000003
#define STANDARD73 0x00000002
#define STANDARD36 0x00000001
#define STANDARD71 0x00000000
/*---------------------------------------------------------------------------*/
/* SVA - Slave address register (30H R/W) */
/*---------------------------------------------------------------------------*/
#define SVA 0x000000fe
/*---------------------------------------------------------------------------*/
/* SHR - Shift register (40H R/W) */
/*---------------------------------------------------------------------------*/
#define SR 0x000000ff
/*---------------------------------------------------------------------------*/
/* INT - Interrupt register (50H R/W) */
/* INTM - Interrupt mask register (60H R/W) */
/*---------------------------------------------------------------------------*/
#define INTE0 0x00000001
/***********************************************************************
* I2C registers
***********************************************************************
*/
#define I2C_EMMA_CNT 0x00
#define I2C_EMMA_STA 0x10
#define I2C_EMMA_CSEL 0x20
#define I2C_EMMA_SVA 0x30
#define I2C_EMMA_SHR 0x40
#define I2C_EMMA_INT 0x50
#define I2C_EMMA_INTM 0x60
/*
* include the board dependent part
*/
#ifdef CONFIG_NEC_MARKEINS
#include <asm/emma/markeins.h>
#else
#error "Unknown EMMA2RH board!"
#endif
#endif /* __ASM_EMMA_EMMA2RH_H */

28
arch/mips/include/asm/emma/markeins.h
Просмотреть файл

@@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
*/
#ifndef MARKEINS_H
#define MARKEINS_H
#define NUM_EMMA2RH_IRQ_SW 32
#define NUM_EMMA2RH_IRQ_GPIO 32
#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT(7) - EMMA2RH_IRQ_INT(0))
#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT(46) - EMMA2RH_IRQ_INT(0))
#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
#define EMMA2RH_SW_IRQ_INT(n) (EMMA2RH_SW_IRQ_BASE + (n))
#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15
#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16
#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17
#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18
#endif /* CONFIG_MARKEINS */

6
arch/mips/include/asm/fpu.h
Просмотреть файл

@@ -71,12 +71,12 @@ static inline int __enable_fpu(enum fpu_mode mode)
goto fr_common;
case FPU_64BIT:
#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
|| defined(CONFIG_64BIT))
#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_64BIT))
/* we only have a 32-bit FPU */
return SIGFPE;
#endif
/* fall through */
fallthrough;
case FPU_32BIT:
if (cpu_has_fre) {
/* clear FRE */

4
arch/mips/include/asm/fpu_emulator.h
Просмотреть файл

@@ -172,10 +172,6 @@ void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
struct task_struct *tsk);
int process_fpemu_return(int sig, void __user *fault_addr,
unsigned long fcr31);
int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
unsigned long *contpc);
int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
unsigned long *contpc);
/*
* Mask the FCSR Cause bits according to the Enable bits, observing

8
arch/mips/include/asm/hazards.h
Просмотреть файл

@@ -22,8 +22,9 @@
/*
* TLB hazards
*/
#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \
!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)) && \
!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
/*
* MIPSR2 defines ehb for hazard avoidance
@@ -278,7 +279,8 @@ do { \
#define __disable_fpu_hazard
#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)
#define __enable_fpu_hazard \
___ehb

87
arch/mips/include/asm/io.h
Просмотреть файл

@@ -30,8 +30,6 @@
#include <asm/pgtable-bits.h>
#include <asm/processor.h>
#include <asm/string.h>
#include <ioremap.h>
#include <mangle-port.h>
/*
@@ -153,66 +151,9 @@ static inline void *isa_bus_to_virt(unsigned long address)
*/
#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
extern void __iounmap(const volatile void __iomem *addr);
static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
void __iomem *addr = plat_ioremap(offset, size, flags);
if (addr)
return addr;
#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
if (cpu_has_64bit_addresses) {
u64 base = UNCAC_BASE;
/*
* R10000 supports a 2 bit uncached attribute therefore
* UNCAC_BASE may not equal IO_BASE.
*/
if (flags == _CACHE_UNCACHED)
base = (u64) IO_BASE;
return (void __iomem *) (unsigned long) (base + offset);
} else if (__builtin_constant_p(offset) &&
__builtin_constant_p(size) && __builtin_constant_p(flags)) {
phys_addr_t phys_addr, last_addr;
phys_addr = fixup_bigphys_addr(offset, size);
/* Don't allow wraparound or zero size. */
last_addr = phys_addr + size - 1;
if (!size || last_addr < phys_addr)
return NULL;
/*
* Map uncached objects in the low 512MB of address
* space using KSEG1.
*/
if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
flags == _CACHE_UNCACHED)
return (void __iomem *)
(unsigned long)CKSEG1ADDR(phys_addr);
}
return __ioremap(offset, size, flags);
#undef __IS_LOW512
}
/*
* ioremap_prot - map bus memory into CPU space
* @offset: bus address of the memory
* @size: size of the resource to map
* ioremap_prot gives the caller control over cache coherency attributes (CCA)
*/
static inline void __iomem *ioremap_prot(phys_addr_t offset,
unsigned long size, unsigned long prot_val) {
return __ioremap_mode(offset, size, prot_val & _CACHE_MASK);
}
void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
unsigned long prot_val);
void iounmap(const volatile void __iomem *addr);
/*
* ioremap - map bus memory into CPU space
@@ -226,7 +167,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset,
* address.
*/
#define ioremap(offset, size) \
__ioremap_mode((offset), (size), _CACHE_UNCACHED)
ioremap_prot((offset), (size), _CACHE_UNCACHED)
#define ioremap_uc ioremap
/*
@@ -245,7 +186,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset,
* memory-like regions on I/O busses.
*/
#define ioremap_cache(offset, size) \
__ioremap_mode((offset), (size), _page_cachable_default)
ioremap_prot((offset), (size), _page_cachable_default)
/*
* ioremap_wc - map bus memory into CPU space
@@ -266,23 +207,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset,
* _CACHE_UNCACHED option (see cpu_probe() method).
*/
#define ioremap_wc(offset, size) \
__ioremap_mode((offset), (size), boot_cpu_data.writecombine)
static inline void iounmap(const volatile void __iomem *addr)
{
if (plat_iounmap(addr))
return;
#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
if (cpu_has_64bit_addresses ||
(__builtin_constant_p(addr) && __IS_KSEG1(addr)))
return;
__iounmap(addr);
#undef __IS_KSEG1
}
ioremap_prot((offset), (size), boot_cpu_data.writecombine)
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
#define war_io_reorder_wmb() wmb()

19
arch/mips/include/asm/lasat/ds1603.h
Просмотреть файл

@@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/addrspace.h>
/* Lasat 100 */
#define DS1603_REG_100 (KSEG1ADDR(0x1c810000))
#define DS1603_RST_100 (1 << 2)
#define DS1603_CLK_100 (1 << 0)
#define DS1603_DATA_SHIFT_100 1
#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100)
/* Lasat 200 */
#define DS1603_REG_200 (KSEG1ADDR(0x11000000))
#define DS1603_RST_200 (1 << 3)
#define DS1603_CLK_200 (1 << 4)
#define DS1603_DATA_200 (1 << 5)
#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000)
#define DS1603_DATA_READ_SHIFT_200 9
#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200)

18
arch/mips/include/asm/lasat/eeprom.h
Просмотреть файл

@@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/addrspace.h>
/* lasat 100 */
#define AT93C_REG_100 KSEG1ADDR(0x1c810000)
#define AT93C_RDATA_REG_100 AT93C_REG_100
#define AT93C_RDATA_SHIFT_100 4
#define AT93C_WDATA_SHIFT_100 4
#define AT93C_CS_M_100 (1 << 5)
#define AT93C_CLK_M_100 (1 << 3)
/* lasat 200 */
#define AT93C_REG_200 KSEG1ADDR(0x11000000)
#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000)
#define AT93C_RDATA_SHIFT_200 8
#define AT93C_WDATA_SHIFT_200 2
#define AT93C_CS_M_200 (1 << 0)
#define AT93C_CLK_M_200 (1 << 1)

23
arch/mips/include/asm/lasat/head.h
Просмотреть файл

@@ -1,23 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Image header stuff
*/
#ifndef _HEAD_H
#define _HEAD_H
#define LASAT_K_MAGIC0_VAL 0xfedeabba
#define LASAT_K_MAGIC1_VAL 0x00bedead
#ifndef _LANGUAGE_ASSEMBLY
#include <linux/types.h>
struct bootloader_header {
u32 magic[2];
u32 version;
u32 image_start;
u32 image_size;
u32 kernel_start;
u32 kernel_entry;
};
#endif
#endif /* _HEAD_H */

245
arch/mips/include/asm/lasat/lasat.h
Просмотреть файл

@@ -1,245 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* lasat.h
*
* Thomas Horsten <thh@lasat.com>
* Copyright (C) 2000 LASAT Networks A/S.
*
* Configuration for LASAT boards, loads the appropriate include files.
*/
#ifndef _LASAT_H
#define _LASAT_H
#ifndef _LANGUAGE_ASSEMBLY
extern struct lasat_misc {
volatile u32 *reset_reg;
volatile u32 *flash_wp_reg;
u32 flash_wp_bit;
} *lasat_misc;
enum lasat_mtdparts {
LASAT_MTD_BOOTLOADER,
LASAT_MTD_SERVICE,
LASAT_MTD_NORMAL,
LASAT_MTD_CONFIG,
LASAT_MTD_FS,
LASAT_MTD_LAST
};
/*
* The format of the data record in the EEPROM.
* See the LASAT Hardware Configuration field specification for a detailed
* description of the config field.
*/
#include <linux/types.h>
#define LASAT_EEPROM_VERSION 7
struct lasat_eeprom_struct {
unsigned int version;
unsigned int cfg[3];
unsigned char hwaddr[6];
unsigned char print_partno[12];
unsigned char term0;
unsigned char print_serial[14];
unsigned char term1;
unsigned char prod_partno[12];
unsigned char term2;
unsigned char prod_serial[14];
unsigned char term3;
unsigned char passwd_hash[16];
unsigned char pwdnull;
unsigned char vendid;
unsigned char ts_ref;
unsigned char ts_signoff;
unsigned char reserved[11];
unsigned char debugaccess;
unsigned short prid;
unsigned int serviceflag;
unsigned int ipaddr;
unsigned int netmask;
unsigned int crc32;
};
struct lasat_eeprom_struct_pre7 {
unsigned int version;
unsigned int flags[3];
unsigned char hwaddr0[6];
unsigned char hwaddr1[6];
unsigned char print_partno[9];
unsigned char term0;
unsigned char print_serial[14];
unsigned char term1;
unsigned char prod_partno[9];
unsigned char term2;
unsigned char prod_serial[14];
unsigned char term3;
unsigned char passwd_hash[24];
unsigned char pwdnull;
unsigned char vendor;
unsigned char ts_ref;
unsigned char ts_signoff;
unsigned char reserved[6];
unsigned int writecount;
unsigned int ipaddr;
unsigned int netmask;
unsigned int crc32;
};
/* Configuration descriptor encoding - see the doc for details */
#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf)
#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf)
#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf)
#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf)
#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf)
#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf)
#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf)
#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf)
#define LASAT_W1_EDHAC(v) (((v)) & 0xf)
#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1)
#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1)
#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1)
#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1)
#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1)
#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1)
#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1)
#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf)
#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf)
#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf)
#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf)
#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf)
/* Routines specific to LASAT boards */
#define LASAT_BMID_MASQUERADE2 0
#define LASAT_BMID_MASQUERADEPRO 1
#define LASAT_BMID_SAFEPIPE25 2
#define LASAT_BMID_SAFEPIPE50 3
#define LASAT_BMID_SAFEPIPE100 4
#define LASAT_BMID_SAFEPIPE5000 5
#define LASAT_BMID_SAFEPIPE7000 6
#define LASAT_BMID_SAFEPIPE1000 7
#if 0
#define LASAT_BMID_SAFEPIPE30 7
#define LASAT_BMID_SAFEPIPE5100 8
#define LASAT_BMID_SAFEPIPE7100 9
#endif
#define LASAT_BMID_UNKNOWN 0xf
#define LASAT_MAX_BMID_NAMES 9 /* no larger than 15! */
#define LASAT_HAS_EDHAC (1 << 0)
#define LASAT_EDHAC_FAST (1 << 1)
#define LASAT_HAS_EADI (1 << 2)
#define LASAT_HAS_HIFN (1 << 3)
#define LASAT_HAS_ISDN (1 << 4)
#define LASAT_HAS_LEASEDLINE_IF (1 << 5)
#define LASAT_HAS_HDC (1 << 6)
#define LASAT_PRID_MASQUERADE2 0
#define LASAT_PRID_MASQUERADEPRO 1
#define LASAT_PRID_SAFEPIPE25 2
#define LASAT_PRID_SAFEPIPE50 3
#define LASAT_PRID_SAFEPIPE100 4
#define LASAT_PRID_SAFEPIPE5000 5
#define LASAT_PRID_SAFEPIPE7000 6
#define LASAT_PRID_SAFEPIPE30 7
#define LASAT_PRID_SAFEPIPE5100 8
#define LASAT_PRID_SAFEPIPE7100 9
#define LASAT_PRID_SAFEPIPE1110 10
#define LASAT_PRID_SAFEPIPE3020 11
#define LASAT_PRID_SAFEPIPE3030 12
#define LASAT_PRID_SAFEPIPE5020 13
#define LASAT_PRID_SAFEPIPE5030 14
#define LASAT_PRID_SAFEPIPE1120 15
#define LASAT_PRID_SAFEPIPE1130 16
#define LASAT_PRID_SAFEPIPE6010 17
#define LASAT_PRID_SAFEPIPE6110 18
#define LASAT_PRID_SAFEPIPE6210 19
#define LASAT_PRID_SAFEPIPE1020 20
#define LASAT_PRID_SAFEPIPE1040 21
#define LASAT_PRID_SAFEPIPE1060 22
struct lasat_info {
unsigned int li_cpu_hz;
unsigned int li_bus_hz;
unsigned int li_bmid;
unsigned int li_memsize;
unsigned int li_flash_size;
unsigned int li_prid;
unsigned char li_bmstr[16];
unsigned char li_namestr[32];
unsigned char li_typestr[16];
/* Info on the Flash layout */
unsigned int li_flash_base;
unsigned long li_flashpart_base[LASAT_MTD_LAST];
unsigned long li_flashpart_size[LASAT_MTD_LAST];
struct lasat_eeprom_struct li_eeprom_info;
unsigned int li_eeprom_upgrade_version;
unsigned int li_debugaccess;
};
extern struct lasat_info lasat_board_info;
static inline unsigned long lasat_flash_partition_start(int partno)
{
if (partno < 0 || partno >= LASAT_MTD_LAST)
return 0;
return lasat_board_info.li_flashpart_base[partno];
}
static inline unsigned long lasat_flash_partition_size(int partno)
{
if (partno < 0 || partno >= LASAT_MTD_LAST)
return 0;
return lasat_board_info.li_flashpart_size[partno];
}
/* Called from setup() to initialize the global board_info struct */
extern int lasat_init_board_info(void);
/* Write the modified EEPROM info struct */
extern void lasat_write_eeprom_info(void);
#define N_MACHTYPES 2
/* for calibration of delays */
/* the lasat_ndelay function is necessary because it is used at an
* early stage of the boot process where ndelay is not calibrated.
* It is used for the bit-banging rtc and eeprom drivers */
#include <linux/delay.h>
#include <linux/smp.h>
/* calculating with the slowest board with 100 MHz clock */
#define LASAT_100_DIVIDER 20
/* All 200's run at 250 MHz clock */
#define LASAT_200_DIVIDER 8
extern unsigned int lasat_ndelay_divider;
static inline void lasat_ndelay(unsigned int ns)
{
__delay(ns / lasat_ndelay_divider);
}
#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000)
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba
/* Lasat 100 boards */
#define LASAT_GT_BASE (KSEG1ADDR(0x14000000))
/* Lasat 200 boards */
#define Vrc5074_PHYS_BASE 0x1fa00000
#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE))
#define PCI_WINDOW1 0x1a000000
#endif /* _LASAT_H */

15
arch/mips/include/asm/lasat/lasatint.h
Просмотреть файл

@@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_LASAT_LASATINT_H
#define __ASM_LASAT_LASATINT_H
/* lasat 100 */
#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
#define LASATINT_MASK_SHIFT_100 0
/* lasat 200 */
#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c))
#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
#define LASATINT_MASK_SHIFT_200 16
#endif /* __ASM_LASAT_LASATINT_H */

16
arch/mips/include/asm/lasat/picvue.h
Просмотреть файл

@@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Lasat 100 */
#define PVC_REG_100 KSEG1ADDR(0x1c820000)
#define PVC_DATA_SHIFT_100 0
#define PVC_DATA_M_100 0xFF
#define PVC_E_100 (1 << 8)
#define PVC_RW_100 (1 << 9)
#define PVC_RS_100 (1 << 10)
/* Lasat 200 */
#define PVC_REG_200 KSEG1ADDR(0x11000000)
#define PVC_DATA_SHIFT_200 24
#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200)
#define PVC_E_200 (1 << 16)
#define PVC_RW_200 (1 << 17)
#define PVC_RS_200 (1 << 18)

14
arch/mips/include/asm/lasat/serial.h
Просмотреть файл

@@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/lasat/lasat.h>
/* Lasat 100 boards serial configuration */
#define LASAT_BASE_BAUD_100 (7372800 / 16)
#define LASAT_UART_REGS_BASE_100 0x1c8b0000
#define LASAT_UART_REGS_SHIFT_100 2
#define LASATINT_UART_100 16
/* * LASAT 200 boards serial configuration */
#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
#define LASAT_UART_REGS_SHIFT_200 3
#define LASATINT_UART_200 21

17
arch/mips/include/asm/maar.h
Просмотреть файл

@@ -32,7 +32,7 @@ unsigned platform_maar_init(unsigned num_pairs);
* @upper: The highest address that the MAAR pair will affect. Must be
* aligned to one byte before a 2^16 byte boundary.
* @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
* MIPS_MAAR_VL attribute will automatically be set.
* MIPS_MAAR_VL/MIPS_MAAR_VH attributes will automatically be set.
*
* Program the pair of MAAR registers specified by idx to apply the attributes
* specified by attrs to the range of addresses from lower to higher.
@@ -48,17 +48,30 @@ static inline void write_maar_pair(unsigned idx, phys_addr_t lower,
/* Automatically set MIPS_MAAR_VL */
attrs |= MIPS_MAAR_VL;
/* Write the upper address & attributes (only MIPS_MAAR_VL matters) */
/*
* Write the upper address & attributes (both MIPS_MAAR_VL and
* MIPS_MAAR_VH matter)
*/
write_c0_maari(idx << 1);
back_to_back_c0_hazard();
write_c0_maar(((upper >> 4) & MIPS_MAAR_ADDR) | attrs);
back_to_back_c0_hazard();
#ifdef CONFIG_XPA
upper >>= MIPS_MAARX_ADDR_SHIFT;
writex_c0_maar(((upper >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
back_to_back_c0_hazard();
#endif
/* Write the lower address & attributes */
write_c0_maari((idx << 1) | 0x1);
back_to_back_c0_hazard();
write_c0_maar((lower >> 4) | attrs);
back_to_back_c0_hazard();
#ifdef CONFIG_XPA
lower >>= MIPS_MAARX_ADDR_SHIFT;
writex_c0_maar(((lower >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
back_to_back_c0_hazard();
#endif
}
/**

1
arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
Просмотреть файл

@@ -56,6 +56,5 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */

1
arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
Просмотреть файл

@@ -45,7 +45,6 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32

38
arch/mips/include/asm/mach-au1x00/ioremap.h
Просмотреть файл

@@ -1,38 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/mach-au1x00/ioremap.h
*/
#ifndef __ASM_MACH_AU1X00_IOREMAP_H
#define __ASM_MACH_AU1X00_IOREMAP_H
#include <linux/types.h>
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t);
#else
static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
#endif
/*
* Allow physical addresses to be fixed up to help 36-bit peripherals.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return __fixup_bigphys_addr(phys_addr, size);
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
return NULL;
}
static inline int plat_iounmap(const volatile void __iomem *addr)
{
return 0;
}
#endif /* __ASM_MACH_AU1X00_IOREMAP_H */

6
arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
Просмотреть файл

@@ -13,16 +13,16 @@ static inline unsigned long bcm63xx_gpio_count(void)
case BCM6328_CPU_ID:
return 32;
case BCM3368_CPU_ID:
case BCM6358_CPU_ID:
return 40;
case BCM6338_CPU_ID:
return 8;
case BCM6345_CPU_ID:
return 16;
case BCM6362_CPU_ID:
return 48;
case BCM6358_CPU_ID:
case BCM6368_CPU_ID:
return 38;
case BCM6362_CPU_ID:
return 48;
case BCM6348_CPU_ID:
default:
return 37;

4
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
Просмотреть файл

@@ -1367,8 +1367,8 @@
#define MISC_STRAPBUS_6328_REG 0x240
#define STRAPBUS_6328_FCVO_SHIFT 7
#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 18)
#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 18)
/*************************************************************************
* _REG relative to RSET_PCIE

5
arch/mips/include/asm/mach-bcm63xx/ioremap.h
Просмотреть файл

@@ -4,11 +4,6 @@
#include <bcm63xx_cpu.h>
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline int is_bcm63xx_internal_registers(phys_addr_t offset)
{
switch (bcm63xx_get_cpu_id()) {

5
arch/mips/include/asm/mach-bmips/ioremap.h
Просмотреть файл

@@ -4,11 +4,6 @@
#include <linux/types.h>
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline int is_bmips_internal_registers(phys_addr_t offset)
{
if (offset >= 0xfff80000)

15
arch/mips/include/asm/mach-emma2rh/irq.h
Просмотреть файл

@@ -1,15 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_EMMA2RH_IRQ_H
#define __ASM_MACH_EMMA2RH_IRQ_H
#define NR_IRQS 256
#include <asm/mach-generic/irq.h>
#endif /* __ASM_MACH_EMMA2RH_IRQ_H */

9
arch/mips/include/asm/mach-generic/ioremap.h
Просмотреть файл

@@ -7,15 +7,6 @@
#include <linux/types.h>
/*
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{

6
arch/mips/include/asm/mach-generic/irq.h
Просмотреть файл

@@ -36,10 +36,4 @@
#endif /* CONFIG_IRQ_MIPS_CPU */
#ifdef CONFIG_MIPS_GIC
#ifndef MIPS_GIC_IRQ_BASE
#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
#endif
#endif /* CONFIG_MIPS_GIC */
#endif /* __ASM_MACH_GENERIC_IRQ_H */

12
arch/mips/include/asm/mach-ip27/spaces.h
Просмотреть файл

@@ -10,17 +10,19 @@
#ifndef _ASM_MACH_IP27_SPACES_H
#define _ASM_MACH_IP27_SPACES_H
#include <linux/const.h>
/*
* IP27 uses the R10000's uncached attribute feature. Attribute 3 selects
* uncached memory addressing. Hide the definitions on 32-bit compilation
* of the compat-vdso code.
*/
#ifdef CONFIG_64BIT
#define HSPEC_BASE 0x9000000000000000
#define IO_BASE 0x9200000000000000
#define MSPEC_BASE 0x9400000000000000
#define UNCAC_BASE 0x9600000000000000
#define CAC_BASE 0xa800000000000000
#define HSPEC_BASE _AC(0x9000000000000000, UL)
#define IO_BASE _AC(0x9200000000000000, UL)
#define MSPEC_BASE _AC(0x9400000000000000, UL)
#define UNCAC_BASE _AC(0x9600000000000000, UL)
#define CAC_BASE _AC(0xa800000000000000, UL)
#endif
#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK))

6
arch/mips/include/asm/mach-ip30/war.h
Просмотреть файл

@@ -8,19 +8,17 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#ifdef CONFIG_CPU_R10000
#define R10000_LLSC_WAR 1
#else
#define R10000_LLSC_WAR 0
#endif
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */

27
arch/mips/include/asm/mach-jz4740/base.h
Просмотреть файл

@@ -1,27 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_MACH_JZ4740_BASE_H__
#define __ASM_MACH_JZ4740_BASE_H__
#define JZ4740_CPM_BASE_ADDR 0x10000000
#define JZ4740_INTC_BASE_ADDR 0x10001000
#define JZ4740_WDT_BASE_ADDR 0x10002000
#define JZ4740_TCU_BASE_ADDR 0x10002010
#define JZ4740_RTC_BASE_ADDR 0x10003000
#define JZ4740_GPIO_BASE_ADDR 0x10010000
#define JZ4740_AIC_BASE_ADDR 0x10020000
#define JZ4740_MSC_BASE_ADDR 0x10021000
#define JZ4740_UART0_BASE_ADDR 0x10030000
#define JZ4740_UART1_BASE_ADDR 0x10031000
#define JZ4740_I2C_BASE_ADDR 0x10042000
#define JZ4740_SSI_BASE_ADDR 0x10043000
#define JZ4740_SADC_BASE_ADDR 0x10070000
#define JZ4740_EMC_BASE_ADDR 0x13010000
#define JZ4740_DMAC_BASE_ADDR 0x13020000
#define JZ4740_UHC_BASE_ADDR 0x13030000
#define JZ4740_UDC_BASE_ADDR 0x13040000
#define JZ4740_LCD_BASE_ADDR 0x13050000
#define JZ4740_SLCD_BASE_ADDR 0x13050000
#define JZ4740_CIM_BASE_ADDR 0x13060000
#define JZ4740_IPU_BASE_ADDR 0x13080000
#endif

23
arch/mips/include/asm/mach-jz4740/dma.h
Просмотреть файл

@@ -1,23 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ7420/JZ4740 DMA definitions
*/
#ifndef __ASM_MACH_JZ4740_DMA_H__
#define __ASM_MACH_JZ4740_DMA_H__
enum jz4740_dma_request_type {
JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
JZ4740_DMA_TYPE_UART_RECEIVE = 21,
JZ4740_DMA_TYPE_SPI_TRANSMIT = 22,
JZ4740_DMA_TYPE_SPI_RECEIVE = 23,
JZ4740_DMA_TYPE_MMC_TRANSMIT = 26,
JZ4740_DMA_TYPE_MMC_RECEIVE = 27,
JZ4740_DMA_TYPE_TCU = 28,
JZ4740_DMA_TYPE_SADC = 29,
JZ4740_DMA_TYPE_SLCD = 30,
};
#endif /* __ASM_JZ4740_DMA_H__ */

45
arch/mips/include/asm/mach-jz4740/irq.h
Просмотреть файл

@@ -8,49 +8,6 @@
#define __ASM_MACH_JZ4740_IRQ_H__
#define MIPS_CPU_IRQ_BASE 0
#define JZ4740_IRQ_BASE 8
#ifdef CONFIG_MACH_JZ4740
# define NR_INTC_IRQS 32
#else
# define NR_INTC_IRQS 64
#endif
/* 1st-level interrupts */
#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
#define JZ4740_IRQ_I2C JZ4740_IRQ(1)
#define JZ4740_IRQ_UHC JZ4740_IRQ(3)
#define JZ4740_IRQ_UART1 JZ4740_IRQ(8)
#define JZ4740_IRQ_UART0 JZ4740_IRQ(9)
#define JZ4740_IRQ_SADC JZ4740_IRQ(12)
#define JZ4740_IRQ_MSC JZ4740_IRQ(14)
#define JZ4740_IRQ_RTC JZ4740_IRQ(15)
#define JZ4740_IRQ_SSI JZ4740_IRQ(16)
#define JZ4740_IRQ_CIM JZ4740_IRQ(17)
#define JZ4740_IRQ_AIC JZ4740_IRQ(18)
#define JZ4740_IRQ_ETH JZ4740_IRQ(19)
#define JZ4740_IRQ_DMAC JZ4740_IRQ(20)
#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21)
#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22)
#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23)
#define JZ4740_IRQ_UDC JZ4740_IRQ(24)
#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25)
#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26)
#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27)
#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28)
#define JZ4740_IRQ_IPU JZ4740_IRQ(29)
#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
#define JZ4780_IRQ_TCU2 JZ4740_IRQ(25)
/* 2nd-level interrupts */
#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(NR_INTC_IRQS) + (x))
#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(NR_INTC_IRQS + 16) + (x))
#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(NR_INTC_IRQS + 144)
#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
#define NR_IRQS 256
#endif

126
arch/mips/include/asm/mach-jz4740/timer.h
Просмотреть файл

@@ -1,126 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 platform timer support
*/
#ifndef __ASM_MACH_JZ4740_TIMER
#define __ASM_MACH_JZ4740_TIMER
#define JZ_REG_TIMER_STOP 0x0C
#define JZ_REG_TIMER_STOP_SET 0x1C
#define JZ_REG_TIMER_STOP_CLEAR 0x2C
#define JZ_REG_TIMER_ENABLE 0x00
#define JZ_REG_TIMER_ENABLE_SET 0x04
#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
#define JZ_REG_TIMER_FLAG 0x10
#define JZ_REG_TIMER_FLAG_SET 0x14
#define JZ_REG_TIMER_FLAG_CLEAR 0x18
#define JZ_REG_TIMER_MASK 0x20
#define JZ_REG_TIMER_MASK_SET 0x24
#define JZ_REG_TIMER_MASK_CLEAR 0x28
#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
#define JZ_TIMER_IRQ_FULL(x) BIT(x)
#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
extern void __iomem *jz4740_timer_base;
void __init jz4740_timer_init(void);
void jz4740_timer_enable_watchdog(void);
void jz4740_timer_disable_watchdog(void);
static inline void jz4740_timer_stop(unsigned int timer)
{
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
}
static inline void jz4740_timer_start(unsigned int timer)
{
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
}
static inline bool jz4740_timer_is_enabled(unsigned int timer)
{
return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
}
static inline void jz4740_timer_enable(unsigned int timer)
{
writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
}
static inline void jz4740_timer_disable(unsigned int timer)
{
writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
}
static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
{
writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
}
static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
{
writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
}
static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
{
writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
}
static inline uint16_t jz4740_timer_get_count(unsigned int timer)
{
return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
}
static inline void jz4740_timer_ack_full(unsigned int timer)
{
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
}
static inline void jz4740_timer_irq_full_enable(unsigned int timer)
{
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
}
static inline void jz4740_timer_irq_full_disable(unsigned int timer)
{
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
}
static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
{
writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
}
static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
{
return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
}
#endif

1
arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
Просмотреть файл

@@ -46,7 +46,6 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32

14
arch/mips/include/asm/mach-lasat/irq.h
Просмотреть файл

@@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_MACH_LASAT_IRQ_H
#define _ASM_MACH_LASAT_IRQ_H
#define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
#define LASAT_IRQ_BASE 8
#define LASAT_IRQ_END 23
#define NR_IRQS 24
#include <asm/mach-generic/irq.h>
#endif /* _ASM_MACH_LASAT_IRQ_H */

28
arch/mips/include/asm/mach-lasat/mach-gt64120.h
Просмотреть файл

@@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This is a direct copy of the ev96100.h file, with a global
* search and replace. The numbers are the same.
*
* The reason I'm duplicating this is so that the 64120/96100
* defines won't be confusing in the source code.
*/
#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
#define _ASM_GT64120_LASAT_GT64120_DEP_H
/*
* GT64120 config space base address on Lasat 100
*/
#define GT64120_BASE (KSEG1ADDR(0x14000000))
/*
* PCI Bus allocation
*
* (Guessing ...)
*/
#define GT_PCI_MEM_BASE 0x12000000UL
#define GT_PCI_MEM_SIZE 0x02000000UL
#define GT_PCI_IO_BASE 0x10000000UL
#define GT_PCI_IO_SIZE 0x02000000UL
#define GT_ISA_IO_BASE PCI_IO_BASE
#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */

1
arch/mips/include/asm/mach-loongson2ef/loongson.h
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@@ -244,6 +244,7 @@ static inline void do_perfcnt_IRQ(void)
#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
#include <linux/cpufreq.h>
extern struct cpufreq_frequency_table loongson2_clockmod_table[];
extern int loongson2_cpu_set_rate(unsigned long rate_khz);
#endif
/*

11
arch/mips/include/asm/mach-loongson64/boot_param.h
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@@ -192,6 +192,11 @@ struct boot_params {
struct efi_reset_system_t reset_system;
};
enum loongson_bridge_type {
LS7A = 1,
RS780E = 2
};
struct loongson_system_configuration {
u32 nr_cpus;
u32 nr_nodes;
@@ -200,6 +205,7 @@ struct loongson_system_configuration {
u16 boot_cpu_id;
u16 reserved_cpus_mask;
enum loongson_cpu_type cputype;
enum loongson_bridge_type bridgetype;
u64 ht_control_base;
u64 pci_mem_start_addr;
u64 pci_mem_end_addr;
@@ -215,9 +221,14 @@ struct loongson_system_configuration {
u32 nr_sensors;
struct sensor_device sensors[MAX_SENSORS];
u64 workarounds;
void (*early_config)(void);
};
extern struct efi_memory_map_loongson *loongson_memmap;
extern struct loongson_system_configuration loongson_sysconf;
extern u32 node_id_offset;
extern void ls7a_early_config(void);
extern void rs780e_early_config(void);
#endif

1
arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
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@@ -48,5 +48,6 @@
#define cpu_hwrena_impl_bits 0xc0000000
#define cpu_has_mac2008_only 1
#define cpu_has_mips_r2_exec_hazard 0
#define cpu_has_perf_cntr_intr_bit 0
#endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */

74
arch/mips/include/asm/mach-loongson64/cpucfg-emul.h Обычный файл
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@@ -0,0 +1,74 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_
#define _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_
#include <asm/cpu-info.h>
#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
#include <loongson_regs.h>
#define LOONGSON_FPREV_MASK 0x7
void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c);
static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
{
/* All supported cores have non-zero LOONGSON_CFG1 data. */
return c->loongson3_cpucfg_data[0] != 0;
}
static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
__u64 sel)
{
switch (sel) {
case LOONGSON_CFG0:
return c->processor_id;
case LOONGSON_CFG1:
case LOONGSON_CFG2:
case LOONGSON_CFG3:
return c->loongson3_cpucfg_data[sel - 1];
case LOONGSON_CFG4:
case LOONGSON_CFG5:
/* CPUCFG selects 4 and 5 are related to the input clock
* signal.
*
* Unimplemented for now.
*/
return 0;
case LOONGSON_CFG6:
/* CPUCFG select 6 is for the undocumented Safe Extension. */
return 0;
case LOONGSON_CFG7:
/* CPUCFG select 7 is for the virtualization extension.
* We don't know if the two currently known features are
* supported on older cores according to the public
* documentation, so leave this at zero.
*/
return 0;
}
/*
* Return 0 for unrecognized CPUCFG selects, which is real hardware
* behavior observed on Loongson 3A R4.
*/
return 0;
}
#else
static inline void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
{
}
static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
{
return false;
}
static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
__u64 sel)
{
return 0;
}
#endif
#endif /* _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ */

29
arch/mips/include/asm/mach-loongson64/loongson_regs.h
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@@ -67,6 +67,8 @@ static inline u32 read_cpucfg(u32 reg)
#define LOONGSON_CFG1_SFBP BIT(29)
#define LOONGSON_CFG1_CDMAP BIT(30)
#define LOONGSON_CFG1_FPREV_OFFSET 1
#define LOONGSON_CFG2 0x2
#define LOONGSON_CFG2_LEXT1 BIT(0)
#define LOONGSON_CFG2_LEXT2 BIT(1)
@@ -77,12 +79,12 @@ static inline u32 read_cpucfg(u32 reg)
#define LOONGSON_CFG2_LBT3 BIT(6)
#define LOONGSON_CFG2_LBTMMU BIT(7)
#define LOONGSON_CFG2_LPMP BIT(8)
#define LOONGSON_CFG2_LPMPREV GENMASK(11, 9)
#define LOONGSON_CFG2_LPMREV GENMASK(11, 9)
#define LOONGSON_CFG2_LAMO BIT(12)
#define LOONGSON_CFG2_LPIXU BIT(13)
#define LOONGSON_CFG2_LPIXUN BIT(14)
#define LOONGSON_CFG2_LZVP BIT(15)
#define LOONGSON_CFG2_LZVREV GENMASK(18, 16)
#define LOONGSON_CFG2_LPIXNU BIT(14)
#define LOONGSON_CFG2_LVZP BIT(15)
#define LOONGSON_CFG2_LVZREV GENMASK(18, 16)
#define LOONGSON_CFG2_LGFTP BIT(19)
#define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20)
#define LOONGSON_CFG2_LLFTP BIT(23)
@@ -90,6 +92,13 @@ static inline u32 read_cpucfg(u32 reg)
#define LOONGSON_CFG2_LCSRP BIT(27)
#define LOONGSON_CFG2_LDISBLIKELY BIT(28)
#define LOONGSON_CFG2_LPMREV_OFFSET 9
#define LOONGSON_CFG2_LPM_REV1 (1 << LOONGSON_CFG2_LPMREV_OFFSET)
#define LOONGSON_CFG2_LPM_REV2 (2 << LOONGSON_CFG2_LPMREV_OFFSET)
#define LOONGSON_CFG2_LVZREV_OFFSET 16
#define LOONGSON_CFG2_LVZ_REV1 (1 << LOONGSON_CFG2_LVZREV_OFFSET)
#define LOONGSON_CFG2_LVZ_REV2 (2 << LOONGSON_CFG2_LVZREV_OFFSET)
#define LOONGSON_CFG3 0x3
#define LOONGSON_CFG3_LCAMP BIT(0)
#define LOONGSON_CFG3_LCAMREV GENMASK(3, 1)
@@ -97,6 +106,16 @@ static inline u32 read_cpucfg(u32 reg)
#define LOONGSON_CFG3_LCAMKW GENMASK(19, 12)
#define LOONGSON_CFG3_LCAMVW GENMASK(27, 20)
#define LOONGSON_CFG3_LCAMREV_OFFSET 1
#define LOONGSON_CFG3_LCAM_REV1 (1 << LOONGSON_CFG3_LCAMREV_OFFSET)
#define LOONGSON_CFG3_LCAM_REV2 (2 << LOONGSON_CFG3_LCAMREV_OFFSET)
#define LOONGSON_CFG3_LCAMNUM_OFFSET 4
#define LOONGSON_CFG3_LCAMNUM_REV1 (0x3f << LOONGSON_CFG3_LCAMNUM_OFFSET)
#define LOONGSON_CFG3_LCAMKW_OFFSET 12
#define LOONGSON_CFG3_LCAMKW_REV1 (0x27 << LOONGSON_CFG3_LCAMKW_OFFSET)
#define LOONGSON_CFG3_LCAMVW_OFFSET 20
#define LOONGSON_CFG3_LCAMVW_REV1 (0x3f << LOONGSON_CFG3_LCAMVW_OFFSET)
#define LOONGSON_CFG4 0x4
#define LOONGSON_CFG4_CCFREQ GENMASK(31, 0)
@@ -139,7 +158,7 @@ static inline u64 csr_readq(u32 reg)
{
u64 __res;
/* DWRCSR reg, val */
/* DRDCSR reg, val */
__asm__ __volatile__(
"parse_r __res,%0\n\t"
"parse_r reg,%1\n\t"

36
arch/mips/include/asm/mach-loongson64/mc146818rtc.h
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@@ -1,36 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org)
*
* RTC routines for PC style attached Dallas chip.
*/
#ifndef __ASM_MACH_LOONGSON64_MC146818RTC_H
#define __ASM_MACH_LOONGSON64_MC146818RTC_H
#include <linux/io.h>
#define RTC_PORT(x) (0x70 + (x))
#define RTC_IRQ 8
static inline unsigned char CMOS_READ(unsigned long addr)
{
outb_p(addr, RTC_PORT(0));
return inb_p(RTC_PORT(1));
}
static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
{
outb_p(addr, RTC_PORT(0));
outb_p(data, RTC_PORT(1));
}
#define RTC_ALWAYS_BCD 0
#ifndef mc146818_decode_year
#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
#endif
#endif /* __ASM_MACH_LOONGSON64_MC146818RTC_H */

8
arch/mips/include/asm/mach-loongson64/spaces.h
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@@ -6,5 +6,13 @@
#define CAC_BASE _AC(0x9800000000000000, UL)
#endif /* CONFIG_64BIT */
/* Skip 128k to trap NULL pointer dereferences */
#define PCI_IOBASE _AC(0xc000000000000000 + SZ_128K, UL)
#define PCI_IOSIZE SZ_16M
#define MAP_BASE (PCI_IOBASE + PCI_IOSIZE)
/* Reserved at the start of PCI_IOBASE for legacy drivers */
#define MMIO_LOWER_RESERVED 0x10000
#include <asm/mach-generic/spaces.h>
#endif

22
arch/mips/include/asm/mach-pmcs-msp71xx/cpu-feature-overrides.h
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@@ -1,22 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H
#define cpu_has_mips16 1
#define cpu_has_dsp 1
/* #define cpu_has_dsp2 ??? - do runtime detection */
#define cpu_has_mipsmt 1
#define cpu_has_fpu 0
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif /* __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H */

139
arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h
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@@ -1,139 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the MSP interrupt controller.
*
* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
* Author: Carsten Langgaard, carstenl@mips.com
*
* ########################################################################
*
* ########################################################################
*/
#ifndef _MSP_CIC_INT_H
#define _MSP_CIC_INT_H
/*
* The PMC-Sierra CIC interrupts are all centrally managed by the
* CIC sub-system.
* We attempt to keep the interrupt numbers as consistent as possible
* across all of the MSP devices, but some differences will creep in ...
* The interrupts which are directly forwarded to the MIPS core interrupts
* are assigned interrupts in the range 0-7, interrupts cascaded through
* the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4
* (MSP_INT_CIC). Currently we don't really distinguish between VPE1
* and VPE0 (or thread contexts for that matter). Will have to fix.
* The PER interrupts are assigned interrupts in the range 40-71.
*/
/*
* IRQs directly forwarded to the CPU
*/
#define MSP_MIPS_INTBASE 0
#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */
#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */
#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */
#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */
/*
* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
* These defines should be tied to the register definitions for the CIC
* interrupt routine. For now, just use hard-coded values.
*/
#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8)
#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0)
/* External interrupt 0 */
#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1)
/* External interrupt 1 */
#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2)
/* External interrupt 2 */
#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3)
/* External interrupt 3 */
#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4)
/* CPU interface interrupt */
#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5)
/* External interrupt 4 */
#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6)
/* Cascaded IRQ for USB */
#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7)
/* Sec engine mailbox IRQ */
#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8)
/* External interrupt 5 */
#define MSP_INT_TDM (MSP_CIC_INTBASE + 9)
/* TDM interrupt */
#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10)
/* Cascaded IRQ for MAC 0 */
#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11)
/* Cascaded IRQ for MAC 1 */
#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12)
/* Cascaded IRQ for sec engine */
#define MSP_INT_PER (MSP_CIC_INTBASE + 13)
/* Peripheral interrupt */
#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14)
/* SLP timer 0 */
#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15)
/* SLP timer 1 */
#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16)
/* SLP timer 2 */
#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17)
/* VPE0 MIPS timer */
#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18)
/* Block Copy */
#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19)
/* UART 0 */
#define MSP_INT_PCI (MSP_CIC_INTBASE + 20)
/* PCI subsystem */
#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21)
/* External interrupt 5 */
#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22)
/* PCI Message Signal */
#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23)
/* Cascaded ADSL2+ SAR IRQ */
#define MSP_INT_DSL (MSP_CIC_INTBASE + 24)
/* ADSL2+ IRQ */
#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25)
/* SLP error condition */
#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26)
/* VPE1 MIPS timer */
#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27)
/* VPE0 Performance counter */
#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28)
/* VPE1 Performance counter */
#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29)
/* External interrupt 5 */
#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30)
/* VPE0 Software interrupt */
#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31)
/* VPE0 Software interrupt */
/*
* IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
*/
#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32)
/* Reserved 0-1 */
#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
/* UART 1 */
/* Reserved 3-5 */
#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
/* 2-wire */
#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
/* Peripheral timer block out 0 */
#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
/* Peripheral timer block out 1 */
/* Reserved 9 */
#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
/* SPI RX complete */
#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
/* SPI TX complete */
#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
/* GPIO */
#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
/* Peripheral error */
/* Reserved 14-31 */
#endif /* !_MSP_CIC_INT_H */

343
arch/mips/include/asm/mach-pmcs-msp71xx/msp_gpio_macros.h
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@@ -1,343 +0,0 @@
/*
*
* Macros for external SMP-safe access to the PMC MSP71xx reference
* board GPIO pins
*
* Copyright 2010 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MSP_GPIO_MACROS_H__
#define __MSP_GPIO_MACROS_H__
#include <msp_regops.h>
#include <msp_regs.h>
#ifdef CONFIG_PMC_MSP7120_GW
#define MSP_NUM_GPIOS 20
#else
#define MSP_NUM_GPIOS 28
#endif
/* -- GPIO Enumerations -- */
enum msp_gpio_data {
MSP_GPIO_LO = 0,
MSP_GPIO_HI = 1,
MSP_GPIO_NONE, /* Special - Means pin is out of range */
MSP_GPIO_TOGGLE, /* Special - Sets pin to opposite */
};
enum msp_gpio_mode {
MSP_GPIO_INPUT = 0x0,
/* MSP_GPIO_ INTERRUPT = 0x1, Not supported yet */
MSP_GPIO_UART_INPUT = 0x2, /* Only GPIO 4 or 5 */
MSP_GPIO_OUTPUT = 0x8,
MSP_GPIO_UART_OUTPUT = 0x9, /* Only GPIO 2 or 3 */
MSP_GPIO_PERIF_TIMERA = 0x9, /* Only GPIO 0 or 1 */
MSP_GPIO_PERIF_TIMERB = 0xa, /* Only GPIO 0 or 1 */
MSP_GPIO_UNKNOWN = 0xb, /* No such GPIO or mode */
};
/* -- Static Tables -- */
/* Maps pins to data register */
static volatile u32 * const MSP_GPIO_DATA_REGISTER[] = {
/* GPIO 0 and 1 on the first register */
GPIO_DATA1_REG, GPIO_DATA1_REG,
/* GPIO 2, 3, 4, and 5 on the second register */
GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG,
/* GPIO 6, 7, 8, and 9 on the third register */
GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG,
/* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG,
GPIO_DATA4_REG, GPIO_DATA4_REG,
/* GPIO 16 - 23 on the first strange EXTENDED register */
EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
/* GPIO 24 - 27 on the second strange EXTENDED register */
EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG,
EXTENDED_GPIO2_REG,
};
/* Maps pins to mode register */
static volatile u32 * const MSP_GPIO_MODE_REGISTER[] = {
/* GPIO 0 and 1 on the first register */
GPIO_CFG1_REG, GPIO_CFG1_REG,
/* GPIO 2, 3, 4, and 5 on the second register */
GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG,
/* GPIO 6, 7, 8, and 9 on the third register */
GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG,
/* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG,
GPIO_CFG4_REG, GPIO_CFG4_REG,
/* GPIO 16 - 23 on the first strange EXTENDED register */
EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
/* GPIO 24 - 27 on the second strange EXTENDED register */
EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG,
EXTENDED_GPIO2_REG,
};
/* Maps 'basic' pins to relative offset from 0 per register */
static int MSP_GPIO_OFFSET[] = {
/* GPIO 0 and 1 on the first register */
0, 0,
/* GPIO 2, 3, 4, and 5 on the second register */
2, 2, 2, 2,
/* GPIO 6, 7, 8, and 9 on the third register */
6, 6, 6, 6,
/* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
10, 10, 10, 10, 10, 10,
};
/* Maps MODE to allowed pin mask */
static unsigned int MSP_GPIO_MODE_ALLOWED[] = {
0xffffffff, /* Mode 0 - INPUT */
0x00000, /* Mode 1 - INTERRUPT */
0x00030, /* Mode 2 - UART_INPUT (GPIO 4, 5)*/
0, 0, 0, 0, 0, /* Modes 3, 4, 5, 6, and 7 are reserved */
0xffffffff, /* Mode 8 - OUTPUT */
0x0000f, /* Mode 9 - UART_OUTPUT/
PERF_TIMERA (GPIO 0, 1, 2, 3) */
0x00003, /* Mode a - PERF_TIMERB (GPIO 0, 1) */
0x00000, /* Mode b - Not really a mode! */
};
/* -- Bit masks -- */
/* This gives you the 'register relative offset gpio' number */
#define OFFSET_GPIO_NUMBER(gpio) (gpio - MSP_GPIO_OFFSET[gpio])
/* These take the 'register relative offset gpio' number */
#define BASIC_DATA_REG_MASK(ogpio) (1 << ogpio)
#define BASIC_MODE_REG_VALUE(mode, ogpio) \
(mode << BASIC_MODE_REG_SHIFT(ogpio))
#define BASIC_MODE_REG_MASK(ogpio) \
BASIC_MODE_REG_VALUE(0xf, ogpio)
#define BASIC_MODE_REG_SHIFT(ogpio) (ogpio * 4)
#define BASIC_MODE_REG_FROM_REG(data, ogpio) \
((data & BASIC_MODE_REG_MASK(ogpio)) >> BASIC_MODE_REG_SHIFT(ogpio))
/* These take the actual GPIO number (0 through 15) */
#define BASIC_DATA_MASK(gpio) \
BASIC_DATA_REG_MASK(OFFSET_GPIO_NUMBER(gpio))
#define BASIC_MODE_MASK(gpio) \
BASIC_MODE_REG_MASK(OFFSET_GPIO_NUMBER(gpio))
#define BASIC_MODE(mode, gpio) \
BASIC_MODE_REG_VALUE(mode, OFFSET_GPIO_NUMBER(gpio))
#define BASIC_MODE_SHIFT(gpio) \
BASIC_MODE_REG_SHIFT(OFFSET_GPIO_NUMBER(gpio))
#define BASIC_MODE_FROM_REG(data, gpio) \
BASIC_MODE_REG_FROM_REG(data, OFFSET_GPIO_NUMBER(gpio))
/*
* Each extended GPIO register is 32 bits long and is responsible for up to
* eight GPIOs. The least significant 16 bits contain the set and clear bit
* pair for each of the GPIOs. The most significant 16 bits contain the
* disable and enable bit pair for each of the GPIOs. For example, the
* extended GPIO reg for GPIOs 16-23 is as follows:
*
* 31: GPIO23_DISABLE
* ...
* 19: GPIO17_DISABLE
* 18: GPIO17_ENABLE
* 17: GPIO16_DISABLE
* 16: GPIO16_ENABLE
* ...
* 3: GPIO17_SET
* 2: GPIO17_CLEAR
* 1: GPIO16_SET
* 0: GPIO16_CLEAR
*/
/* This gives the 'register relative offset gpio' number */
#define EXTENDED_OFFSET_GPIO(gpio) (gpio < 24 ? gpio - 16 : gpio - 24)
/* These take the 'register relative offset gpio' number */
#define EXTENDED_REG_DISABLE(ogpio) (0x2 << ((ogpio * 2) + 16))
#define EXTENDED_REG_ENABLE(ogpio) (0x1 << ((ogpio * 2) + 16))
#define EXTENDED_REG_SET(ogpio) (0x2 << (ogpio * 2))
#define EXTENDED_REG_CLR(ogpio) (0x1 << (ogpio * 2))
/* These take the actual GPIO number (16 through 27) */
#define EXTENDED_DISABLE(gpio) \
EXTENDED_REG_DISABLE(EXTENDED_OFFSET_GPIO(gpio))
#define EXTENDED_ENABLE(gpio) \
EXTENDED_REG_ENABLE(EXTENDED_OFFSET_GPIO(gpio))
#define EXTENDED_SET(gpio) \
EXTENDED_REG_SET(EXTENDED_OFFSET_GPIO(gpio))
#define EXTENDED_CLR(gpio) \
EXTENDED_REG_CLR(EXTENDED_OFFSET_GPIO(gpio))
#define EXTENDED_FULL_MASK (0xffffffff)
/* -- API inline-functions -- */
/*
* Gets the current value of the specified pin
*/
static inline enum msp_gpio_data msp_gpio_pin_get(unsigned int gpio)
{
u32 pinhi_mask = 0, pinhi_mask2 = 0;
if (gpio >= MSP_NUM_GPIOS)
return MSP_GPIO_NONE;
if (gpio < 16) {
pinhi_mask = BASIC_DATA_MASK(gpio);
} else {
/*
* Two cases are possible with the EXTENDED register:
* - In output mode (ENABLED flag set), check the CLR bit
* - In input mode (ENABLED flag not set), check the SET bit
*/
pinhi_mask = EXTENDED_ENABLE(gpio) | EXTENDED_CLR(gpio);
pinhi_mask2 = EXTENDED_SET(gpio);
}
if (((*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask) == pinhi_mask) ||
(*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask2))
return MSP_GPIO_HI;
else
return MSP_GPIO_LO;
}
/* Sets the specified pin to the specified value */
static inline void msp_gpio_pin_set(enum msp_gpio_data data, unsigned int gpio)
{
if (gpio >= MSP_NUM_GPIOS)
return;
if (gpio < 16) {
if (data == MSP_GPIO_TOGGLE)
toggle_reg32(MSP_GPIO_DATA_REGISTER[gpio],
BASIC_DATA_MASK(gpio));
else if (data == MSP_GPIO_HI)
set_reg32(MSP_GPIO_DATA_REGISTER[gpio],
BASIC_DATA_MASK(gpio));
else
clear_reg32(MSP_GPIO_DATA_REGISTER[gpio],
BASIC_DATA_MASK(gpio));
} else {
if (data == MSP_GPIO_TOGGLE) {
/* Special ugly case:
* We have to read the CLR bit.
* If set, we write the CLR bit.
* If not, we write the SET bit.
*/
u32 tmpdata;
custom_read_reg32(MSP_GPIO_DATA_REGISTER[gpio],
tmpdata);
if (tmpdata & EXTENDED_CLR(gpio))
tmpdata = EXTENDED_CLR(gpio);
else
tmpdata = EXTENDED_SET(gpio);
custom_write_reg32(MSP_GPIO_DATA_REGISTER[gpio],
tmpdata);
} else {
u32 newdata;
if (data == MSP_GPIO_HI)
newdata = EXTENDED_SET(gpio);
else
newdata = EXTENDED_CLR(gpio);
set_value_reg32(MSP_GPIO_DATA_REGISTER[gpio],
EXTENDED_FULL_MASK, newdata);
}
}
}
/* Sets the specified pin to the specified value */
static inline void msp_gpio_pin_hi(unsigned int gpio)
{
msp_gpio_pin_set(MSP_GPIO_HI, gpio);
}
/* Sets the specified pin to the specified value */
static inline void msp_gpio_pin_lo(unsigned int gpio)
{
msp_gpio_pin_set(MSP_GPIO_LO, gpio);
}
/* Sets the specified pin to the opposite value */
static inline void msp_gpio_pin_toggle(unsigned int gpio)
{
msp_gpio_pin_set(MSP_GPIO_TOGGLE, gpio);
}
/* Gets the mode of the specified pin */
static inline enum msp_gpio_mode msp_gpio_pin_get_mode(unsigned int gpio)
{
enum msp_gpio_mode retval = MSP_GPIO_UNKNOWN;
uint32_t data;
if (gpio >= MSP_NUM_GPIOS)
return retval;
data = *MSP_GPIO_MODE_REGISTER[gpio];
if (gpio < 16) {
retval = BASIC_MODE_FROM_REG(data, gpio);
} else {
/* Extended pins can only be either INPUT or OUTPUT */
if (data & EXTENDED_ENABLE(gpio))
retval = MSP_GPIO_OUTPUT;
else
retval = MSP_GPIO_INPUT;
}
return retval;
}
/*
* Sets the specified mode on the requested pin
* Returns 0 on success, or -1 if that mode is not allowed on this pin
*/
static inline int msp_gpio_pin_mode(enum msp_gpio_mode mode, unsigned int gpio)
{
u32 modemask, newmode;
if ((1 << gpio) & ~MSP_GPIO_MODE_ALLOWED[mode])
return -1;
if (gpio >= MSP_NUM_GPIOS)
return -1;
if (gpio < 16) {
modemask = BASIC_MODE_MASK(gpio);
newmode = BASIC_MODE(mode, gpio);
} else {
modemask = EXTENDED_FULL_MASK;
if (mode == MSP_GPIO_INPUT)
newmode = EXTENDED_DISABLE(gpio);
else
newmode = EXTENDED_ENABLE(gpio);
}
/* Do the set atomically */
set_value_reg32(MSP_GPIO_MODE_REGISTER[gpio], modemask, newmode);
return 0;
}
#endif /* __MSP_GPIO_MACROS_H__ */

31
arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h
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@@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the MSP interrupt handlers.
*
* Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved.
* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
*
* ########################################################################
*
* ########################################################################
*/
#ifndef _MSP_INT_H
#define _MSP_INT_H
/*
* The PMC-Sierra MSP product line has at least two different interrupt
* controllers, the SLP register based scheme and the CIC interrupt
* controller block mechanism. This file distinguishes between them
* so that devices see a uniform interface.
*/
#if defined(CONFIG_IRQ_MSP_SLP)
#include "msp_slp_int.h"
#elif defined(CONFIG_IRQ_MSP_CIC)
#include "msp_cic_int.h"
#else
#error "What sort of interrupt controller does *your* MSP have?"
#endif
#endif /* !_MSP_INT_H */

189
arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h
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@@ -1,189 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2000-2006 PMC-Sierra INC.
*
* PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
* SOFTWARE.
*/
#ifndef _MSP_PCI_H_
#define _MSP_PCI_H_
#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
/*
* It is convenient to program the OATRAN register so that
* Athena virtual address space and PCI address space are
* the same. This is not a requirement, just a convenience.
*
* The only hard restrictions on the value of OATRAN is that
* OATRAN must not be programmed to allow translated memory
* addresses to fall within the lowest 512MB of
* PCI address space. This region is hardcoded
* for use as Athena PCI Host Controller target
* access memory space to the Athena's SDRAM.
*
* Note that OATRAN applies only to memory accesses, not
* to I/O accesses.
*
* To program OATRAN to make Athena virtual address space
* and PCI address space have the same values, OATRAN
* is to be programmed to 0xB8000000. The top seven
* bits of the value mimic the seven bits clipped off
* by the PCI Host controller.
*
* With OATRAN at the said value, when the CPU does
* an access to its virtual address at, say 0xB900_5000,
* the address appearing on the PCI bus will be
* 0xB900_5000.
* - Michael Penner
*/
#define MSP_PCI_OATRAN 0xB8000000UL
#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL)
#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000)
#define MSP_PCI_SPACE_END \
(MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL)
#define MSP_PCI_IOSPACE_SIZE 0x1000
#define MSP_PCI_IOSPACE_END \
(MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
/* IRQ for PCI status interrupts */
#define PCI_STAT_IRQ 20
#define QFLUSH_REG_1 0xB7F40000
typedef volatile unsigned int pcireg;
typedef void * volatile ppcireg;
struct pci_block_copy
{
pcireg unused1; /* +0x00 */
pcireg unused2; /* +0x04 */
ppcireg unused3; /* +0x08 */
ppcireg unused4; /* +0x0C */
pcireg unused5; /* +0x10 */
pcireg unused6; /* +0x14 */
pcireg unused7; /* +0x18 */
ppcireg unused8; /* +0x1C */
ppcireg unused9; /* +0x20 */
pcireg unusedA; /* +0x24 */
ppcireg unusedB; /* +0x28 */
ppcireg unusedC; /* +0x2C */
};
enum
{
config_device_vendor, /* 0 */
config_status_command, /* 1 */
config_class_revision, /* 2 */
config_BIST_header_latency_cache, /* 3 */
config_BAR0, /* 4 */
config_BAR1, /* 5 */
config_BAR2, /* 6 */
config_not_used7, /* 7 */
config_not_used8, /* 8 */
config_not_used9, /* 9 */
config_CIS, /* 10 */
config_subsystem, /* 11 */
config_not_used12, /* 12 */
config_capabilities, /* 13 */
config_not_used14, /* 14 */
config_lat_grant_irq, /* 15 */
config_message_control,/* 16 */
config_message_addr, /* 17 */
config_message_data, /* 18 */
config_VPD_addr, /* 19 */
config_VPD_data, /* 20 */
config_maxregs /* 21 - number of registers */
};
struct msp_pci_regs
{
pcireg hop_unused_00; /* +0x00 */
pcireg hop_unused_04; /* +0x04 */
pcireg hop_unused_08; /* +0x08 */
pcireg hop_unused_0C; /* +0x0C */
pcireg hop_unused_10; /* +0x10 */
pcireg hop_unused_14; /* +0x14 */
pcireg hop_unused_18; /* +0x18 */
pcireg hop_unused_1C; /* +0x1C */
pcireg hop_unused_20; /* +0x20 */
pcireg hop_unused_24; /* +0x24 */
pcireg hop_unused_28; /* +0x28 */
pcireg hop_unused_2C; /* +0x2C */
pcireg hop_unused_30; /* +0x30 */
pcireg hop_unused_34; /* +0x34 */
pcireg if_control; /* +0x38 */
pcireg oatran; /* +0x3C */
pcireg reset_ctl; /* +0x40 */
pcireg config_addr; /* +0x44 */
pcireg hop_unused_48; /* +0x48 */
pcireg msg_signaled_int_status; /* +0x4C */
pcireg msg_signaled_int_mask; /* +0x50 */
pcireg if_status; /* +0x54 */
pcireg if_mask; /* +0x58 */
pcireg hop_unused_5C; /* +0x5C */
pcireg hop_unused_60; /* +0x60 */
pcireg hop_unused_64; /* +0x64 */
pcireg hop_unused_68; /* +0x68 */
pcireg hop_unused_6C; /* +0x6C */
pcireg hop_unused_70; /* +0x70 */
struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
pcireg error_hdr1; /* +0xE0 */
pcireg error_hdr2; /* +0xE4 */
pcireg config[config_maxregs] __attribute__((aligned(256)));
};
#define BPCI_CFGADDR_BUSNUM_SHF 16
#define BPCI_CFGADDR_FUNCTNUM_SHF 8
#define BPCI_CFGADDR_REGNUM_SHF 2
#define BPCI_CFGADDR_ENABLE (1<<31)
#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */
#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */
#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */
#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */
#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */
#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */
#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */
#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */
#define BPCI_IFSTATUS_SER (1<<19) /* System error */
#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */
#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */
#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */
#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */
#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */
#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */
#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */
#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */
#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */
#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */
#define BPCI_RESETCTL_RT (1<<4) /* Release time */
#define BPCI_RESETCTL_CT (1<<8) /* Config time */
#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */
#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */
#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */
extern struct msp_pci_regs msp_pci_regs
__attribute__((section(".register")));
extern unsigned long msp_pci_config_space
__attribute__((section(".register")));
#endif /* !_MSP_PCI_H_ */

159
arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h
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@@ -1,159 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* MIPS boards bootprom interface for the Linux kernel.
*
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Author: Carsten Langgaard, carstenl@mips.com
*
* ########################################################################
*
* ########################################################################
*/
#ifndef _ASM_MSP_PROM_H
#define _ASM_MSP_PROM_H
#include <linux/types.h>
#define DEVICEID "deviceid"
#define FEATURES "features"
#define PROM_ENV "prom_env"
#define PROM_ENV_FILE "/proc/"PROM_ENV
#define PROM_ENV_SIZE 256
#define CPU_DEVID_FAMILY 0x0000ff00
#define CPU_DEVID_REVISION 0x000000ff
#define FPGA_IS_POLO(revision) \
(((revision >= 0xb0) && (revision < 0xd0)))
#define FPGA_IS_5000(revision) \
((revision >= 0x80) && (revision <= 0x90))
#define FPGA_IS_ZEUS(revision) ((revision < 0x7f))
#define FPGA_IS_DUET(revision) \
(((revision >= 0xa0) && (revision < 0xb0)))
#define FPGA_IS_MSP4200(revision) ((revision >= 0xd0))
#define FPGA_IS_MSP7100(revision) ((revision >= 0xd0))
#define MACHINE_TYPE_POLO "POLO"
#define MACHINE_TYPE_DUET "DUET"
#define MACHINE_TYPE_ZEUS "ZEUS"
#define MACHINE_TYPE_MSP2000REVB "MSP2000REVB"
#define MACHINE_TYPE_MSP5000 "MSP5000"
#define MACHINE_TYPE_MSP4200 "MSP4200"
#define MACHINE_TYPE_MSP7120 "MSP7120"
#define MACHINE_TYPE_MSP7130 "MSP7130"
#define MACHINE_TYPE_OTHER "OTHER"
#define MACHINE_TYPE_POLO_FPGA "POLO-FPGA"
#define MACHINE_TYPE_DUET_FPGA "DUET-FPGA"
#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA"
#define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA"
#define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA"
#define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA"
#define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA"
#define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA"
/* Device Family definitions */
#define FAMILY_FPGA 0x0000
#define FAMILY_ZEUS 0x1000
#define FAMILY_POLO 0x2000
#define FAMILY_DUET 0x4000
#define FAMILY_TRIAD 0x5000
#define FAMILY_MSP4200 0x4200
#define FAMILY_MSP4200_FPGA 0x4f00
#define FAMILY_MSP7100 0x7100
#define FAMILY_MSP7100_FPGA 0x7f00
/* Device Type definitions */
#define TYPE_MSP7120 0x7120
#define TYPE_MSP7130 0x7130
#define ENET_KEY 'E'
#define ENETTXD_KEY 'e'
#define PCI_KEY 'P'
#define PCIMUX_KEY 'p'
#define SEC_KEY 'S'
#define SPAD_KEY 'D'
#define TDM_KEY 'T'
#define ZSP_KEY 'Z'
#define FEATURE_NOEXIST '-'
#define FEATURE_EXIST '+'
#define ENET_MII 'M'
#define ENET_RMII 'R'
#define ENETTXD_FALLING 'F'
#define ENETTXD_RISING 'R'
#define PCI_HOST 'H'
#define PCI_PERIPHERAL 'P'
#define PCIMUX_FULL 'F'
#define PCIMUX_SINGLE 'S'
#define SEC_DUET 'D'
#define SEC_POLO 'P'
#define SEC_SLOW 'S'
#define SEC_TRIAD 'T'
#define SPAD_POLO 'P'
#define TDM_DUET 'D' /* DUET TDMs might exist */
#define TDM_POLO 'P' /* POLO TDMs might exist */
#define TDM_TRIAD 'T' /* TRIAD TDMs might exist */
#define ZSP_DUET 'D' /* one DUET zsp engine */
#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
extern char *prom_getenv(char *name);
extern void prom_init_cmdline(void);
extern void prom_meminit(void);
extern void prom_fixup_mem_map(unsigned long start_mem,
unsigned long end_mem);
extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
extern unsigned long get_deviceid(void);
extern char identify_enet(unsigned long interface_num);
extern char identify_enetTxD(unsigned long interface_num);
extern char identify_pci(void);
extern char identify_sec(void);
extern char identify_spad(void);
extern char identify_sec(void);
extern char identify_tdm(void);
extern char identify_zsp(void);
extern unsigned long identify_family(void);
extern unsigned long identify_revision(void);
/*
* The following macro calls prom_printf and puts the format string
* into an init section so it can be reclaimed.
*/
#define ppfinit(f, x...) \
do { \
static char _f[] __initdata = KERN_INFO f; \
printk(_f, ## x); \
} while (0)
/* Memory descriptor management. */
#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */
enum yamon_memtypes {
yamon_dontuse,
yamon_prom,
yamon_free,
};
struct prom_pmemblock {
unsigned long base; /* Within KSEG0. */
unsigned int size; /* In bytes. */
unsigned int type; /* free or prom memory */
};
extern int prom_argc;
extern char **prom_argv;
extern char **prom_envp;
extern int *prom_vec;
extern struct prom_pmemblock *prom_getmdesc(void);
#endif /* !_ASM_MSP_PROM_H */

237
arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
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@@ -1,237 +0,0 @@
/*
* SMP/VPE-safe functions to access "registers" (see note).
*
* NOTES:
* - These macros use ll/sc instructions, so it is your responsibility to
* ensure these are available on your platform before including this file.
* - The MIPS32 spec states that ll/sc results are undefined for uncached
* accesses. This means they can't be used on HW registers accessed
* through kseg1. Code which requires these macros for this purpose must
* front-end the registers with cached memory "registers" and have a single
* thread update the actual HW registers.
* - A maximum of 2k of code can be inserted between ll and sc. Every
* memory accesses between the instructions will increase the chance of
* sc failing and having to loop.
* - When using custom_read_reg32/custom_write_reg32 only perform the
* necessary logical operations on the register value in between these
* two calls. All other logic should be performed before the first call.
* - There is a bug on the R10000 chips which has a workaround. If you
* are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
* to be non-zero. If you are using this header from within linux, you may
* include <asm/war.h> before including this file to have this defined
* appropriately for you.
*
* Copyright 2005-2007 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc., 675
* Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_REGOPS_H__
#define __ASM_REGOPS_H__
#include <linux/types.h>
#include <asm/compiler.h>
#include <asm/war.h>
#ifndef R10000_LLSC_WAR
#define R10000_LLSC_WAR 0
#endif
#if R10000_LLSC_WAR == 1
#define __beqz "beqzl "
#else
#define __beqz "beqz "
#endif
#ifndef _LINUX_TYPES_H
typedef unsigned int u32;
#endif
/*
* Sets all the masked bits to the corresponding value bits
*/
static inline void set_value_reg32(volatile u32 *const addr,
u32 const mask,
u32 const value)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set arch=r4000 \n"
"1: ll %0, %1 # set_value_reg32 \n"
" and %0, %2 \n"
" or %0, %3 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
: "ir" (~mask), "ir" (value), GCC_OFF_SMALL_ASM() (*addr));
}
/*
* Sets all the masked bits to '1'
*/
static inline void set_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set arch=r4000 \n"
"1: ll %0, %1 # set_reg32 \n"
" or %0, %2 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
: "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
}
/*
* Sets all the masked bits to '0'
*/
static inline void clear_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set arch=r4000 \n"
"1: ll %0, %1 # clear_reg32 \n"
" and %0, %2 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
: "ir" (~mask), GCC_OFF_SMALL_ASM() (*addr));
}
/*
* Toggles all masked bits from '0' to '1' and '1' to '0'
*/
static inline void toggle_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set arch=r4000 \n"
"1: ll %0, %1 # toggle_reg32 \n"
" xor %0, %2 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
: "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
}
/*
* Read all masked bits others are returned as '0'
*/
static inline u32 read_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" lw %0, %1 # read \n"
" and %0, %2 # mask \n"
" .set pop \n"
: "=&r" (temp)
: "m" (*addr), "ir" (mask));
return temp;
}
/*
* blocking_read_reg32 - Read address with blocking load
*
* Uncached writes need to be read back to ensure they reach RAM.
* The returned value must be 'used' to prevent from becoming a
* non-blocking load.
*/
static inline u32 blocking_read_reg32(volatile u32 *const addr)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" lw %0, %1 # read \n"
" move %0, %0 # block \n"
" .set pop \n"
: "=&r" (temp)
: "m" (*addr));
return temp;
}
/*
* For special strange cases only:
*
* If you need custom processing within a ll/sc loop, use the following macros
* VERY CAREFULLY:
*
* u32 tmp; <-- Define a variable to hold the data
*
* custom_read_reg32(address, tmp); <-- Reads the address and put the value
* in the 'tmp' variable given
*
* From here on out, you are (basically) atomic, so don't do anything too
* fancy!
* Also, this code may loop if the end of this block fails to write
* everything back safely due do the other CPU, so do NOT do anything
* with side-effects!
*
* custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely.
*/
#define custom_read_reg32(address, tmp) \
__asm__ __volatile__( \
" .set push \n" \
" .set arch=r4000 \n" \
"1: ll %0, %1 #custom_read_reg32 \n" \
" .set pop \n" \
: "=r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
: GCC_OFF_SMALL_ASM() (*address))
#define custom_write_reg32(address, tmp) \
__asm__ __volatile__( \
" .set push \n" \
" .set arch=r4000 \n" \
" sc %0, %1 #custom_write_reg32 \n" \
" "__beqz"%0, 1b \n" \
" nop \n" \
" .set pop \n" \
: "=&r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
: "0" (tmp), GCC_OFF_SMALL_ASM() (*address))
#endif /* __ASM_REGOPS_H__ */

652
arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h
Просмотреть файл

@@ -1,652 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the address space, registers and register configuration
* (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
* This file contains addess maps for all the devices in the line of
* products but only has register definitions and configuration masks for
* registers which aren't definitely associated with any device. Things
* like clock settings, reset access, the ELB etc. Individual device
* drivers will reference the appropriate XXX_BASE value defined here
* and have individual registers offset from that.
*
* Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved.
* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
*
* ########################################################################
*
* ########################################################################
*/
#include <asm/addrspace.h>
#include <linux/types.h>
#ifndef _ASM_MSP_REGS_H
#define _ASM_MSP_REGS_H
/*
########################################################################
# Address space and device base definitions #
########################################################################
*/
/*
***************************************************************************
* System Logic and Peripherals (ELB, UART0, etc) device address space *
***************************************************************************
*/
#define MSP_SLP_BASE 0x1c000000
/* System Logic and Peripherals */
#define MSP_RST_BASE (MSP_SLP_BASE + 0x10)
/* System reset register base */
#define MSP_RST_SIZE 0x0C /* System reset register space */
#define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)
/* watchdog timer base */
#define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)
/* internal timer base */
#define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)
/* UART0 controller base */
#define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)
/* Block Copy controller base */
#define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)
/* Block Copy descriptor base */
/*
***************************************************************************
* PCI address space *
***************************************************************************
*/
#define MSP_PCI_BASE 0x19000000
/*
***************************************************************************
* MSbus device address space *
***************************************************************************
*/
#define MSP_MSB_BASE 0x18000000
/* MSbus address start */
#define MSP_PER_BASE (MSP_MSB_BASE + 0x400000)
/* Peripheral device registers */
#define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000)
/* MAC A device registers */
#define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000)
/* MAC B device registers */
#define MSP_MAC_SIZE 0xE0 /* MAC register space */
#define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000)
/* Security Engine registers */
#define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000)
/* MAC C device registers */
#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)
/* ADSL2 device registers */
#define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000)
/* USB0 device registers */
#define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000)
/* USB1 device registers */
#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)
/* CPU interface registers */
/* Devices within the MSbus peripheral block */
#define MSP_UART1_BASE (MSP_PER_BASE + 0x030)
/* UART1 controller base */
#define MSP_SPI_BASE (MSP_PER_BASE + 0x058)
/* SPI/MPI control registers */
#define MSP_TWI_BASE (MSP_PER_BASE + 0x090)
/* Two-wire control registers */
#define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0)
/* Programmable timer control */
/*
***************************************************************************
* Physical Memory configuration address space *
***************************************************************************
*/
#define MSP_MEM_CFG_BASE 0x17f00000
#define MSP_MEM_INDIRECT_CTL_10 0x10
/*
* Notes:
* 1) The SPI registers are split into two blocks, one offset from the
* MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
* 0x68. The SPI driver definitions for the register must be aware
* of this.
* 2) The block copy engine register are divided into two regions, one
* for the control/configuration of the engine proper and one for the
* values of the descriptors used in the copy process. These have
* different base defines (CTRL_BASE vs DESC_BASE)
* 3) These constants are for physical addresses which means that they
* work correctly with "ioremap" and friends. This means that device
* drivers will need to remap these addresses using ioremap and perhaps
* the readw/writew macros. Or they could use the regptr() macro
* defined below, but the readw/writew calls are the correct thing.
* 4) The UARTs have an additional status register offset from the base
* address. This register isn't used in the standard 8250 driver but
* may be used in other software. Consult the hardware datasheet for
* offset details.
* 5) For some unknown reason the security engine (MSP_SEC_BASE) registers
* start at an offset of 0x84 from the base address but the block of
* registers before this is reserved for the security engine. The
* driver will have to be aware of this but it makes the register
* definitions line up better with the documentation.
*/
/*
########################################################################
# System register definitions. Not associated with a specific device #
########################################################################
*/
/*
* This macro maps the physical register number into uncached space
* and (for C code) casts it into a u32 pointer so it can be dereferenced
* Normally these would be accessed with ioremap and readX/writeX, but
* these are convenient for a lot of internal kernel code.
*/
#ifdef __ASSEMBLER__
#define regptr(addr) (KSEG1ADDR(addr))
#else
#define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
#endif
/*
***************************************************************************
* System Logic and Peripherals (RESET, ELB, etc) registers *
***************************************************************************
*/
/* System Control register definitions */
#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)
/* Device-ID RO */
#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)
/* Firmware-ID Register RW */
#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)
/* System-ID Register-0 RW */
#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)
/* System-ID Register-1 RW */
/* System Reset register definitions */
#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10)
/* System Reset Status RO */
#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14)
/* System Set Reset WO */
#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)
/* System Clear Reset WO */
/* System Clock Registers */
#define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)
/* PCI clock generator RW */
#define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)
/* UART clock generator RW */
/* reserved (MSP_SLP_BASE + 0x24) */
/* reserved (MSP_SLP_BASE + 0x28) */
#define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)
/* PLL1 clock generator RW */
#define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)
/* PLL0 clock generator RW */
#define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)
/* MIPS clock generator RW */
#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)
/* Voice Eng clock generator RW */
/* reserved (MSP_SLP_BASE + 0x3C) */
#define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)
/* MS-Bus clock generator RW */
#define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)
/* Sec & MAC clock generator RW */
#define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)
/* Per & TDM clock generator RW */
/* Interrupt Controller Registers */
#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
/* Interrupt status register RW */
#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
/* Interrupt enable/mask RW */
#define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)
/* Security Engine mailbox RW */
#define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)
/* Voice Engine mailbox RW */
/* ELB Controller Registers */
#define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)
/* ELB CS0 Configuration Reg */
#define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)
/* ELB CS0 Base Address Reg */
#define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)
/* ELB CS0 Mask Register */
#define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)
/* ELB CS0 access register */
#define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)
/* ELB CS1 Configuration Reg */
#define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)
/* ELB CS1 Base Address Reg */
#define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)
/* ELB CS1 Mask Register */
#define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)
/* ELB CS1 access register */
#define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)
/* ELB CS2 Configuration Reg */
#define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)
/* ELB CS2 Base Address Reg */
#define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)
/* ELB CS2 Mask Register */
#define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)
/* ELB CS2 access register */
#define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)
/* ELB CS3 Configuration Reg */
#define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)
/* ELB CS3 Base Address Reg */
#define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)
/* ELB CS3 Mask Register */
#define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)
/* ELB CS3 access register */
#define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)
/* ELB CS4 Configuration Reg */
#define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)
/* ELB CS4 Base Address Reg */
#define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)
/* ELB CS4 Mask Register */
#define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)
/* ELB CS4 access register */
#define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)
/* ELB CS5 Configuration Reg */
#define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)
/* ELB CS5 Base Address Reg */
#define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)
/* ELB CS5 Mask Register */
#define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)
/* ELB CS5 access register */
/* reserved 0xE0 - 0xE8 */
#define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)
/* ELB single PC card detect */
/* reserved 0xF0 - 0xF8 */
#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
/* SDRAM read/ELB timing Reg */
/* Extended UART status registers */
#define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0)
/* UART Status Register 0 */
#define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170)
/* UART Status Register 1 */
/* Performance monitoring registers */
#define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)
/* Performance monitor control */
#define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)
/* Performance monitor clear */
#define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)
/* Perf monitor counter high */
#define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)
/* Perf monitor counter low */
/* System control registers */
#define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)
/* System control register */
#define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)
/* System Error status 1 */
#define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)
/* System Error status 2 */
#define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)
/* System Interrupt config */
/* Voice Engine Memory configuration */
#define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)
/* Voice engine memory config */
/* CPU/SLP Error Status registers */
#define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)
/* CPU/SLP Error status 1 */
#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
/* CPU/SLP Error status 1 */
/* Extended GPIO registers */
#define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188)
#define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c)
#define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG
/* Backward-compatibility */
/* System Error registers */
#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
/* Int status for SLP errors */
#define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)
/* Int mask for SLP errors */
#define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)
/* External ELB reset */
#define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)
/* Boot Status */
/* Extended ELB addressing */
#define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)
/* CS0 Extended address */
#define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)
/* CS1 Extended address */
#define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)
/* CS2 Extended address */
#define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)
/* CS3 Extended address */
/* reserved 0x1B0 */
#define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)
/* CS5 Extended address */
/* PLL Adjustment registers */
#define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)
/* PLL0 lock status */
#define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)
/* PLL Analog reset status */
#define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)
/* PLL0 Adjustment value */
#define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)
/* PLL1 Adjustment value */
/*
***************************************************************************
* Peripheral Register definitions *
***************************************************************************
*/
/* Peripheral status */
#define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50)
/* Peripheral control register */
#define PER_STS_REG regptr(MSP_PER_BASE + 0x54)
/* Peripheral status register */
/* SPI/MPI Registers */
#define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58)
/* SPI/MPI Tx Size register */
#define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C)
/* SPI/MPI Rx Size register */
#define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60)
/* SPI/MPI Control register */
#define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64)
/* SPI/MPI Chip Select reg */
#define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0)
/* SPI/MPI Core Data reg */
#define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4)
/* SPI/MPI Core Control reg */
#define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8)
/* SPI/MPI Core Status reg */
#define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC)
/* SPI/MPI Core Ssel reg */
#define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0)
/* SPI/MPI Data FIFO reg */
/* Peripheral Block Error Registers */
#define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70)
/* Error Bit Status Register */
#define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74)
/* Error Bit Mask Register */
#define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78)
/* Error Header 1 Register */
#define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C)
/* Error Header 2 Register */
/* Peripheral Block Interrupt Registers */
#define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80)
/* Interrupt status register */
#define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84)
/* Interrupt Mask Register */
#define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88)
/* GPIO interrupt status reg */
#define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C)
/* GPIO interrupt MASK Reg */
/* POLO GPIO registers */
#define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0)
/* Polo GPIO[8:0] data reg */
#define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4)
/* Polo GPIO[7:0] config reg */
#define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8)
/* Polo GPIO[15:8] config reg */
#define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC)
/* Polo GPIO[31:0] output drive */
#define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170)
/* Polo GPIO[23:16] config reg */
#define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174)
/* Polo GPIO[15:9] data reg */
#define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178)
/* Polo GPIO[23:16] data reg */
#define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C)
/* Polo GPIO[31:24] data reg */
#define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180)
/* Polo GPIO[39:32] data reg */
#define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184)
/* Polo GPIO[47:40] data reg */
#define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188)
/* Polo GPIO[54:48] data reg */
#define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
/* Polo GPIO[31:24] config reg */
#define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190)
/* Polo GPIO[39:32] config reg */
#define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194)
/* Polo GPIO[47:40] config reg */
#define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198)
/* Polo GPIO[54:48] config reg */
#define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C)
/* Polo GPIO[54:32] output drive */
/* Generic GPIO registers */
#define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170)
/* GPIO[1:0] data register */
#define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174)
/* GPIO[5:2] data register */
#define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178)
/* GPIO[9:6] data register */
#define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C)
/* GPIO[15:10] data register */
#define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180)
/* GPIO[1:0] config register */
#define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184)
/* GPIO[5:2] config register */
#define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188)
/* GPIO[9:6] config register */
#define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
/* GPIO[15:10] config register */
#define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190)
/* GPIO[15:0] output drive */
/*
***************************************************************************
* CPU Interface register definitions *
***************************************************************************
*/
#define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00)
/* PCI-SDRAM queue flush trigger */
#define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04)
/* OCP Error Attribute 1 */
#define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08)
/* OCP Error Attribute 2 */
#define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C)
/* OCP Error Status */
#define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10)
/* CPU policy configuration */
#define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10)
/* Misc configuration options */
/* Central Interrupt Controller Registers */
#define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000)
/* Central Interrupt registers */
#define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00)
/* External interrupt config */
#define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04)
/* CIC Interrupt Status */
#define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08)
/* VPE0 Interrupt Mask */
#define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C)
/* VPE1 Interrupt Mask */
#define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10)
/* Thread Context 0 Int Mask */
#define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14)
/* Thread Context 1 Int Mask */
#define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18)
/* Thread Context 2 Int Mask */
#define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18)
/* Thread Context 3 Int Mask */
#define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18)
/* Thread Context 4 Int Mask */
#define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18)
#define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18)
#define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18)
#define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08)
/*
***************************************************************************
* Memory controller registers *
***************************************************************************
*/
#define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00)
#define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00)
#define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04)
#define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08)
/*
***************************************************************************
* PCI controller registers *
***************************************************************************
*/
#define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00)
#define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800)
#define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)
/*
########################################################################
# Register content & macro definitions #
########################################################################
*/
/*
***************************************************************************
* DEV_ID defines *
***************************************************************************
*/
#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */
#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */
#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */
#define DEV_ID_FAMILY (0xff << 8) /* family ID code */
#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */
#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */
#define MSP5000_ID (0x50 << 8)
#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */
#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */
#define MSP4200_ID (0x42 << 8)
#define MSP4000_ID (0x40 << 8)
#define MSP2XXX_ID (0x20 << 8)
#define MSPZEUS_ID (0x10 << 8)
#define MSP2004_SUB_ID (0x0 << 16)
#define MSP2005_SUB_ID (0x1 << 16)
#define MSP2006_SUB_ID (0x1 << 16)
#define MSP2007_SUB_ID (0x2 << 16)
#define MSP2010_SUB_ID (0x3 << 16)
#define MSP2015_SUB_ID (0x4 << 16)
#define MSP2020_SUB_ID (0x5 << 16)
#define MSP2100_SUB_ID (0x6 << 16)
/*
***************************************************************************
* RESET defines *
***************************************************************************
*/
#define MSP_GR_RST (0x01 << 0) /* Global reset bit */
#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */
#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */
#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */
/* reserved */
#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */
#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */
#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */
#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */
#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */
#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */
#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */
#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */
#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */
/*
***************************************************************************
* UART defines *
***************************************************************************
*/
#define MSP_BASE_BAUD 25000000
#define MSP_UART_REG_LEN 0x20
/*
***************************************************************************
* ELB defines *
***************************************************************************
*/
#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */
#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */
/*
***************************************************************************
* CIC defines *
***************************************************************************
*/
/* CIC_EXT_CFG_REG */
#define EXT_INT_POL(eirq) (1 << (eirq + 8))
#define EXT_INT_EDGE(eirq) (1 << eirq)
#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq))
#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq))
#define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq))
#define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq))
#define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI
#define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO
#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
((reg & EXT_INT_EDGE(eirq)) == 0)
#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq))
#define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq))
#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
((reg & EXT_INT_POL(eirq)) == 0)
#define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI
#define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO
/*
***************************************************************************
* Memory Controller defines *
***************************************************************************
*/
/* Indirect memory controller registers */
#define DDRC_CFG(n) (n)
#define DDRC_DEBUG(n) (0x04 + n)
#define DDRC_CTL(n) (0x40 + n)
/* Macro to perform DDRC indirect write */
#define DDRC_INDIRECT_WRITE(reg, mask, value) \
({ \
*MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
*MEM_SS_DATA = (value); \
*MEM_SS_WRITE = 1; \
})
/*
***************************************************************************
* SPI/MPI Mode *
***************************************************************************
*/
#define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */
#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */
#define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */
#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */
/*
***************************************************************************
* SPI/MPI Control Register *
***************************************************************************
*/
#define SPI_MPI_RX_START 0x00000004 /* Start receive command */
#define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */
#define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */
#endif /* !_ASM_MSP_REGS_H */

129
arch/mips/include/asm/mach-pmcs-msp71xx/msp_slp_int.h
Просмотреть файл

@@ -1,129 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the MSP interrupt controller.
*
* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
* Author: Carsten Langgaard, carstenl@mips.com
*
* ########################################################################
*
* ########################################################################
*/
#ifndef _MSP_SLP_INT_H
#define _MSP_SLP_INT_H
/*
* The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
* hierarchical system. The first level are the direct MIPS interrupts
* and are assigned the interrupt range 0-7. The second level is the SLM
* interrupt controller and is assigned the range 8-39. The third level
* comprises the Peripherial block, the PCI block, the PCI MSI block and
* the SLP. The PCI interrupts and the SLP errors are handled by the
* relevant subsystems so the core interrupt code needs only concern
* itself with the Peripheral block. These are assigned interrupts in
* the range 40-71.
*/
/*
* IRQs directly connected to CPU
*/
#define MSP_MIPS_INTBASE 0
#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */
#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */
#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */
#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */
/*
* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
* These defines should be tied to the register definition for the SLM
* interrupt routine. For now, just use hard-coded values.
*/
#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)
#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)
/* External interrupt 0 */
#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)
/* External interrupt 1 */
#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)
/* External interrupt 2 */
#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)
/* External interrupt 3 */
/* Reserved 4-7 */
/*
*************************************************************************
* DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
* Some MSP produces have this interrupt labelled as Voice and some are *
* SEC mbox ... *
*************************************************************************
*/
#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)
/* Cascaded IRQ for Voice Engine*/
#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)
/* TDM interrupt */
#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)
/* Cascaded IRQ for MAC 0 */
#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)
/* Cascaded IRQ for MAC 1 */
#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)
/* IRQ for security engine */
#define MSP_INT_PER (MSP_SLP_INTBASE + 13)
/* Peripheral interrupt */
#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)
/* SLP timer 0 */
#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)
/* SLP timer 1 */
#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)
/* SLP timer 2 */
#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)
/* Cascaded MIPS timer */
#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)
/* Block Copy */
#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)
/* UART 0 */
#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)
/* PCI subsystem */
#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)
/* PCI doorbell */
#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)
/* PCI Message Signal */
#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)
/* PCI Block Copy 0 */
#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)
/* PCI Block Copy 1 */
#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)
/* SLP error condition */
#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)
/* IRQ for MAC2 */
/* Reserved 26-31 */
/*
* IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
*/
#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)
/* Reserved 0-1 */
#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
/* UART 1 */
/* Reserved 3-5 */
#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
/* 2-wire */
#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
/* Peripheral timer block out 0 */
#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
/* Peripheral timer block out 1 */
/* Reserved 9 */
#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
/* SPI RX complete */
#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
/* SPI TX complete */
#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
/* GPIO */
#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
/* Peripheral error */
/* Reserved 14-31 */
#endif /* !_MSP_SLP_INT_H */

124
arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h
Просмотреть файл

@@ -1,124 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/******************************************************************
* Copyright (c) 2000-2007 PMC-Sierra INC.
*
* PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
* SOFTWARE.
*/
#ifndef MSP_USB_H_
#define MSP_USB_H_
#define NUM_USB_DEVS 1
/* Register spaces for USB host 0 */
#define MSP_USB0_MAB_START (MSP_USB0_BASE + 0x0)
#define MSP_USB0_MAB_END (MSP_USB0_BASE + 0x17)
#define MSP_USB0_ID_START (MSP_USB0_BASE + 0x40000)
#define MSP_USB0_ID_END (MSP_USB0_BASE + 0x4008f)
#define MSP_USB0_HS_START (MSP_USB0_BASE + 0x40100)
#define MSP_USB0_HS_END (MSP_USB0_BASE + 0x401FF)
/* Register spaces for USB host 1 */
#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0)
#define MSP_USB1_MAB_END (MSP_USB1_BASE + 0x17)
#define MSP_USB1_ID_START (MSP_USB1_BASE + 0x40000)
#define MSP_USB1_ID_END (MSP_USB1_BASE + 0x4008f)
#define MSP_USB1_HS_START (MSP_USB1_BASE + 0x40100)
#define MSP_USB1_HS_END (MSP_USB1_BASE + 0x401ff)
/* USB Identification registers */
struct msp_usbid_regs {
u32 id; /* 0x0: Identification register */
u32 hwgen; /* 0x4: General HW params */
u32 hwhost; /* 0x8: Host HW params */
u32 hwdev; /* 0xc: Device HW params */
u32 hwtxbuf; /* 0x10: Tx buffer HW params */
u32 hwrxbuf; /* 0x14: Rx buffer HW params */
u32 reserved[26];
u32 timer0_load; /* 0x80: General-purpose timer 0 load*/
u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
u32 timer1_load; /* 0x88: General-purpose timer 1 load*/
u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */
};
/* MSBus to AMBA registers */
struct msp_mab_regs {
u32 isr; /* 0x0: Interrupt status */
u32 imr; /* 0x4: Interrupt mask */
u32 thcr0; /* 0x8: Transaction header capture 0 */
u32 thcr1; /* 0xc: Transaction header capture 1 */
u32 int_stat; /* 0x10: Interrupt status summary */
u32 phy_cfg; /* 0x14: USB phy config */
};
/* EHCI registers */
struct msp_usbhs_regs {
u32 hciver; /* 0x0: Version and offset to operational regs */
u32 hcsparams; /* 0x4: Host control structural parameters */
u32 hccparams; /* 0x8: Host control capability parameters */
u32 reserved0[5];
u32 dciver; /* 0x20: Device interface version */
u32 dccparams; /* 0x24: Device control capability parameters */
u32 reserved1[6];
u32 cmd; /* 0x40: USB command */
u32 sts; /* 0x44: USB status */
u32 int_ena; /* 0x48: USB interrupt enable */
u32 frindex; /* 0x4c: Frame index */
u32 reserved3;
union {
struct {
u32 flb_addr; /* 0x54: Frame list base address */
u32 next_async_addr; /* 0x58: next asynchronous addr */
u32 ttctrl; /* 0x5c: embedded transaction translator
async buffer status */
u32 burst_size; /* 0x60: Controller burst size */
u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */
u32 reserved0[4];
u32 endpt_nak; /* 0x78: Endpoint NAK */
u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */
u32 cfg_flag; /* 0x80: Config flag */
u32 port_sc1; /* 0x84: Port status & control 1 */
u32 reserved1[7];
u32 otgsc; /* 0xa4: OTG status & control */
u32 mode; /* 0xa8: USB controller mode */
} host;
struct {
u32 dev_addr; /* 0x54: Device address */
u32 endpt_list_addr; /* 0x58: Endpoint list address */
u32 reserved0[7];
u32 endpt_nak; /* 0x74 */
u32 endpt_nak_ctrl; /* 0x78 */
u32 cfg_flag; /* 0x80 */
u32 port_sc1; /* 0x84: Port status & control 1 */
u32 reserved[7];
u32 otgsc; /* 0xa4: OTG status & control */
u32 mode; /* 0xa8: USB controller mode */
u32 endpt_setup_stat; /* 0xac */
u32 endpt_prime; /* 0xb0 */
u32 endpt_flush; /* 0xb4 */
u32 endpt_stat; /* 0xb8 */
u32 endpt_complete; /* 0xbc */
u32 endpt_ctrl0; /* 0xc0 */
u32 endpt_ctrl1; /* 0xc4 */
u32 endpt_ctrl2; /* 0xc8 */
u32 endpt_ctrl3; /* 0xcc */
} device;
} u;
};
/*
* Container for the more-generic platform_device.
* This exists mainly as a way to map the non-standard register
* spaces and make them accessible to the USB ISR.
*/
struct mspusb_device {
struct msp_mab_regs __iomem *mab_regs;
struct msp_usbid_regs __iomem *usbid_regs;
struct msp_usbhs_regs __iomem *usbhs_regs;
struct platform_device dev;
};
#define to_mspusb_device(x) container_of((x), struct mspusb_device, dev)
#define TO_HOST_ID(x) ((x) & 0x3)
#endif /*MSP_USB_H_*/

28
arch/mips/include/asm/mach-pmcs-msp71xx/war.h
Просмотреть файл

@@ -1,28 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
#define __ASM_MIPS_PMC_SIERRA_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
defined(CONFIG_PMC_MSP7120_FPGA)
#define MIPS34K_MISSED_ITLB_WAR 1
#else
#define MIPS34K_MISSED_ITLB_WAR 0
#endif
#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */

1
arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
Просмотреть файл

@@ -45,7 +45,6 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32

2
arch/mips/include/asm/mach-ralink/mt7621.h
Просмотреть файл

@@ -31,6 +31,4 @@
#define MT7621_CHIP_NAME0 0x3637544D
#define MT7621_CHIP_NAME1 0x20203132
#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
#endif

1
arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
Просмотреть файл

@@ -46,7 +46,6 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32

1
arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
Просмотреть файл

@@ -44,7 +44,6 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 16
#define cpu_icache_line_size() 16

1
arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
Просмотреть файл

@@ -44,7 +44,6 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32

1
arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
Просмотреть файл

@@ -43,7 +43,6 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32

1
arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
Просмотреть файл

@@ -54,7 +54,6 @@
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_has_inclusive_pcaches 0

3
arch/mips/include/asm/mach-rc32434/pci.h
Просмотреть файл

@@ -319,9 +319,6 @@ struct pci_msu {
#define PCIM_H_EA 0x3
#define PCIM_H_IA_FIX 0x4
#define PCIM_H_IA_RR 0x5
#if 0
#define PCI_ADDR_START 0x13000000
#endif
#define PCI_ADDR_START 0x50000000

9
arch/mips/include/asm/mach-tx39xx/ioremap.h
Просмотреть файл

@@ -7,15 +7,6 @@
#include <linux/types.h>
/*
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{

9
arch/mips/include/asm/mach-tx49xx/ioremap.h
Просмотреть файл

@@ -7,15 +7,6 @@
#include <linux/types.h>
/*
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{

14
arch/mips/include/asm/mach-xilfpga/irq.h
Просмотреть файл

@@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Imagination Technologies
* Author: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
*/
#ifndef __MIPS_ASM_MACH_XILFPGA_IRQ_H__
#define __MIPS_ASM_MACH_XILFPGA_IRQ_H__
#define NR_IRQS 32
#include <asm/mach-generic/irq.h>
#endif /* __MIPS_ASM_MACH_XILFPGA_IRQ_H__ */

61
arch/mips/include/asm/mipsregs.h
Просмотреть файл

@@ -468,6 +468,7 @@
#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
#define EXCCODE_CACHEERR 30 /* Parity/ECC occured on a core */
/* Implementation specific trap codes used by MIPS cores */
#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
@@ -563,6 +564,17 @@
#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
#define MIPS_CONF_BE (_ULCAST_(1) << 15)
#define MIPS_CONF_BM (_ULCAST_(1) << 16)
#define MIPS_CONF_MM (_ULCAST_(3) << 17)
#define MIPS_CONF_MM_SYSAD (_ULCAST_(1) << 17)
#define MIPS_CONF_MM_FULL (_ULCAST_(2) << 17)
#define MIPS_CONF_SB (_ULCAST_(1) << 21)
#define MIPS_CONF_UDI (_ULCAST_(1) << 22)
#define MIPS_CONF_DSP (_ULCAST_(1) << 23)
#define MIPS_CONF_ISP (_ULCAST_(1) << 24)
#define MIPS_CONF_KU (_ULCAST_(3) << 25)
#define MIPS_CONF_K23 (_ULCAST_(3) << 28)
#define MIPS_CONF_M (_ULCAST_(1) << 31)
/*
@@ -674,13 +686,38 @@
#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
#define MIPS_CONF5_K (_ULCAST_(1) << 30)
#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
/* Config6 feature bits for proAptiv/P5600 */
/* Jump register cache prediction disable */
#define MIPS_CONF6_MTI_JRCD (_ULCAST_(1) << 0)
/* MIPSr6 extensions enable */
#define MIPS_CONF6_MTI_R6 (_ULCAST_(1) << 2)
/* IFU Performance Control */
#define MIPS_CONF6_MTI_IFUPERFCTL (_ULCAST_(3) << 10)
#define MIPS_CONF6_MTI_SYND (_ULCAST_(1) << 13)
/* Sleep state performance counter disable */
#define MIPS_CONF6_MTI_SPCD (_ULCAST_(1) << 14)
/* proAptiv FTLB on/off bit */
#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
/* Loongson-3 FTLB on/off bit */
#define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
#define MIPS_CONF6_MTI_FTLBEN (_ULCAST_(1) << 15)
/* Disable load/store bonding */
#define MIPS_CONF6_MTI_DLSB (_ULCAST_(1) << 21)
/* FTLB probability bits */
#define MIPS_CONF6_FTLBP_SHIFT (16)
#define MIPS_CONF6_MTI_FTLBP_SHIFT (16)
/* Config6 feature bits for Loongson-3 */
/* Loongson-3 internal timer bit */
#define MIPS_CONF6_LOONGSON_INTIMER (_ULCAST_(1) << 6)
/* Loongson-3 external timer bit */
#define MIPS_CONF6_LOONGSON_EXTIMER (_ULCAST_(1) << 7)
/* Loongson-3 SFB on/off bit, STFill in manual */
#define MIPS_CONF6_LOONGSON_SFBEN (_ULCAST_(1) << 8)
/* Loongson-3's LL on exclusive cacheline */
#define MIPS_CONF6_LOONGSON_LLEXC (_ULCAST_(1) << 16)
/* Loongson-3's SC has a random delay */
#define MIPS_CONF6_LOONGSON_SCRAND (_ULCAST_(1) << 17)
/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
#define MIPS_CONF6_LOONGSON_FTLBDIS (_ULCAST_(1) << 22)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
@@ -753,10 +790,18 @@
/* MAAR bit definitions */
#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
#define MIPS_MAAR_ADDR GENMASK_ULL(55, 12)
#define MIPS_MAAR_ADDR_SHIFT 12
#define MIPS_MAAR_S (_ULCAST_(1) << 1)
#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
#ifdef CONFIG_XPA
#define MIPS_MAAR_V (MIPS_MAAR_VH | MIPS_MAAR_VL)
#else
#define MIPS_MAAR_V MIPS_MAAR_VL
#endif
#define MIPS_MAARX_VH (_ULCAST_(1) << 31)
#define MIPS_MAARX_ADDR 0xF
#define MIPS_MAARX_ADDR_SHIFT 32
/* MAARI bit definitions */
#define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
@@ -997,6 +1042,8 @@
#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
/* Flush DTLB */
#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
/* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
#define LOONGSON_DIAG_UCAC (_ULCAST_(1) << 8)
/* Flush VTLB */
#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
/* Flush FTLB */
@@ -1717,6 +1764,8 @@ do { \
#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
#define read_c0_maar() __read_ulong_c0_register($17, 1)
#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
#define readx_c0_maar() __readx_32bit_c0_register($17, 1)
#define writex_c0_maar(val) __writex_32bit_c0_register($17, 1, val)
#define read_c0_maari() __read_32bit_c0_register($17, 2)
#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)

310
arch/mips/include/asm/nile4.h
Просмотреть файл

@@ -1,310 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@linux-m68k.org>
* Sony Software Development Center Europe (SDCE), Brussels
*
* This file is based on the following documentation:
*
* NEC Vrc 5074 System Controller Data Sheet, June 1998
*/
#ifndef _ASM_NILE4_H
#define _ASM_NILE4_H
#define NILE4_BASE 0xbfa00000
#define NILE4_SIZE 0x00200000 /* 2 MB */
/*
* Physical Device Address Registers (PDARs)
*/
#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */
/* [R/W] */
#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
/*
* CPU Interface Registers
*/
#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */
#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */
#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
/* Enable [R/W] */
#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
/*
* Memory-Interface Registers
*/
#define NILE4_MEMCTRL 0x00C0 /* Memory Control */
#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */
/*
* PCI-Bus Registers
*/
#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */
#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */
/*
* Local-Bus Registers
*/
#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
/* Enables [R/W] */
#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
/*
* DMA Registers
*/
#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
/*
* Timer Registers
*/
#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
/*
* PCI Configuration Space Registers
*/
#define NILE4_PCI_BASE 0x0200
#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */
#define NILE4_DID 0x0202 /* PCI Device ID [R] */
#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */
#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */
#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */
#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */
#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */
#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */
#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */
#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
/* (unimplemented) */
#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */
#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */
/* (unimplemented) */
#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */
#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
/*
* Serial-Port Registers
*/
#define NILE4_UART_BASE 0x0300
#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */
#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */
#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */
#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */
#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */
#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */
#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */
#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */
#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */
#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */
#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */
#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */
#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */
/*
* Interrupt Lines
*/
#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */
#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */
#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */
#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */
#define NILE4_INT_UART 4 /* UART Interrupt */
#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */
#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */
#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */
#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */
#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */
#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */
#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */
#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */
#define NILE4_INT_RESV 13 /* Reserved */
#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */
#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */
/*
* Nile 4 Register Access
*/
static inline void nile4_sync(void)
{
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
}
static inline void nile4_out32(u32 offset, u32 val)
{
*(volatile u32 *)(NILE4_BASE+offset) = val;
nile4_sync();
}
static inline u32 nile4_in32(u32 offset)
{
u32 val = *(volatile u32 *)(NILE4_BASE+offset);
nile4_sync();
return val;
}
static inline void nile4_out16(u32 offset, u16 val)
{
*(volatile u16 *)(NILE4_BASE+offset) = val;
nile4_sync();
}
static inline u16 nile4_in16(u32 offset)
{
u16 val = *(volatile u16 *)(NILE4_BASE+offset);
nile4_sync();
return val;
}
static inline void nile4_out8(u32 offset, u8 val)
{
*(volatile u8 *)(NILE4_BASE+offset) = val;
nile4_sync();
}
static inline u8 nile4_in8(u32 offset)
{
u8 val = *(volatile u8 *)(NILE4_BASE+offset);
nile4_sync();
return val;
}
/*
* Physical Device Address Registers
*/
extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
int on_memory_bus, int visible);
/*
* PCI Master Registers
*/
#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
#define NILE4_PCICMD_IO 1 /* PCI I/O Space */
#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */
#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */
/*
* PCI Address Spaces
*
* Note that these are multiplexed using PCIINIT[01]!
*/
#define NILE4_PCI_IO_BASE 0xa6000000
#define NILE4_PCI_MEM_BASE 0xa8000000
#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE
extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
/*
* Interrupt Programming
*/
#define NUM_I8259_INTERRUPTS 16
#define NUM_NILE4_INTERRUPTS 16
#define IRQ_I8259_CASCADE NILE4_INT_INTE
#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS)
#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS)
#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS)
extern void nile4_map_irq(int nile4_irq, int cpu_irq);
extern void nile4_map_irq_all(int cpu_irq);
extern void nile4_enable_irq(unsigned int nile4_irq);
extern void nile4_disable_irq(unsigned int nile4_irq);
extern void nile4_disable_irq_all(void);
extern u16 nile4_get_irq_stat(int cpu_irq);
extern void nile4_enable_irq_output(int cpu_irq);
extern void nile4_disable_irq_output(int cpu_irq);
extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
extern void nile4_clear_irq(int nile4_irq);
extern void nile4_clear_irq_mask(u32 mask);
extern u8 nile4_i8259_iack(void);
extern void nile4_dump_irq_status(void); /* Debug */
#endif

2
arch/mips/include/asm/octeon/cvmx-sli-defs.h
Просмотреть файл

@@ -46,7 +46,7 @@ static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
return 0x0000000000003CB0ull;
/* Else, fall through */
fallthrough;
default:
return 0x0000000000023CB0ull;
}

2
arch/mips/include/asm/page.h
Просмотреть файл

@@ -49,7 +49,7 @@ static inline unsigned int page_size_ftlb(unsigned int mmuextdef)
return 6;
if (PAGE_SIZE > (256 << 10))
return 7; /* reserved */
/* fall through */
fallthrough;
case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
return (PAGE_SHIFT - 10) / 2;
default:

4
arch/mips/include/asm/pgtable-64.h
Просмотреть файл

@@ -172,6 +172,8 @@
extern pte_t invalid_pte_table[PTRS_PER_PTE];
#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
#ifndef __PAGETABLE_PUD_FOLDED
/*
* For 4-level pagetables we defines these ourselves, for 3-level the
@@ -210,8 +212,6 @@ static inline void p4d_clear(p4d_t *p4dp)
p4d_val(*p4dp) = (unsigned long)invalid_pud_table;
}
#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
static inline unsigned long p4d_page_vaddr(p4d_t p4d)
{
return p4d_val(p4d);

20
arch/mips/include/asm/pgtable-bits.h
Просмотреть файл

@@ -55,6 +55,9 @@ enum pgtable_bits {
#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
#endif
#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
_PAGE_SOFT_DIRTY_SHIFT,
#endif
};
/*
@@ -84,6 +87,9 @@ enum pgtable_bits {
#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
#endif
#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
_PAGE_SOFT_DIRTY_SHIFT,
#endif
};
#elif defined(CONFIG_CPU_R3K_TLB)
@@ -99,6 +105,9 @@ enum pgtable_bits {
#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
#endif
#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
_PAGE_SOFT_DIRTY_SHIFT,
#endif
/* Used by TLB hardware (placed in EntryLo) */
_PAGE_GLOBAL_SHIFT = 8,
@@ -125,7 +134,9 @@ enum pgtable_bits {
#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
#endif
#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
_PAGE_SOFT_DIRTY_SHIFT,
#endif
/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_CPU_HAS_RIXI)
_PAGE_NO_EXEC_SHIFT,
@@ -152,6 +163,11 @@ enum pgtable_bits {
#else
# define _PAGE_SPECIAL 0
#endif
#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
# define _PAGE_SOFT_DIRTY (1 << _PAGE_SOFT_DIRTY_SHIFT)
#else
# define _PAGE_SOFT_DIRTY 0
#endif
/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_XPA)
@@ -269,6 +285,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
_PFN_MASK | _CACHE_MASK)
_PAGE_SOFT_DIRTY | _PFN_MASK | _CACHE_MASK)
#endif /* _ASM_PGTABLE_BITS_H */

108
arch/mips/include/asm/pgtable.h
Просмотреть файл

@@ -400,7 +400,7 @@ static inline pte_t pte_mkwrite(pte_t pte)
static inline pte_t pte_mkdirty(pte_t pte)
{
pte_val(pte) |= _PAGE_MODIFIED;
pte_val(pte) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
if (pte_val(pte) & _PAGE_WRITE)
pte_val(pte) |= _PAGE_SILENT_WRITE;
return pte;
@@ -414,6 +414,8 @@ static inline pte_t pte_mkyoung(pte_t pte)
return pte;
}
#define pte_sw_mkyoung pte_mkyoung
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
@@ -423,6 +425,30 @@ static inline pte_t pte_mkhuge(pte_t pte)
return pte;
}
#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
static inline bool pte_soft_dirty(pte_t pte)
{
return pte_val(pte) & _PAGE_SOFT_DIRTY;
}
#define pte_swp_soft_dirty pte_soft_dirty
static inline pte_t pte_mksoft_dirty(pte_t pte)
{
pte_val(pte) |= _PAGE_SOFT_DIRTY;
return pte;
}
#define pte_swp_mksoft_dirty pte_mksoft_dirty
static inline pte_t pte_clear_soft_dirty(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_SOFT_DIRTY);
return pte;
}
#define pte_swp_clear_soft_dirty pte_clear_soft_dirty
#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
#endif
/*
@@ -454,6 +480,31 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
return __pgprot(prot);
}
static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma,
unsigned long address)
{
}
#define __HAVE_ARCH_PTE_SAME
static inline int pte_same(pte_t pte_a, pte_t pte_b)
{
return pte_val(pte_a) == pte_val(pte_b);
}
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
static inline int ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long address, pte_t *ptep,
pte_t entry, int dirty)
{
if (!pte_same(*ptep, entry))
set_pte_at(vma->vm_mm, address, ptep, entry);
/*
* update_mmu_cache will unconditionally execute, handling both
* the case that the PTE changed and the spurious fault case.
*/
return true;
}
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
@@ -481,8 +532,11 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
#else
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
return __pte((pte_val(pte) & _PAGE_CHG_MASK) |
(pgprot_val(newprot) & ~_PAGE_CHG_MASK));
pte_val(pte) &= _PAGE_CHG_MASK;
pte_val(pte) |= pgprot_val(newprot) & ~_PAGE_CHG_MASK;
if ((pte_val(pte) & _PAGE_ACCESSED) && !(pte_val(pte) & _PAGE_NO_READ))
pte_val(pte) |= _PAGE_SILENT_READ;
return pte;
}
#endif
@@ -497,6 +551,9 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
__update_tlb(vma, address, pte);
}
#define __HAVE_ARCH_UPDATE_MMU_TLB
#define update_mmu_tlb update_mmu_cache
static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
unsigned long address, pmd_t *pmdp)
{
@@ -507,20 +564,17 @@ static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
#define kern_addr_valid(addr) (1)
#ifdef CONFIG_PHYS_ADDR_T_64BIT
extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
static inline int io_remap_pfn_range(struct vm_area_struct *vma,
unsigned long vaddr,
unsigned long pfn,
unsigned long size,
pgprot_t prot)
{
phys_addr_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
}
/*
* Allow physical addresses to be fixed up to help 36-bit peripherals.
*/
#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size);
int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
unsigned long pfn, unsigned long size, pgprot_t prot);
#define io_remap_pfn_range io_remap_pfn_range
#endif
#else
#define fixup_bigphys_addr(addr, size) (addr)
#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
@@ -579,7 +633,7 @@ static inline pmd_t pmd_mkclean(pmd_t pmd)
static inline pmd_t pmd_mkdirty(pmd_t pmd)
{
pmd_val(pmd) |= _PAGE_MODIFIED;
pmd_val(pmd) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
if (pmd_val(pmd) & _PAGE_WRITE)
pmd_val(pmd) |= _PAGE_SILENT_WRITE;
@@ -608,6 +662,26 @@ static inline pmd_t pmd_mkyoung(pmd_t pmd)
return pmd;
}
#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
static inline int pmd_soft_dirty(pmd_t pmd)
{
return !!(pmd_val(pmd) & _PAGE_SOFT_DIRTY);
}
static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
{
pmd_val(pmd) |= _PAGE_SOFT_DIRTY;
return pmd;
}
static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
{
pmd_val(pmd) &= ~(_PAGE_SOFT_DIRTY);
return pmd;
}
#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
/* Extern to avoid header file madness */
extern pmd_t mk_pmd(struct page *page, pgprot_t prot);

2
arch/mips/include/asm/smp.h
Просмотреть файл

@@ -125,7 +125,7 @@ static inline void arch_send_call_function_single_ipi(int cpu)
{
extern const struct plat_smp_ops *mp_ops; /* private */
mp_ops->send_ipi_mask(cpumask_of(cpu), SMP_CALL_FUNCTION);
mp_ops->send_ipi_single(cpu, SMP_CALL_FUNCTION);
}
static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)

2
arch/mips/include/asm/stackframe.h
Просмотреть файл

@@ -424,7 +424,7 @@
.macro RESTORE_SP_AND_RET docfi=0
RESTORE_SP \docfi
#ifdef CONFIG_CPU_MIPSR6
#if defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
eretnc
#else
.set push

8
arch/mips/include/asm/switch_to.h
Просмотреть файл

@@ -67,11 +67,11 @@ do { \
#endif
/*
* Clear LLBit during context switches on MIPSr6 such that eretnc can be used
* Clear LLBit during context switches on MIPSr5+ such that eretnc can be used
* unconditionally when returning to userland in entry.S.
*/
#define __clear_r6_hw_ll_bit() do { \
if (cpu_has_mips_r6) \
#define __clear_r5_hw_ll_bit() do { \
if (cpu_has_mips_r5 || cpu_has_mips_r6) \
write_c0_lladdr(0); \
} while (0)
@@ -129,7 +129,7 @@ do { \
} \
clear_c0_status(ST0_CU2); \
} \
__clear_r6_hw_ll_bit(); \
__clear_r5_hw_ll_bit(); \
__clear_software_ll_bit(); \
if (cpu_has_userlocal) \
write_c0_userlocal(task_thread_info(next)->tp_value); \

779
arch/mips/include/asm/unaligned-emul.h Обычный файл
Просмотреть файл

@@ -0,0 +1,779 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _ASM_MIPS_UNALIGNED_EMUL_H
#define _ASM_MIPS_UNALIGNED_EMUL_H
#include <asm/asm.h>
#ifdef __BIG_ENDIAN
#define _LoadHW(addr, value, res, type) \
do { \
__asm__ __volatile__ (".set\tnoat\n" \
"1:\t"type##_lb("%0", "0(%2)")"\n" \
"2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
"3:\t.set\tat\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _LoadW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
"1:\t"type##_lwl("%0", "(%2)")"\n" \
"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
"li\t%1, 0\n" \
"3:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without lwl instruction */
#define _LoadW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n" \
".set\tnoat\n\t" \
"1:"type##_lb("%0", "0(%2)")"\n\t" \
"2:"type##_lbu("$1", "1(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"3:"type##_lbu("$1", "2(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"4:"type##_lbu("$1", "3(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
".set\tpop\n" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%1, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _LoadHWU(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tnoat\n" \
"1:\t"type##_lbu("%0", "0(%2)")"\n" \
"2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
"3:\n\t" \
".insn\n\t" \
".set\tat\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _LoadWU(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
"1:\t"type##_lwl("%0", "(%2)")"\n" \
"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
"dsll\t%0, %0, 32\n\t" \
"dsrl\t%0, %0, 32\n\t" \
"li\t%1, 0\n" \
"3:\n\t" \
".insn\n\t" \
"\t.section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#define _LoadDW(addr, value, res) \
do { \
__asm__ __volatile__ ( \
"1:\tldl\t%0, (%2)\n" \
"2:\tldr\t%0, 7(%2)\n\t" \
"li\t%1, 0\n" \
"3:\n\t" \
".insn\n\t" \
"\t.section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without lwl and ldl instructions */
#define _LoadWU(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n\t" \
".set\tnoat\n\t" \
"1:"type##_lbu("%0", "0(%2)")"\n\t" \
"2:"type##_lbu("$1", "1(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"3:"type##_lbu("$1", "2(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"4:"type##_lbu("$1", "3(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
".set\tpop\n" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%1, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#define _LoadDW(addr, value, res) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n\t" \
".set\tnoat\n\t" \
"1:lb\t%0, 0(%2)\n\t" \
"2:lbu\t $1, 1(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"3:lbu\t$1, 2(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"4:lbu\t$1, 3(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"5:lbu\t$1, 4(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"6:lbu\t$1, 5(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"7:lbu\t$1, 6(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"8:lbu\t$1, 7(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
".set\tpop\n\t" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%1, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
STR(PTR)"\t5b, 11b\n\t" \
STR(PTR)"\t6b, 11b\n\t" \
STR(PTR)"\t7b, 11b\n\t" \
STR(PTR)"\t8b, 11b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _StoreHW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tnoat\n" \
"1:\t"type##_sb("%1", "1(%2)")"\n" \
"srl\t$1, %1, 0x8\n" \
"2:\t"type##_sb("$1", "0(%2)")"\n" \
".set\tat\n\t" \
"li\t%0, 0\n" \
"3:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%0, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT));\
} while (0)
#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _StoreW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
"1:\t"type##_swl("%1", "(%2)")"\n" \
"2:\t"type##_swr("%1", "3(%2)")"\n\t"\
"li\t%0, 0\n" \
"3:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%0, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT)); \
} while (0)
#define _StoreDW(addr, value, res) \
do { \
__asm__ __volatile__ ( \
"1:\tsdl\t%1,(%2)\n" \
"2:\tsdr\t%1, 7(%2)\n\t" \
"li\t%0, 0\n" \
"3:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%0, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT)); \
} while (0)
#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _StoreW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n\t" \
".set\tnoat\n\t" \
"1:"type##_sb("%1", "3(%2)")"\n\t" \
"srl\t$1, %1, 0x8\n\t" \
"2:"type##_sb("$1", "2(%2)")"\n\t" \
"srl\t$1, $1, 0x8\n\t" \
"3:"type##_sb("$1", "1(%2)")"\n\t" \
"srl\t$1, $1, 0x8\n\t" \
"4:"type##_sb("$1", "0(%2)")"\n\t" \
".set\tpop\n\t" \
"li\t%0, 0\n" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%0, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
".previous" \
: "=&r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT) \
: "memory"); \
} while (0)
#define _StoreDW(addr, value, res) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n\t" \
".set\tnoat\n\t" \
"1:sb\t%1, 7(%2)\n\t" \
"dsrl\t$1, %1, 0x8\n\t" \
"2:sb\t$1, 6(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"3:sb\t$1, 5(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"4:sb\t$1, 4(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"5:sb\t$1, 3(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"6:sb\t$1, 2(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"7:sb\t$1, 1(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"8:sb\t$1, 0(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
".set\tpop\n\t" \
"li\t%0, 0\n" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%0, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
STR(PTR)"\t5b, 11b\n\t" \
STR(PTR)"\t6b, 11b\n\t" \
STR(PTR)"\t7b, 11b\n\t" \
STR(PTR)"\t8b, 11b\n\t" \
".previous" \
: "=&r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT) \
: "memory"); \
} while (0)
#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#else /* __BIG_ENDIAN */
#define _LoadHW(addr, value, res, type) \
do { \
__asm__ __volatile__ (".set\tnoat\n" \
"1:\t"type##_lb("%0", "1(%2)")"\n" \
"2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
"3:\t.set\tat\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _LoadW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
"1:\t"type##_lwl("%0", "3(%2)")"\n" \
"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
"li\t%1, 0\n" \
"3:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without lwl instruction */
#define _LoadW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n" \
".set\tnoat\n\t" \
"1:"type##_lb("%0", "3(%2)")"\n\t" \
"2:"type##_lbu("$1", "2(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"3:"type##_lbu("$1", "1(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"4:"type##_lbu("$1", "0(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
".set\tpop\n" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%1, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _LoadHWU(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tnoat\n" \
"1:\t"type##_lbu("%0", "1(%2)")"\n" \
"2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
"3:\n\t" \
".insn\n\t" \
".set\tat\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _LoadWU(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
"1:\t"type##_lwl("%0", "3(%2)")"\n" \
"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
"dsll\t%0, %0, 32\n\t" \
"dsrl\t%0, %0, 32\n\t" \
"li\t%1, 0\n" \
"3:\n\t" \
".insn\n\t" \
"\t.section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#define _LoadDW(addr, value, res) \
do { \
__asm__ __volatile__ ( \
"1:\tldl\t%0, 7(%2)\n" \
"2:\tldr\t%0, (%2)\n\t" \
"li\t%1, 0\n" \
"3:\n\t" \
".insn\n\t" \
"\t.section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%1, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without lwl and ldl instructions */
#define _LoadWU(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n\t" \
".set\tnoat\n\t" \
"1:"type##_lbu("%0", "3(%2)")"\n\t" \
"2:"type##_lbu("$1", "2(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"3:"type##_lbu("$1", "1(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"4:"type##_lbu("$1", "0(%2)")"\n\t" \
"sll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
".set\tpop\n" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%1, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#define _LoadDW(addr, value, res) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n\t" \
".set\tnoat\n\t" \
"1:lb\t%0, 7(%2)\n\t" \
"2:lbu\t$1, 6(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"3:lbu\t$1, 5(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"4:lbu\t$1, 4(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"5:lbu\t$1, 3(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"6:lbu\t$1, 2(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"7:lbu\t$1, 1(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"8:lbu\t$1, 0(%2)\n\t" \
"dsll\t%0, 0x8\n\t" \
"or\t%0, $1\n\t" \
"li\t%1, 0\n" \
".set\tpop\n\t" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%1, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
STR(PTR)"\t5b, 11b\n\t" \
STR(PTR)"\t6b, 11b\n\t" \
STR(PTR)"\t7b, 11b\n\t" \
STR(PTR)"\t8b, 11b\n\t" \
".previous" \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while (0)
#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _StoreHW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tnoat\n" \
"1:\t"type##_sb("%1", "0(%2)")"\n" \
"srl\t$1,%1, 0x8\n" \
"2:\t"type##_sb("$1", "1(%2)")"\n" \
".set\tat\n\t" \
"li\t%0, 0\n" \
"3:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%0, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT));\
} while (0)
#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _StoreW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
"1:\t"type##_swl("%1", "3(%2)")"\n" \
"2:\t"type##_swr("%1", "(%2)")"\n\t"\
"li\t%0, 0\n" \
"3:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%0, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT)); \
} while (0)
#define _StoreDW(addr, value, res) \
do { \
__asm__ __volatile__ ( \
"1:\tsdl\t%1, 7(%2)\n" \
"2:\tsdr\t%1, (%2)\n\t" \
"li\t%0, 0\n" \
"3:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"4:\tli\t%0, %3\n\t" \
"j\t3b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 4b\n\t" \
STR(PTR)"\t2b, 4b\n\t" \
".previous" \
: "=r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT)); \
} while (0)
#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without swl and sdl instructions */
#define _StoreW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n\t" \
".set\tnoat\n\t" \
"1:"type##_sb("%1", "0(%2)")"\n\t" \
"srl\t$1, %1, 0x8\n\t" \
"2:"type##_sb("$1", "1(%2)")"\n\t" \
"srl\t$1, $1, 0x8\n\t" \
"3:"type##_sb("$1", "2(%2)")"\n\t" \
"srl\t$1, $1, 0x8\n\t" \
"4:"type##_sb("$1", "3(%2)")"\n\t" \
".set\tpop\n\t" \
"li\t%0, 0\n" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%0, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
".previous" \
: "=&r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT) \
: "memory"); \
} while (0)
#define _StoreDW(addr, value, res) \
do { \
__asm__ __volatile__ ( \
".set\tpush\n\t" \
".set\tnoat\n\t" \
"1:sb\t%1, 0(%2)\n\t" \
"dsrl\t$1, %1, 0x8\n\t" \
"2:sb\t$1, 1(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"3:sb\t$1, 2(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"4:sb\t$1, 3(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"5:sb\t$1, 4(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"6:sb\t$1, 5(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"7:sb\t$1, 6(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
"8:sb\t$1, 7(%2)\n\t" \
"dsrl\t$1, $1, 0x8\n\t" \
".set\tpop\n\t" \
"li\t%0, 0\n" \
"10:\n\t" \
".insn\n\t" \
".section\t.fixup,\"ax\"\n\t" \
"11:\tli\t%0, %3\n\t" \
"j\t10b\n\t" \
".previous\n\t" \
".section\t__ex_table,\"a\"\n\t" \
STR(PTR)"\t1b, 11b\n\t" \
STR(PTR)"\t2b, 11b\n\t" \
STR(PTR)"\t3b, 11b\n\t" \
STR(PTR)"\t4b, 11b\n\t" \
STR(PTR)"\t5b, 11b\n\t" \
STR(PTR)"\t6b, 11b\n\t" \
STR(PTR)"\t7b, 11b\n\t" \
STR(PTR)"\t8b, 11b\n\t" \
".previous" \
: "=&r" (res) \
: "r" (value), "r" (addr), "i" (-EFAULT) \
: "memory"); \
} while (0)
#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#endif
#define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
#define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user)
#define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel)
#define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user)
#define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel)
#define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user)
#define LoadW(addr, value, res) _LoadW(addr, value, res, kernel)
#define LoadWE(addr, value, res) _LoadW(addr, value, res, user)
#define LoadDW(addr, value, res) _LoadDW(addr, value, res)
#define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel)
#define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user)
#define StoreW(addr, value, res) _StoreW(addr, value, res, kernel)
#define StoreWE(addr, value, res) _StoreW(addr, value, res, user)
#define StoreDW(addr, value, res) _StoreDW(addr, value, res)
#endif /* _ASM_MIPS_UNALIGNED_EMUL_H */

6
arch/mips/include/asm/vermagic.h
Просмотреть файл

@@ -8,12 +8,16 @@
#define MODULE_PROC_FAMILY "MIPS32_R1 "
#elif defined CONFIG_CPU_MIPS32_R2
#define MODULE_PROC_FAMILY "MIPS32_R2 "
#elif defined CONFIG_CPU_MIPS32_R5
#define MODULE_PROC_FAMILY "MIPS32_R5 "
#elif defined CONFIG_CPU_MIPS32_R6
#define MODULE_PROC_FAMILY "MIPS32_R6 "
#elif defined CONFIG_CPU_MIPS64_R1
#define MODULE_PROC_FAMILY "MIPS64_R1 "
#elif defined CONFIG_CPU_MIPS64_R2
#define MODULE_PROC_FAMILY "MIPS64_R2 "
#elif defined CONFIG_CPU_MIPS64_R5
#define MODULE_PROC_FAMILY "MIPS64_R5 "
#elif defined CONFIG_CPU_MIPS64_R6
#define MODULE_PROC_FAMILY "MIPS64_R6 "
#elif defined CONFIG_CPU_R3000
@@ -46,6 +50,8 @@
#define MODULE_PROC_FAMILY "LOONGSON64 "
#elif defined CONFIG_CPU_CAVIUM_OCTEON
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_P5600
#define MODULE_PROC_FAMILY "P5600 "
#elif defined CONFIG_CPU_XLR
#define MODULE_PROC_FAMILY "XLR "
#elif defined CONFIG_CPU_XLP

1
arch/mips/include/uapi/asm/hwcap.h
Просмотреть файл

@@ -17,5 +17,6 @@
#define HWCAP_LOONGSON_MMI (1 << 11)
#define HWCAP_LOONGSON_EXT (1 << 12)
#define HWCAP_LOONGSON_EXT2 (1 << 13)
#define HWCAP_LOONGSON_CPUCFG (1 << 14)
#endif /* _UAPI_ASM_HWCAP_H */

26
arch/mips/include/uapi/asm/inst.h
Просмотреть файл

@@ -988,6 +988,30 @@ struct mm16_r5_format { /* Load/store from stack pointer format */
;))))
};
/*
* Loongson-3 overridden COP2 instruction formats (32-bit length)
*/
struct loongson3_lswc2_format { /* Loongson-3 overridden lwc2/swc2 Load/Store format */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int base : 5,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int fr : 1,
__BITFIELD_FIELD(unsigned int offset : 9,
__BITFIELD_FIELD(unsigned int ls : 1,
__BITFIELD_FIELD(unsigned int rq : 5,
;)))))))
};
struct loongson3_lsdc2_format { /* Loongson-3 overridden ldc2/sdc2 Load/Store format */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int base : 5,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int index : 5,
__BITFIELD_FIELD(unsigned int offset : 8,
__BITFIELD_FIELD(unsigned int opcode1 : 3,
;))))))
};
/*
* MIPS16e instruction formats (16-bit length)
*/
@@ -1088,6 +1112,8 @@ union mips_instruction {
struct mm16_rb_format mm16_rb_format;
struct mm16_r3_format mm16_r3_format;
struct mm16_r5_format mm16_r5_format;
struct loongson3_lswc2_format loongson3_lswc2_format;
struct loongson3_lsdc2_format loongson3_lsdc2_format;
};
union mips16e_instruction {