Merge branch 'linus' into percpu-cpumask-x86-for-linus-2

Conflicts:
	arch/sparc/kernel/time_64.c
	drivers/gpu/drm/drm_proc.c

Manual merge to resolve build warning due to phys_addr_t type change
on x86:

	drivers/gpu/drm/drm_info.c

Signed-off-by: Ingo Molnar <mingo@elte.hu>
这个提交包含在:
Ingo Molnar
2009-03-28 04:21:18 +01:00
当前提交 82268da1b1
修改 408 个文件,包含 18152 行新增6418 行删除

查看文件

@@ -485,6 +485,7 @@ config MWL8K
source "drivers/net/wireless/p54/Kconfig"
source "drivers/net/wireless/ath5k/Kconfig"
source "drivers/net/wireless/ath9k/Kconfig"
source "drivers/net/wireless/ar9170/Kconfig"
source "drivers/net/wireless/ipw2x00/Kconfig"
source "drivers/net/wireless/iwlwifi/Kconfig"
source "drivers/net/wireless/hostap/Kconfig"

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@@ -57,5 +57,6 @@ obj-$(CONFIG_P54_COMMON) += p54/
obj-$(CONFIG_ATH5K) += ath5k/
obj-$(CONFIG_ATH9K) += ath9k/
obj-$(CONFIG_AR9170_USB) += ar9170/
obj-$(CONFIG_MAC80211_HWSIM) += mac80211_hwsim.o

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@@ -0,0 +1,17 @@
config AR9170_USB
tristate "Atheros AR9170 802.11n USB support"
depends on USB && MAC80211 && WLAN_80211 && EXPERIMENTAL
select FW_LOADER
help
This is a driver for the Atheros "otus" 802.11n USB devices.
These devices require additional firmware (2 files).
For now, these files can be downloaded from here:
http://wireless.kernel.org/en/users/Drivers/ar9170
If you choose to build a module, it'll be called ar9170usb.
config AR9170_LEDS
bool
depends on AR9170_USB && MAC80211_LEDS && (LEDS_CLASS = y || LEDS_CLASS = AR9170_USB)
default y

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@@ -0,0 +1,3 @@
ar9170usb-objs := usb.o main.o cmd.o mac.o phy.o led.o
obj-$(CONFIG_AR9170_USB) += ar9170usb.o

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@@ -0,0 +1,209 @@
/*
* Atheros AR9170 driver
*
* Driver specific definitions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR9170_H
#define __AR9170_H
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <net/wireless.h>
#include <net/mac80211.h>
#ifdef CONFIG_AR9170_LEDS
#include <linux/leds.h>
#endif /* CONFIG_AR9170_LEDS */
#include "eeprom.h"
#include "hw.h"
#define PAYLOAD_MAX (AR9170_MAX_CMD_LEN/4 - 1)
enum ar9170_bw {
AR9170_BW_20,
AR9170_BW_40_BELOW,
AR9170_BW_40_ABOVE,
__AR9170_NUM_BW,
};
enum ar9170_rf_init_mode {
AR9170_RFI_NONE,
AR9170_RFI_WARM,
AR9170_RFI_COLD,
};
#define AR9170_MAX_RX_BUFFER_SIZE 8192
#ifdef CONFIG_AR9170_LEDS
struct ar9170;
struct ar9170_led {
struct ar9170 *ar;
struct led_classdev l;
char name[32];
unsigned int toggled;
bool registered;
};
#endif /* CONFIG_AR9170_LEDS */
enum ar9170_device_state {
AR9170_UNKNOWN_STATE,
AR9170_STOPPED,
AR9170_IDLE,
AR9170_STARTED,
AR9170_ASSOCIATED,
};
struct ar9170 {
struct ieee80211_hw *hw;
struct mutex mutex;
enum ar9170_device_state state;
int (*open)(struct ar9170 *);
void (*stop)(struct ar9170 *);
int (*tx)(struct ar9170 *, struct sk_buff *, bool, unsigned int);
int (*exec_cmd)(struct ar9170 *, enum ar9170_cmd, u32 ,
void *, u32 , void *);
void (*callback_cmd)(struct ar9170 *, u32 , void *);
/* interface mode settings */
struct ieee80211_vif *vif;
u8 mac_addr[ETH_ALEN];
u8 bssid[ETH_ALEN];
/* beaconing */
struct sk_buff *beacon;
struct work_struct beacon_work;
/* cryptographic engine */
u64 usedkeys;
bool rx_software_decryption;
bool disable_offload;
/* filter settings */
struct work_struct filter_config_work;
u64 cur_mc_hash, want_mc_hash;
u32 cur_filter, want_filter;
unsigned int filter_changed;
bool sniffer_enabled;
/* PHY */
struct ieee80211_channel *channel;
int noise[4];
/* power calibration data */
u8 power_5G_leg[4];
u8 power_2G_cck[4];
u8 power_2G_ofdm[4];
u8 power_5G_ht20[8];
u8 power_5G_ht40[8];
u8 power_2G_ht20[8];
u8 power_2G_ht40[8];
#ifdef CONFIG_AR9170_LEDS
struct delayed_work led_work;
struct ar9170_led leds[AR9170_NUM_LEDS];
#endif /* CONFIG_AR9170_LEDS */
/* qos queue settings */
spinlock_t tx_stats_lock;
struct ieee80211_tx_queue_stats tx_stats[5];
struct ieee80211_tx_queue_params edcf[5];
spinlock_t cmdlock;
__le32 cmdbuf[PAYLOAD_MAX + 1];
/* MAC statistics */
struct ieee80211_low_level_stats stats;
/* EEPROM */
struct ar9170_eeprom eeprom;
/* global tx status for unregistered Stations. */
struct sk_buff_head global_tx_status;
struct sk_buff_head global_tx_status_waste;
struct delayed_work tx_status_janitor;
};
struct ar9170_sta_info {
struct sk_buff_head tx_status[__AR9170_NUM_TXQ];
};
#define IS_STARTED(a) (a->state >= AR9170_STARTED)
#define IS_ACCEPTING_CMD(a) (a->state >= AR9170_IDLE)
#define AR9170_FILTER_CHANGED_PROMISC BIT(0)
#define AR9170_FILTER_CHANGED_MULTICAST BIT(1)
#define AR9170_FILTER_CHANGED_FRAMEFILTER BIT(2)
/* exported interface */
void *ar9170_alloc(size_t priv_size);
int ar9170_register(struct ar9170 *ar, struct device *pdev);
void ar9170_rx(struct ar9170 *ar, struct sk_buff *skb);
void ar9170_unregister(struct ar9170 *ar);
void ar9170_handle_tx_status(struct ar9170 *ar, struct sk_buff *skb,
bool update_statistics, u16 tx_status);
/* MAC */
int ar9170_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
int ar9170_init_mac(struct ar9170 *ar);
int ar9170_set_qos(struct ar9170 *ar);
int ar9170_update_multicast(struct ar9170 *ar);
int ar9170_update_frame_filter(struct ar9170 *ar);
int ar9170_set_operating_mode(struct ar9170 *ar);
int ar9170_set_beacon_timers(struct ar9170 *ar);
int ar9170_set_hwretry_limit(struct ar9170 *ar, u32 max_retry);
int ar9170_update_beacon(struct ar9170 *ar);
void ar9170_new_beacon(struct work_struct *work);
int ar9170_upload_key(struct ar9170 *ar, u8 id, const u8 *mac, u8 ktype,
u8 keyidx, u8 *keydata, int keylen);
int ar9170_disable_key(struct ar9170 *ar, u8 id);
/* LEDs */
#ifdef CONFIG_AR9170_LEDS
int ar9170_register_leds(struct ar9170 *ar);
void ar9170_unregister_leds(struct ar9170 *ar);
#endif /* CONFIG_AR9170_LEDS */
int ar9170_init_leds(struct ar9170 *ar);
int ar9170_set_leds_state(struct ar9170 *ar, u32 led_state);
/* PHY / RF */
int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band);
int ar9170_init_rf(struct ar9170 *ar);
int ar9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
enum ar9170_rf_init_mode rfi, enum ar9170_bw bw);
#endif /* __AR9170_H */

查看文件

@@ -0,0 +1,129 @@
/*
* Atheros AR9170 driver
*
* Basic HW register/memory/command access functions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "ar9170.h"
#include "cmd.h"
int ar9170_write_mem(struct ar9170 *ar, const __le32 *data, size_t len)
{
int err;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return 0;
err = ar->exec_cmd(ar, AR9170_CMD_WMEM, len, (u8 *) data, 0, NULL);
if (err)
printk(KERN_DEBUG "%s: writing memory failed\n",
wiphy_name(ar->hw->wiphy));
return err;
}
int ar9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val)
{
__le32 buf[2] = {
cpu_to_le32(reg),
cpu_to_le32(val),
};
int err;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return 0;
err = ar->exec_cmd(ar, AR9170_CMD_WREG, sizeof(buf),
(u8 *) buf, 0, NULL);
if (err)
printk(KERN_DEBUG "%s: writing reg %#x (val %#x) failed\n",
wiphy_name(ar->hw->wiphy), reg, val);
return err;
}
static int ar9170_read_mreg(struct ar9170 *ar, int nregs,
const u32 *regs, u32 *out)
{
int i, err;
__le32 *offs, *res;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return 0;
/* abuse "out" for the register offsets, must be same length */
offs = (__le32 *)out;
for (i = 0; i < nregs; i++)
offs[i] = cpu_to_le32(regs[i]);
/* also use the same buffer for the input */
res = (__le32 *)out;
err = ar->exec_cmd(ar, AR9170_CMD_RREG,
4 * nregs, (u8 *)offs,
4 * nregs, (u8 *)res);
if (err)
return err;
/* convert result to cpu endian */
for (i = 0; i < nregs; i++)
out[i] = le32_to_cpu(res[i]);
return 0;
}
int ar9170_read_reg(struct ar9170 *ar, u32 reg, u32 *val)
{
return ar9170_read_mreg(ar, 1, &reg, val);
}
int ar9170_echo_test(struct ar9170 *ar, u32 v)
{
__le32 echobuf = cpu_to_le32(v);
__le32 echores;
int err;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return -ENODEV;
err = ar->exec_cmd(ar, AR9170_CMD_ECHO,
4, (u8 *)&echobuf,
4, (u8 *)&echores);
if (err)
return err;
if (echobuf != echores)
return -EINVAL;
return 0;
}

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@@ -0,0 +1,91 @@
/*
* Atheros AR9170 driver
*
* Basic HW register/memory/command access functions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __CMD_H
#define __CMD_H
#include "ar9170.h"
/* basic HW access */
int ar9170_write_mem(struct ar9170 *ar, const __le32 *data, size_t len);
int ar9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val);
int ar9170_read_reg(struct ar9170 *ar, u32 reg, u32 *val);
int ar9170_echo_test(struct ar9170 *ar, u32 v);
/*
* Macros to facilitate writing multiple registers in a single
* write-combining USB command. Note that when the first group
* fails the whole thing will fail without any others attempted,
* but you won't know which write in the group failed.
*/
#define ar9170_regwrite_begin(ar) \
do { \
int __nreg = 0, __err = 0; \
struct ar9170 *__ar = ar;
#define ar9170_regwrite(r, v) do { \
__ar->cmdbuf[2 * __nreg + 1] = cpu_to_le32(r); \
__ar->cmdbuf[2 * __nreg + 2] = cpu_to_le32(v); \
__nreg++; \
if ((__nreg >= PAYLOAD_MAX/2)) { \
if (IS_ACCEPTING_CMD(__ar)) \
__err = ar->exec_cmd(__ar, AR9170_CMD_WREG, \
8 * __nreg, \
(u8 *) &__ar->cmdbuf[1], \
0, NULL); \
__nreg = 0; \
if (__err) \
goto __regwrite_out; \
} \
} while (0)
#define ar9170_regwrite_finish() \
__regwrite_out : \
if (__nreg) { \
if (IS_ACCEPTING_CMD(__ar)) \
__err = ar->exec_cmd(__ar, AR9170_CMD_WREG, \
8 * __nreg, \
(u8 *) &__ar->cmdbuf[1], \
0, NULL); \
__nreg = 0; \
}
#define ar9170_regwrite_result() \
__err; \
} while (0);
#endif /* __CMD_H */

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@@ -0,0 +1,179 @@
/*
* Atheros AR9170 driver
*
* EEPROM layout
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR9170_EEPROM_H
#define __AR9170_EEPROM_H
#define AR5416_MAX_CHAINS 2
#define AR5416_MODAL_SPURS 5
struct ar9170_eeprom_modal {
__le32 antCtrlChain[AR5416_MAX_CHAINS];
__le32 antCtrlCommon;
s8 antennaGainCh[AR5416_MAX_CHAINS];
u8 switchSettling;
u8 txRxAttenCh[AR5416_MAX_CHAINS];
u8 rxTxMarginCh[AR5416_MAX_CHAINS];
s8 adcDesiredSize;
s8 pgaDesiredSize;
u8 xlnaGainCh[AR5416_MAX_CHAINS];
u8 txEndToXpaOff;
u8 txEndToRxOn;
u8 txFrameToXpaOn;
u8 thresh62;
s8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
u8 xpdGain;
u8 xpd;
s8 iqCalICh[AR5416_MAX_CHAINS];
s8 iqCalQCh[AR5416_MAX_CHAINS];
u8 pdGainOverlap;
u8 ob;
u8 db;
u8 xpaBiasLvl;
u8 pwrDecreaseFor2Chain;
u8 pwrDecreaseFor3Chain;
u8 txFrameToDataStart;
u8 txFrameToPaOn;
u8 ht40PowerIncForPdadc;
u8 bswAtten[AR5416_MAX_CHAINS];
u8 bswMargin[AR5416_MAX_CHAINS];
u8 swSettleHt40;
u8 reserved[22];
struct spur_channel {
__le16 spurChan;
u8 spurRangeLow;
u8 spurRangeHigh;
} __packed spur_channels[AR5416_MODAL_SPURS];
} __packed;
#define AR5416_NUM_PD_GAINS 4
#define AR5416_PD_GAIN_ICEPTS 5
struct ar9170_calibration_data_per_freq {
u8 pwr_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
u8 vpd_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
} __packed;
#define AR5416_NUM_5G_CAL_PIERS 8
#define AR5416_NUM_2G_CAL_PIERS 4
#define AR5416_NUM_5G_TARGET_PWRS 8
#define AR5416_NUM_2G_CCK_TARGET_PWRS 3
#define AR5416_NUM_2G_OFDM_TARGET_PWRS 4
#define AR5416_MAX_NUM_TGT_PWRS 8
struct ar9170_calibration_target_power_legacy {
u8 freq;
u8 power[4];
} __packed;
struct ar9170_calibration_target_power_ht {
u8 freq;
u8 power[8];
} __packed;
#define AR5416_NUM_CTLS 24
struct ar9170_calctl_edges {
u8 channel;
#define AR9170_CALCTL_EDGE_FLAGS 0xC0
u8 power_flags;
} __packed;
#define AR5416_NUM_BAND_EDGES 8
struct ar9170_calctl_data {
struct ar9170_calctl_edges
control_edges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
} __packed;
struct ar9170_eeprom {
__le16 length;
__le16 checksum;
__le16 version;
u8 operating_flags;
#define AR9170_OPFLAG_5GHZ 1
#define AR9170_OPFLAG_2GHZ 2
u8 misc;
__le16 reg_domain[2];
u8 mac_address[6];
u8 rx_mask;
u8 tx_mask;
__le16 rf_silent;
__le16 bluetooth_options;
__le16 device_capabilities;
__le32 build_number;
u8 deviceType;
u8 reserved[33];
u8 customer_data[64];
struct ar9170_eeprom_modal
modal_header[2];
u8 cal_freq_pier_5G[AR5416_NUM_5G_CAL_PIERS];
u8 cal_freq_pier_2G[AR5416_NUM_2G_CAL_PIERS];
struct ar9170_calibration_data_per_freq
cal_pier_data_5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS],
cal_pier_data_2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
/* power calibration data */
struct ar9170_calibration_target_power_legacy
cal_tgt_pwr_5G[AR5416_NUM_5G_TARGET_PWRS];
struct ar9170_calibration_target_power_ht
cal_tgt_pwr_5G_ht20[AR5416_NUM_5G_TARGET_PWRS],
cal_tgt_pwr_5G_ht40[AR5416_NUM_5G_TARGET_PWRS];
struct ar9170_calibration_target_power_legacy
cal_tgt_pwr_2G_cck[AR5416_NUM_2G_CCK_TARGET_PWRS],
cal_tgt_pwr_2G_ofdm[AR5416_NUM_2G_OFDM_TARGET_PWRS];
struct ar9170_calibration_target_power_ht
cal_tgt_pwr_2G_ht20[AR5416_NUM_2G_OFDM_TARGET_PWRS],
cal_tgt_pwr_2G_ht40[AR5416_NUM_2G_OFDM_TARGET_PWRS];
/* conformance testing limits */
u8 ctl_index[AR5416_NUM_CTLS];
struct ar9170_calctl_data
ctl_data[AR5416_NUM_CTLS];
u8 pad;
__le16 subsystem_id;
} __packed;
#endif /* __AR9170_EEPROM_H */

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@@ -0,0 +1,417 @@
/*
* Atheros AR9170 driver
*
* Hardware-specific definitions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR9170_HW_H
#define __AR9170_HW_H
#define AR9170_MAX_CMD_LEN 64
enum ar9170_cmd {
AR9170_CMD_RREG = 0x00,
AR9170_CMD_WREG = 0x01,
AR9170_CMD_RMEM = 0x02,
AR9170_CMD_WMEM = 0x03,
AR9170_CMD_BITAND = 0x04,
AR9170_CMD_BITOR = 0x05,
AR9170_CMD_EKEY = 0x28,
AR9170_CMD_DKEY = 0x29,
AR9170_CMD_FREQUENCY = 0x30,
AR9170_CMD_RF_INIT = 0x31,
AR9170_CMD_SYNTH = 0x32,
AR9170_CMD_FREQ_START = 0x33,
AR9170_CMD_ECHO = 0x80,
AR9170_CMD_TALLY = 0x81,
AR9170_CMD_TALLY_APD = 0x82,
AR9170_CMD_CONFIG = 0x83,
AR9170_CMD_RESET = 0x90,
AR9170_CMD_DKRESET = 0x91,
AR9170_CMD_DKTX_STATUS = 0x92,
AR9170_CMD_FDC = 0xA0,
AR9170_CMD_WREEPROM = 0xB0,
AR9170_CMD_WFLASH = 0xB0,
AR9170_CMD_FLASH_ERASE = 0xB1,
AR9170_CMD_FLASH_PROG = 0xB2,
AR9170_CMD_FLASH_CHKSUM = 0xB3,
AR9170_CMD_FLASH_READ = 0xB4,
AR9170_CMD_FW_DL_INIT = 0xB5,
AR9170_CMD_MEM_WREEPROM = 0xBB,
};
/* endpoints */
#define AR9170_EP_TX 1
#define AR9170_EP_RX 2
#define AR9170_EP_IRQ 3
#define AR9170_EP_CMD 4
#define AR9170_EEPROM_START 0x1600
#define AR9170_GPIO_REG_BASE 0x1d0100
#define AR9170_GPIO_REG_PORT_TYPE AR9170_GPIO_REG_BASE
#define AR9170_GPIO_REG_DATA (AR9170_GPIO_REG_BASE + 4)
#define AR9170_NUM_LEDS 2
#define AR9170_USB_REG_BASE 0x1e1000
#define AR9170_USB_REG_DMA_CTL (AR9170_USB_REG_BASE + 0x108)
#define AR9170_DMA_CTL_ENABLE_TO_DEVICE 0x1
#define AR9170_DMA_CTL_ENABLE_FROM_DEVICE 0x2
#define AR9170_DMA_CTL_HIGH_SPEED 0x4
#define AR9170_DMA_CTL_PACKET_MODE 0x8
#define AR9170_USB_REG_MAX_AGG_UPLOAD (AR9170_USB_REG_BASE + 0x110)
#define AR9170_USB_REG_UPLOAD_TIME_CTL (AR9170_USB_REG_BASE + 0x114)
#define AR9170_MAC_REG_BASE 0x1c3000
#define AR9170_MAC_REG_TSF_L (AR9170_MAC_REG_BASE + 0x514)
#define AR9170_MAC_REG_TSF_H (AR9170_MAC_REG_BASE + 0x518)
#define AR9170_MAC_REG_ATIM_WINDOW (AR9170_MAC_REG_BASE + 0x51C)
#define AR9170_MAC_REG_BCN_PERIOD (AR9170_MAC_REG_BASE + 0x520)
#define AR9170_MAC_REG_PRETBTT (AR9170_MAC_REG_BASE + 0x524)
#define AR9170_MAC_REG_MAC_ADDR_L (AR9170_MAC_REG_BASE + 0x610)
#define AR9170_MAC_REG_MAC_ADDR_H (AR9170_MAC_REG_BASE + 0x614)
#define AR9170_MAC_REG_BSSID_L (AR9170_MAC_REG_BASE + 0x618)
#define AR9170_MAC_REG_BSSID_H (AR9170_MAC_REG_BASE + 0x61c)
#define AR9170_MAC_REG_GROUP_HASH_TBL_L (AR9170_MAC_REG_BASE + 0x624)
#define AR9170_MAC_REG_GROUP_HASH_TBL_H (AR9170_MAC_REG_BASE + 0x628)
#define AR9170_MAC_REG_RX_TIMEOUT (AR9170_MAC_REG_BASE + 0x62C)
#define AR9170_MAC_REG_BASIC_RATE (AR9170_MAC_REG_BASE + 0x630)
#define AR9170_MAC_REG_MANDATORY_RATE (AR9170_MAC_REG_BASE + 0x634)
#define AR9170_MAC_REG_RTS_CTS_RATE (AR9170_MAC_REG_BASE + 0x638)
#define AR9170_MAC_REG_BACKOFF_PROTECT (AR9170_MAC_REG_BASE + 0x63c)
#define AR9170_MAC_REG_RX_THRESHOLD (AR9170_MAC_REG_BASE + 0x640)
#define AR9170_MAC_REG_RX_PE_DELAY (AR9170_MAC_REG_BASE + 0x64C)
#define AR9170_MAC_REG_DYNAMIC_SIFS_ACK (AR9170_MAC_REG_BASE + 0x658)
#define AR9170_MAC_REG_SNIFFER (AR9170_MAC_REG_BASE + 0x674)
#define AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC BIT(0)
#define AR9170_MAC_REG_SNIFFER_DEFAULTS 0x02000000
#define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678)
#define AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE BIT(3)
#define AR9170_MAC_REG_ENCRYPTION_DEFAULTS 0x70
#define AR9170_MAC_REG_MISC_680 (AR9170_MAC_REG_BASE + 0x680)
#define AR9170_MAC_REG_TX_UNDERRUN (AR9170_MAC_REG_BASE + 0x688)
#define AR9170_MAC_REG_FRAMETYPE_FILTER (AR9170_MAC_REG_BASE + 0x68c)
#define AR9170_MAC_REG_FTF_ASSOC_REQ BIT(0)
#define AR9170_MAC_REG_FTF_ASSOC_RESP BIT(1)
#define AR9170_MAC_REG_FTF_REASSOC_REQ BIT(2)
#define AR9170_MAC_REG_FTF_REASSOC_RESP BIT(3)
#define AR9170_MAC_REG_FTF_PRB_REQ BIT(4)
#define AR9170_MAC_REG_FTF_PRB_RESP BIT(5)
#define AR9170_MAC_REG_FTF_BIT6 BIT(6)
#define AR9170_MAC_REG_FTF_BIT7 BIT(7)
#define AR9170_MAC_REG_FTF_BEACON BIT(8)
#define AR9170_MAC_REG_FTF_ATIM BIT(9)
#define AR9170_MAC_REG_FTF_DEASSOC BIT(10)
#define AR9170_MAC_REG_FTF_AUTH BIT(11)
#define AR9170_MAC_REG_FTF_DEAUTH BIT(12)
#define AR9170_MAC_REG_FTF_BIT13 BIT(13)
#define AR9170_MAC_REG_FTF_BIT14 BIT(14)
#define AR9170_MAC_REG_FTF_BIT15 BIT(15)
#define AR9170_MAC_REG_FTF_BAR BIT(24)
#define AR9170_MAC_REG_FTF_BIT25 BIT(25)
#define AR9170_MAC_REG_FTF_PSPOLL BIT(26)
#define AR9170_MAC_REG_FTF_RTS BIT(27)
#define AR9170_MAC_REG_FTF_CTS BIT(28)
#define AR9170_MAC_REG_FTF_ACK BIT(29)
#define AR9170_MAC_REG_FTF_CFE BIT(30)
#define AR9170_MAC_REG_FTF_CFE_ACK BIT(31)
#define AR9170_MAC_REG_FTF_DEFAULTS 0x0500ffff
#define AR9170_MAC_REG_FTF_MONITOR 0xfd00ffff
#define AR9170_MAC_REG_RX_TOTAL (AR9170_MAC_REG_BASE + 0x6A0)
#define AR9170_MAC_REG_RX_CRC32 (AR9170_MAC_REG_BASE + 0x6A4)
#define AR9170_MAC_REG_RX_CRC16 (AR9170_MAC_REG_BASE + 0x6A8)
#define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI (AR9170_MAC_REG_BASE + 0x6AC)
#define AR9170_MAC_REG_RX_OVERRUN (AR9170_MAC_REG_BASE + 0x6B0)
#define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL (AR9170_MAC_REG_BASE + 0x6BC)
#define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6CC)
#define AR9170_MAC_REG_TX_TOTAL (AR9170_MAC_REG_BASE + 0x6F4)
#define AR9170_MAC_REG_ACK_EXTENSION (AR9170_MAC_REG_BASE + 0x690)
#define AR9170_MAC_REG_EIFS_AND_SIFS (AR9170_MAC_REG_BASE + 0x698)
#define AR9170_MAC_REG_SLOT_TIME (AR9170_MAC_REG_BASE + 0x6F0)
#define AR9170_MAC_REG_POWERMANAGEMENT (AR9170_MAC_REG_BASE + 0x700)
#define AR9170_MAC_REG_POWERMGT_IBSS 0xe0
#define AR9170_MAC_REG_POWERMGT_AP 0xa1
#define AR9170_MAC_REG_POWERMGT_STA 0x2
#define AR9170_MAC_REG_POWERMGT_AP_WDS 0x3
#define AR9170_MAC_REG_POWERMGT_DEFAULTS (0xf << 24)
#define AR9170_MAC_REG_ROLL_CALL_TBL_L (AR9170_MAC_REG_BASE + 0x704)
#define AR9170_MAC_REG_ROLL_CALL_TBL_H (AR9170_MAC_REG_BASE + 0x708)
#define AR9170_MAC_REG_AC0_CW (AR9170_MAC_REG_BASE + 0xB00)
#define AR9170_MAC_REG_AC1_CW (AR9170_MAC_REG_BASE + 0xB04)
#define AR9170_MAC_REG_AC2_CW (AR9170_MAC_REG_BASE + 0xB08)
#define AR9170_MAC_REG_AC3_CW (AR9170_MAC_REG_BASE + 0xB0C)
#define AR9170_MAC_REG_AC4_CW (AR9170_MAC_REG_BASE + 0xB10)
#define AR9170_MAC_REG_AC1_AC0_AIFS (AR9170_MAC_REG_BASE + 0xB14)
#define AR9170_MAC_REG_AC3_AC2_AIFS (AR9170_MAC_REG_BASE + 0xB18)
#define AR9170_MAC_REG_RETRY_MAX (AR9170_MAC_REG_BASE + 0xB28)
#define AR9170_MAC_REG_FCS_SELECT (AR9170_MAC_REG_BASE + 0xBB0)
#define AR9170_MAC_FCS_SWFCS 0x1
#define AR9170_MAC_FCS_FIFO_PROT 0x4
#define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND (AR9170_MAC_REG_BASE + 0xB30)
#define AR9170_MAC_REG_AC1_AC0_TXOP (AR9170_MAC_REG_BASE + 0xB44)
#define AR9170_MAC_REG_AC3_AC2_TXOP (AR9170_MAC_REG_BASE + 0xB48)
#define AR9170_MAC_REG_ACK_TABLE (AR9170_MAC_REG_BASE + 0xC00)
#define AR9170_MAC_REG_AMPDU_RX_THRESH (AR9170_MAC_REG_BASE + 0xC50)
#define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xD7C)
#define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f
#define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0
#define AR9170_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000
#define AR9170_MAC_TXRX_MPI_RX_TO_MASK 0xfff00000
#define AR9170_MAC_REG_BCN_ADDR (AR9170_MAC_REG_BASE + 0xD84)
#define AR9170_MAC_REG_BCN_LENGTH (AR9170_MAC_REG_BASE + 0xD88)
#define AR9170_MAC_REG_BCN_PLCP (AR9170_MAC_REG_BASE + 0xD90)
#define AR9170_MAC_REG_BCN_CTRL (AR9170_MAC_REG_BASE + 0xD94)
#define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xDA0)
#define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xDA4)
#define AR9170_PWR_REG_BASE 0x1D4000
#define AR9170_PWR_REG_CLOCK_SEL (AR9170_PWR_REG_BASE + 0x008)
#define AR9170_PWR_CLK_AHB_40MHZ 0
#define AR9170_PWR_CLK_AHB_20_22MHZ 1
#define AR9170_PWR_CLK_AHB_40_44MHZ 2
#define AR9170_PWR_CLK_AHB_80_88MHZ 3
#define AR9170_PWR_CLK_DAC_160_INV_DLY 0x70
/* put beacon here in memory */
#define AR9170_BEACON_BUFFER_ADDRESS 0x117900
struct ar9170_tx_control {
__le16 length;
__le16 mac_control;
__le32 phy_control;
u8 frame_data[0];
} __packed;
/* these are either-or */
#define AR9170_TX_MAC_PROT_RTS 0x0001
#define AR9170_TX_MAC_PROT_CTS 0x0002
#define AR9170_TX_MAC_NO_ACK 0x0004
/* if unset, MAC will only do SIFS space before frame */
#define AR9170_TX_MAC_BACKOFF 0x0008
#define AR9170_TX_MAC_BURST 0x0010
#define AR9170_TX_MAC_AGGR 0x0020
/* encryption is a two-bit field */
#define AR9170_TX_MAC_ENCR_NONE 0x0000
#define AR9170_TX_MAC_ENCR_RC4 0x0040
#define AR9170_TX_MAC_ENCR_CENC 0x0080
#define AR9170_TX_MAC_ENCR_AES 0x00c0
#define AR9170_TX_MAC_MMIC 0x0100
#define AR9170_TX_MAC_HW_DURATION 0x0200
#define AR9170_TX_MAC_QOS_SHIFT 10
#define AR9170_TX_MAC_QOS_MASK (3 << AR9170_TX_MAC_QOS_SHIFT)
#define AR9170_TX_MAC_AGGR_QOS_BIT1 0x0400
#define AR9170_TX_MAC_AGGR_QOS_BIT2 0x0800
#define AR9170_TX_MAC_DISABLE_TXOP 0x1000
#define AR9170_TX_MAC_TXOP_RIFS 0x2000
#define AR9170_TX_MAC_IMM_AMPDU 0x4000
#define AR9170_TX_MAC_RATE_PROBE 0x8000
/* either-or */
#define AR9170_TX_PHY_MOD_CCK 0x00000000
#define AR9170_TX_PHY_MOD_OFDM 0x00000001
#define AR9170_TX_PHY_MOD_HT 0x00000002
/* depends on modulation */
#define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004
#define AR9170_TX_PHY_GREENFIELD 0x00000004
#define AR9170_TX_PHY_BW_SHIFT 3
#define AR9170_TX_PHY_BW_MASK (3 << AR9170_TX_PHY_BW_SHIFT)
#define AR9170_TX_PHY_BW_20MHZ 0
#define AR9170_TX_PHY_BW_40MHZ 2
#define AR9170_TX_PHY_BW_40MHZ_DUP 3
#define AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT 6
#define AR9170_TX_PHY_TX_HEAVY_CLIP_MASK (7 << AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT)
#define AR9170_TX_PHY_TX_PWR_SHIFT 9
#define AR9170_TX_PHY_TX_PWR_MASK (0x3f << AR9170_TX_PHY_TX_PWR_SHIFT)
/* not part of the hw-spec */
#define AR9170_TX_PHY_QOS_SHIFT 25
#define AR9170_TX_PHY_QOS_MASK (3 << AR9170_TX_PHY_QOS_SHIFT)
#define AR9170_TX_PHY_TXCHAIN_SHIFT 15
#define AR9170_TX_PHY_TXCHAIN_MASK (7 << AR9170_TX_PHY_TXCHAIN_SHIFT)
#define AR9170_TX_PHY_TXCHAIN_1 1
/* use for cck, ofdm 6/9/12/18/24 and HT if capable */
#define AR9170_TX_PHY_TXCHAIN_2 5
#define AR9170_TX_PHY_MCS_SHIFT 18
#define AR9170_TX_PHY_MCS_MASK (0x7f << AR9170_TX_PHY_MCS_SHIFT)
#define AR9170_TX_PHY_SHORT_GI 0x80000000
struct ar9170_rx_head {
u8 plcp[12];
};
struct ar9170_rx_tail {
union {
struct {
u8 rssi_ant0, rssi_ant1, rssi_ant2,
rssi_ant0x, rssi_ant1x, rssi_ant2x,
rssi_combined;
};
u8 rssi[7];
};
u8 evm_stream0[6], evm_stream1[6];
u8 phy_err;
u8 SAidx, DAidx;
u8 error;
u8 status;
};
#define AR9170_ENC_ALG_NONE 0x0
#define AR9170_ENC_ALG_WEP64 0x1
#define AR9170_ENC_ALG_TKIP 0x2
#define AR9170_ENC_ALG_AESCCMP 0x4
#define AR9170_ENC_ALG_WEP128 0x5
#define AR9170_ENC_ALG_WEP256 0x6
#define AR9170_ENC_ALG_CENC 0x7
#define AR9170_RX_ENC_SOFTWARE 0x8
static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_tail *t)
{
return (t->SAidx & 0xc0) >> 4 |
(t->DAidx & 0xc0) >> 6;
}
#define AR9170_RX_STATUS_MODULATION_MASK 0x03
#define AR9170_RX_STATUS_MODULATION_CCK 0x00
#define AR9170_RX_STATUS_MODULATION_OFDM 0x01
#define AR9170_RX_STATUS_MODULATION_HT 0x02
#define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03
/* depends on modulation */
#define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08
#define AR9170_RX_STATUS_GREENFIELD 0x08
#define AR9170_RX_STATUS_MPDU_MASK 0x30
#define AR9170_RX_STATUS_MPDU_SINGLE 0x00
#define AR9170_RX_STATUS_MPDU_FIRST 0x10
#define AR9170_RX_STATUS_MPDU_MIDDLE 0x20
#define AR9170_RX_STATUS_MPDU_LAST 0x30
#define AR9170_RX_ERROR_RXTO 0x01
#define AR9170_RX_ERROR_OVERRUN 0x02
#define AR9170_RX_ERROR_DECRYPT 0x04
#define AR9170_RX_ERROR_FCS 0x08
#define AR9170_RX_ERROR_WRONG_RA 0x10
#define AR9170_RX_ERROR_PLCP 0x20
#define AR9170_RX_ERROR_MMIC 0x40
struct ar9170_cmd_tx_status {
__le16 unkn;
u8 dst[ETH_ALEN];
__le32 rate;
__le16 status;
} __packed;
#define AR9170_TX_STATUS_COMPLETE 0x00
#define AR9170_TX_STATUS_RETRY 0x01
#define AR9170_TX_STATUS_FAILED 0x02
struct ar9170_cmd_ba_failed_count {
__le16 failed;
__le16 rate;
} __packed;
struct ar9170_cmd_response {
u8 flag;
u8 type;
union {
struct ar9170_cmd_tx_status tx_status;
struct ar9170_cmd_ba_failed_count ba_fail_cnt;
u8 data[0];
};
} __packed;
/* QoS */
/* mac80211 queue to HW/FW map */
static const u8 ar9170_qos_hwmap[4] = { 3, 2, 0, 1 };
/* HW/FW queue to mac80211 map */
static const u8 ar9170_qos_mac80211map[4] = { 2, 3, 1, 0 };
enum ar9170_txq {
AR9170_TXQ_BE,
AR9170_TXQ_BK,
AR9170_TXQ_VI,
AR9170_TXQ_VO,
__AR9170_NUM_TXQ,
};
#endif /* __AR9170_HW_H */

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/*
* Atheros AR9170 driver
*
* LED handling
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "ar9170.h"
#include "cmd.h"
int ar9170_set_leds_state(struct ar9170 *ar, u32 led_state)
{
return ar9170_write_reg(ar, AR9170_GPIO_REG_DATA, led_state);
}
int ar9170_init_leds(struct ar9170 *ar)
{
int err;
/* disable LEDs */
/* GPIO [0/1 mode: output, 2/3: input] */
err = ar9170_write_reg(ar, AR9170_GPIO_REG_PORT_TYPE, 3);
if (err)
goto out;
/* GPIO 0/1 value: off */
err = ar9170_set_leds_state(ar, 0);
out:
return err;
}
#ifdef CONFIG_AR9170_LEDS
static void ar9170_update_leds(struct work_struct *work)
{
struct ar9170 *ar = container_of(work, struct ar9170, led_work.work);
int i, tmp, blink_delay = 1000;
u32 led_val = 0;
bool rerun = false;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return ;
mutex_lock(&ar->mutex);
for (i = 0; i < AR9170_NUM_LEDS; i++)
if (ar->leds[i].toggled) {
led_val |= 1 << i;
tmp = 70 + 200 / (ar->leds[i].toggled);
if (tmp < blink_delay)
blink_delay = tmp;
if (ar->leds[i].toggled > 1)
ar->leds[i].toggled = 0;
rerun = true;
}
ar9170_set_leds_state(ar, led_val);
mutex_unlock(&ar->mutex);
if (rerun)
queue_delayed_work(ar->hw->workqueue, &ar->led_work,
msecs_to_jiffies(blink_delay));
}
static void ar9170_led_brightness_set(struct led_classdev *led,
enum led_brightness brightness)
{
struct ar9170_led *arl = container_of(led, struct ar9170_led, l);
struct ar9170 *ar = arl->ar;
arl->toggled++;
if (likely(IS_ACCEPTING_CMD(ar) && brightness))
queue_delayed_work(ar->hw->workqueue, &ar->led_work, HZ/10);
}
static int ar9170_register_led(struct ar9170 *ar, int i, char *name,
char *trigger)
{
int err;
snprintf(ar->leds[i].name, sizeof(ar->leds[i].name),
"ar9170-%s::%s", wiphy_name(ar->hw->wiphy), name);
ar->leds[i].ar = ar;
ar->leds[i].l.name = ar->leds[i].name;
ar->leds[i].l.brightness_set = ar9170_led_brightness_set;
ar->leds[i].l.brightness = 0;
ar->leds[i].l.default_trigger = trigger;
err = led_classdev_register(wiphy_dev(ar->hw->wiphy),
&ar->leds[i].l);
if (err)
printk(KERN_ERR "%s: failed to register %s LED (%d).\n",
wiphy_name(ar->hw->wiphy), ar->leds[i].name, err);
else
ar->leds[i].registered = true;
return err;
}
void ar9170_unregister_leds(struct ar9170 *ar)
{
int i;
cancel_delayed_work_sync(&ar->led_work);
for (i = 0; i < AR9170_NUM_LEDS; i++)
if (ar->leds[i].registered) {
led_classdev_unregister(&ar->leds[i].l);
ar->leds[i].registered = false;
}
}
int ar9170_register_leds(struct ar9170 *ar)
{
int err;
INIT_DELAYED_WORK(&ar->led_work, ar9170_update_leds);
err = ar9170_register_led(ar, 0, "tx",
ieee80211_get_tx_led_name(ar->hw));
if (err)
goto fail;
err = ar9170_register_led(ar, 1, "assoc",
ieee80211_get_assoc_led_name(ar->hw));
if (err)
goto fail;
return 0;
fail:
ar9170_unregister_leds(ar);
return err;
}
#endif /* CONFIG_AR9170_LEDS */

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/*
* Atheros AR9170 driver
*
* MAC programming
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "ar9170.h"
#include "cmd.h"
int ar9170_set_qos(struct ar9170 *ar)
{
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_AC0_CW, ar->edcf[0].cw_min |
(ar->edcf[0].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC1_CW, ar->edcf[1].cw_min |
(ar->edcf[1].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC2_CW, ar->edcf[2].cw_min |
(ar->edcf[2].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC3_CW, ar->edcf[3].cw_min |
(ar->edcf[3].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC4_CW, ar->edcf[4].cw_min |
(ar->edcf[4].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_AIFS,
((ar->edcf[0].aifs * 9 + 10)) |
((ar->edcf[1].aifs * 9 + 10) << 12) |
((ar->edcf[2].aifs * 9 + 10) << 24));
ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_AIFS,
((ar->edcf[2].aifs * 9 + 10) >> 8) |
((ar->edcf[3].aifs * 9 + 10) << 4) |
((ar->edcf[4].aifs * 9 + 10) << 16));
ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP,
ar->edcf[0].txop | ar->edcf[1].txop << 16);
ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP,
ar->edcf[1].txop | ar->edcf[3].txop << 16);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_init_mac(struct ar9170 *ar)
{
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION, 0x40);
ar9170_regwrite(AR9170_MAC_REG_RETRY_MAX, 0);
/* enable MMIC */
ar9170_regwrite(AR9170_MAC_REG_SNIFFER,
AR9170_MAC_REG_SNIFFER_DEFAULTS);
ar9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD, 0xc1f80);
ar9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY, 0x70);
ar9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS, 0xa144000);
ar9170_regwrite(AR9170_MAC_REG_SLOT_TIME, 9 << 10);
/* CF-END mode */
ar9170_regwrite(0x1c3b2c, 0x19000000);
/* NAV protects ACK only (in TXOP) */
ar9170_regwrite(0x1c3b38, 0x201);
/* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
/* OTUS set AM to 0x1 */
ar9170_regwrite(AR9170_MAC_REG_BCN_HT1, 0x8000170);
ar9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105);
/* AGG test code*/
/* Aggregation MAX number and timeout */
ar9170_regwrite(0x1c3b9c, 0x10000a);
ar9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
AR9170_MAC_REG_FTF_DEFAULTS);
/* Enable deaggregator, response in sniffer mode */
ar9170_regwrite(0x1c3c40, 0x1 | 1<<30);
/* rate sets */
ar9170_regwrite(AR9170_MAC_REG_BASIC_RATE, 0x150f);
ar9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, 0x150f);
ar9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
/* MIMO response control */
ar9170_regwrite(0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */
/* switch MAC to OTUS interface */
ar9170_regwrite(0x1c3600, 0x3);
ar9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH, 0xffff);
/* set PHY register read timeout (??) */
ar9170_regwrite(AR9170_MAC_REG_MISC_680, 0xf00008);
/* Disable Rx TimeOut, workaround for BB. */
ar9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT, 0x0);
/* Set CPU clock frequency to 88/80MHz */
ar9170_regwrite(AR9170_PWR_REG_CLOCK_SEL,
AR9170_PWR_CLK_AHB_80_88MHZ |
AR9170_PWR_CLK_DAC_160_INV_DLY);
/* Set WLAN DMA interrupt mode: generate int per packet */
ar9170_regwrite(AR9170_MAC_REG_TXRX_MPI, 0x110011);
ar9170_regwrite(AR9170_MAC_REG_FCS_SELECT,
AR9170_MAC_FCS_FIFO_PROT);
/* Disables the CF_END frame, undocumented register */
ar9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND,
0x141E0F48);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
static int ar9170_set_mac_reg(struct ar9170 *ar, const u32 reg, const u8 *mac)
{
static const u8 zero[ETH_ALEN] = { 0 };
if (!mac)
mac = zero;
ar9170_regwrite_begin(ar);
ar9170_regwrite(reg,
(mac[3] << 24) | (mac[2] << 16) |
(mac[1] << 8) | mac[0]);
ar9170_regwrite(reg + 4, (mac[5] << 8) | mac[4]);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_update_multicast(struct ar9170 *ar)
{
int err;
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H,
ar->want_mc_hash >> 32);
ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L,
ar->want_mc_hash);
ar9170_regwrite_finish();
err = ar9170_regwrite_result();
if (err)
return err;
ar->cur_mc_hash = ar->want_mc_hash;
return 0;
}
int ar9170_update_frame_filter(struct ar9170 *ar)
{
int err;
err = ar9170_write_reg(ar, AR9170_MAC_REG_FRAMETYPE_FILTER,
ar->want_filter);
if (err)
return err;
ar->cur_filter = ar->want_filter;
return 0;
}
static int ar9170_set_promiscouous(struct ar9170 *ar)
{
u32 encr_mode, sniffer;
int err;
err = ar9170_read_reg(ar, AR9170_MAC_REG_SNIFFER, &sniffer);
if (err)
return err;
err = ar9170_read_reg(ar, AR9170_MAC_REG_ENCRYPTION, &encr_mode);
if (err)
return err;
if (ar->sniffer_enabled) {
sniffer |= AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC;
/*
* Rx decryption works in place.
*
* If we don't disable it, the hardware will render all
* encrypted frames which are encrypted with an unknown
* key useless.
*/
encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
ar->sniffer_enabled = true;
} else {
sniffer &= ~AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC;
if (ar->rx_software_decryption)
encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
else
encr_mode &= ~AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
}
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_ENCRYPTION, encr_mode);
ar9170_regwrite(AR9170_MAC_REG_SNIFFER, sniffer);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_set_operating_mode(struct ar9170 *ar)
{
u32 pm_mode = AR9170_MAC_REG_POWERMGT_DEFAULTS;
u8 *mac_addr, *bssid;
int err;
if (ar->vif) {
mac_addr = ar->mac_addr;
bssid = ar->bssid;
switch (ar->vif->type) {
case NL80211_IFTYPE_MESH_POINT:
case NL80211_IFTYPE_ADHOC:
pm_mode |= AR9170_MAC_REG_POWERMGT_IBSS;
break;
/* case NL80211_IFTYPE_AP:
pm_mode |= AR9170_MAC_REG_POWERMGT_AP;
break;*/
case NL80211_IFTYPE_WDS:
pm_mode |= AR9170_MAC_REG_POWERMGT_AP_WDS;
break;
case NL80211_IFTYPE_MONITOR:
ar->sniffer_enabled = true;
ar->rx_software_decryption = true;
break;
default:
pm_mode |= AR9170_MAC_REG_POWERMGT_STA;
break;
}
} else {
mac_addr = NULL;
bssid = NULL;
}
err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_MAC_ADDR_L, mac_addr);
if (err)
return err;
err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_BSSID_L, bssid);
if (err)
return err;
err = ar9170_set_promiscouous(ar);
if (err)
return err;
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_POWERMANAGEMENT, pm_mode);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_set_hwretry_limit(struct ar9170 *ar, unsigned int max_retry)
{
u32 tmp = min_t(u32, 0x33333, max_retry * 0x11111);
return ar9170_write_reg(ar, AR9170_MAC_REG_RETRY_MAX, tmp);
}
int ar9170_set_beacon_timers(struct ar9170 *ar)
{
u32 v = 0;
u32 pretbtt = 0;
v |= ar->hw->conf.beacon_int;
if (ar->vif) {
switch (ar->vif->type) {
case NL80211_IFTYPE_MESH_POINT:
case NL80211_IFTYPE_ADHOC:
v |= BIT(25);
break;
case NL80211_IFTYPE_AP:
v |= BIT(24);
pretbtt = (ar->hw->conf.beacon_int - 6) << 16;
break;
default:
break;
}
v |= ar->vif->bss_conf.dtim_period << 16;
}
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_PRETBTT, pretbtt);
ar9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_update_beacon(struct ar9170 *ar)
{
struct sk_buff *skb;
__le32 *data, *old = NULL;
u32 word;
int i;
skb = ieee80211_beacon_get(ar->hw, ar->vif);
if (!skb)
return -ENOMEM;
data = (__le32 *)skb->data;
if (ar->beacon)
old = (__le32 *)ar->beacon->data;
ar9170_regwrite_begin(ar);
for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) {
/*
* XXX: This accesses beyond skb data for up
* to the last 3 bytes!!
*/
if (old && (data[i] == old[i]))
continue;
word = le32_to_cpu(data[i]);
ar9170_regwrite(AR9170_BEACON_BUFFER_ADDRESS + 4 * i, word);
}
/* XXX: use skb->cb info */
if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ)
ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP,
((skb->len + 4) << (3+16)) + 0x0400);
else
ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP,
((skb->len + 4) << (3+16)) + 0x0400);
ar9170_regwrite(AR9170_MAC_REG_BCN_LENGTH, skb->len + 4);
ar9170_regwrite(AR9170_MAC_REG_BCN_ADDR, AR9170_BEACON_BUFFER_ADDRESS);
ar9170_regwrite(AR9170_MAC_REG_BCN_CTRL, 1);
ar9170_regwrite_finish();
dev_kfree_skb(ar->beacon);
ar->beacon = skb;
return ar9170_regwrite_result();
}
void ar9170_new_beacon(struct work_struct *work)
{
struct ar9170 *ar = container_of(work, struct ar9170,
beacon_work);
struct sk_buff *skb;
if (unlikely(!IS_STARTED(ar)))
return ;
mutex_lock(&ar->mutex);
if (!ar->vif)
goto out;
ar9170_update_beacon(ar);
rcu_read_lock();
while ((skb = ieee80211_get_buffered_bc(ar->hw, ar->vif)))
ar9170_op_tx(ar->hw, skb);
rcu_read_unlock();
out:
mutex_unlock(&ar->mutex);
}
int ar9170_upload_key(struct ar9170 *ar, u8 id, const u8 *mac, u8 ktype,
u8 keyidx, u8 *keydata, int keylen)
{
__le32 vals[7];
static const u8 bcast[ETH_ALEN] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
u8 dummy;
mac = mac ? : bcast;
vals[0] = cpu_to_le32((keyidx << 16) + id);
vals[1] = cpu_to_le32(mac[1] << 24 | mac[0] << 16 | ktype);
vals[2] = cpu_to_le32(mac[5] << 24 | mac[4] << 16 |
mac[3] << 8 | mac[2]);
memset(&vals[3], 0, 16);
if (keydata)
memcpy(&vals[3], keydata, keylen);
return ar->exec_cmd(ar, AR9170_CMD_EKEY,
sizeof(vals), (u8 *)vals,
1, &dummy);
}
int ar9170_disable_key(struct ar9170 *ar, u8 id)
{
__le32 val = cpu_to_le32(id);
u8 dummy;
return ar->exec_cmd(ar, AR9170_CMD_EKEY,
sizeof(val), (u8 *)&val,
1, &dummy);
}

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@@ -0,0 +1,748 @@
/*
* Atheros AR9170 driver
*
* USB - frontend
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
* Copyright 2009, Christian Lamparter <chunkeey@web.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/module.h>
#include <linux/usb.h>
#include <linux/firmware.h>
#include <linux/etherdevice.h>
#include <net/mac80211.h>
#include "ar9170.h"
#include "cmd.h"
#include "hw.h"
#include "usb.h"
MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Atheros AR9170 802.11n USB wireless");
MODULE_FIRMWARE("ar9170-1.fw");
MODULE_FIRMWARE("ar9170-2.fw");
static struct usb_device_id ar9170_usb_ids[] = {
/* Atheros 9170 */
{ USB_DEVICE(0x0cf3, 0x9170) },
/* Atheros TG121N */
{ USB_DEVICE(0x0cf3, 0x1001) },
/* D-Link DWA 160A */
{ USB_DEVICE(0x07d1, 0x3c10) },
/* Netgear WNDA3100 */
{ USB_DEVICE(0x0846, 0x9010) },
/* Netgear WN111 v2 */
{ USB_DEVICE(0x0846, 0x9001) },
/* Zydas ZD1221 */
{ USB_DEVICE(0x0ace, 0x1221) },
/* Z-Com UB81 BG */
{ USB_DEVICE(0x0cde, 0x0023) },
/* Z-Com UB82 ABG */
{ USB_DEVICE(0x0cde, 0x0026) },
/* Arcadyan WN7512 */
{ USB_DEVICE(0x083a, 0xf522) },
/* Planex GWUS300 */
{ USB_DEVICE(0x2019, 0x5304) },
/* IO-Data WNGDNUS2 */
{ USB_DEVICE(0x04bb, 0x093f) },
/* terminate */
{}
};
MODULE_DEVICE_TABLE(usb, ar9170_usb_ids);
static void ar9170_usb_tx_urb_complete_free(struct urb *urb)
{
struct sk_buff *skb = urb->context;
struct ar9170_usb *aru = (struct ar9170_usb *)
usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
if (!aru) {
dev_kfree_skb_irq(skb);
return ;
}
ar9170_handle_tx_status(&aru->common, skb, false,
AR9170_TX_STATUS_COMPLETE);
}
static void ar9170_usb_tx_urb_complete(struct urb *urb)
{
}
static void ar9170_usb_irq_completed(struct urb *urb)
{
struct ar9170_usb *aru = urb->context;
switch (urb->status) {
/* everything is fine */
case 0:
break;
/* disconnect */
case -ENOENT:
case -ECONNRESET:
case -ENODEV:
case -ESHUTDOWN:
goto free;
default:
goto resubmit;
}
print_hex_dump_bytes("ar9170 irq: ", DUMP_PREFIX_OFFSET,
urb->transfer_buffer, urb->actual_length);
resubmit:
usb_anchor_urb(urb, &aru->rx_submitted);
if (usb_submit_urb(urb, GFP_ATOMIC)) {
usb_unanchor_urb(urb);
goto free;
}
return;
free:
usb_buffer_free(aru->udev, 64, urb->transfer_buffer, urb->transfer_dma);
}
static void ar9170_usb_rx_completed(struct urb *urb)
{
struct sk_buff *skb = urb->context;
struct ar9170_usb *aru = (struct ar9170_usb *)
usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
int err;
if (!aru)
goto free;
switch (urb->status) {
/* everything is fine */
case 0:
break;
/* disconnect */
case -ENOENT:
case -ECONNRESET:
case -ENODEV:
case -ESHUTDOWN:
goto free;
default:
goto resubmit;
}
skb_put(skb, urb->actual_length);
ar9170_rx(&aru->common, skb);
resubmit:
skb_reset_tail_pointer(skb);
skb_trim(skb, 0);
usb_anchor_urb(urb, &aru->rx_submitted);
err = usb_submit_urb(urb, GFP_ATOMIC);
if (err) {
usb_unanchor_urb(urb);
dev_kfree_skb_irq(skb);
}
return ;
free:
dev_kfree_skb_irq(skb);
return;
}
static int ar9170_usb_prep_rx_urb(struct ar9170_usb *aru,
struct urb *urb, gfp_t gfp)
{
struct sk_buff *skb;
skb = __dev_alloc_skb(AR9170_MAX_RX_BUFFER_SIZE + 32, gfp);
if (!skb)
return -ENOMEM;
/* reserve some space for mac80211's radiotap */
skb_reserve(skb, 32);
usb_fill_bulk_urb(urb, aru->udev,
usb_rcvbulkpipe(aru->udev, AR9170_EP_RX),
skb->data, min(skb_tailroom(skb),
AR9170_MAX_RX_BUFFER_SIZE),
ar9170_usb_rx_completed, skb);
return 0;
}
static int ar9170_usb_alloc_rx_irq_urb(struct ar9170_usb *aru)
{
struct urb *urb = NULL;
void *ibuf;
int err = -ENOMEM;
/* initialize interrupt endpoint */
urb = usb_alloc_urb(0, GFP_KERNEL);
if (!urb)
goto out;
ibuf = usb_buffer_alloc(aru->udev, 64, GFP_KERNEL, &urb->transfer_dma);
if (!ibuf)
goto out;
usb_fill_int_urb(urb, aru->udev,
usb_rcvintpipe(aru->udev, AR9170_EP_IRQ), ibuf,
64, ar9170_usb_irq_completed, aru, 1);
urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
usb_anchor_urb(urb, &aru->rx_submitted);
err = usb_submit_urb(urb, GFP_KERNEL);
if (err) {
usb_unanchor_urb(urb);
usb_buffer_free(aru->udev, 64, urb->transfer_buffer,
urb->transfer_dma);
}
out:
usb_free_urb(urb);
return err;
}
static int ar9170_usb_alloc_rx_bulk_urbs(struct ar9170_usb *aru)
{
struct urb *urb;
int i;
int err = -EINVAL;
for (i = 0; i < AR9170_NUM_RX_URBS; i++) {
err = -ENOMEM;
urb = usb_alloc_urb(0, GFP_KERNEL);
if (!urb)
goto err_out;
err = ar9170_usb_prep_rx_urb(aru, urb, GFP_KERNEL);
if (err) {
usb_free_urb(urb);
goto err_out;
}
usb_anchor_urb(urb, &aru->rx_submitted);
err = usb_submit_urb(urb, GFP_KERNEL);
if (err) {
usb_unanchor_urb(urb);
dev_kfree_skb_any((void *) urb->transfer_buffer);
usb_free_urb(urb);
goto err_out;
}
usb_free_urb(urb);
}
/* the device now waiting for a firmware. */
aru->common.state = AR9170_IDLE;
return 0;
err_out:
usb_kill_anchored_urbs(&aru->rx_submitted);
return err;
}
static void ar9170_usb_cancel_urbs(struct ar9170_usb *aru)
{
int ret;
aru->common.state = AR9170_UNKNOWN_STATE;
usb_unlink_anchored_urbs(&aru->tx_submitted);
/* give the LED OFF command and the deauth frame a chance to air. */
ret = usb_wait_anchor_empty_timeout(&aru->tx_submitted,
msecs_to_jiffies(100));
if (ret == 0)
dev_err(&aru->udev->dev, "kill pending tx urbs.\n");
usb_poison_anchored_urbs(&aru->tx_submitted);
usb_poison_anchored_urbs(&aru->rx_submitted);
}
static int ar9170_usb_exec_cmd(struct ar9170 *ar, enum ar9170_cmd cmd,
unsigned int plen, void *payload,
unsigned int outlen, void *out)
{
struct ar9170_usb *aru = (void *) ar;
struct urb *urb = NULL;
unsigned long flags;
int err = -ENOMEM;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return -EPERM;
if (WARN_ON(plen > AR9170_MAX_CMD_LEN - 4))
return -EINVAL;
urb = usb_alloc_urb(0, GFP_ATOMIC);
if (unlikely(!urb))
goto err_free;
ar->cmdbuf[0] = cpu_to_le32(plen);
ar->cmdbuf[0] |= cpu_to_le32(cmd << 8);
/* writing multiple regs fills this buffer already */
if (plen && payload != (u8 *)(&ar->cmdbuf[1]))
memcpy(&ar->cmdbuf[1], payload, plen);
spin_lock_irqsave(&aru->common.cmdlock, flags);
aru->readbuf = (u8 *)out;
aru->readlen = outlen;
spin_unlock_irqrestore(&aru->common.cmdlock, flags);
usb_fill_int_urb(urb, aru->udev,
usb_sndbulkpipe(aru->udev, AR9170_EP_CMD),
aru->common.cmdbuf, plen + 4,
ar9170_usb_tx_urb_complete, NULL, 1);
usb_anchor_urb(urb, &aru->tx_submitted);
err = usb_submit_urb(urb, GFP_ATOMIC);
if (err) {
usb_unanchor_urb(urb);
usb_free_urb(urb);
goto err_unbuf;
}
usb_free_urb(urb);
err = wait_for_completion_timeout(&aru->cmd_wait, HZ);
if (err == 0) {
err = -ETIMEDOUT;
goto err_unbuf;
}
if (outlen >= 0 && aru->readlen != outlen) {
err = -EMSGSIZE;
goto err_unbuf;
}
return 0;
err_unbuf:
/* Maybe the device was removed in the second we were waiting? */
if (IS_STARTED(ar)) {
dev_err(&aru->udev->dev, "no command feedback "
"received (%d).\n", err);
/* provide some maybe useful debug information */
print_hex_dump_bytes("ar9170 cmd: ", DUMP_PREFIX_NONE,
aru->common.cmdbuf, plen + 4);
dump_stack();
}
/* invalidate to avoid completing the next prematurely */
spin_lock_irqsave(&aru->common.cmdlock, flags);
aru->readbuf = NULL;
aru->readlen = 0;
spin_unlock_irqrestore(&aru->common.cmdlock, flags);
err_free:
return err;
}
static int ar9170_usb_tx(struct ar9170 *ar, struct sk_buff *skb,
bool txstatus_needed, unsigned int extra_len)
{
struct ar9170_usb *aru = (struct ar9170_usb *) ar;
struct urb *urb;
int err;
if (unlikely(!IS_STARTED(ar))) {
/* Seriously, what were you drink... err... thinking!? */
return -EPERM;
}
urb = usb_alloc_urb(0, GFP_ATOMIC);
if (unlikely(!urb))
return -ENOMEM;
usb_fill_bulk_urb(urb, aru->udev,
usb_sndbulkpipe(aru->udev, AR9170_EP_TX),
skb->data, skb->len + extra_len, (txstatus_needed ?
ar9170_usb_tx_urb_complete :
ar9170_usb_tx_urb_complete_free), skb);
urb->transfer_flags |= URB_ZERO_PACKET;
usb_anchor_urb(urb, &aru->tx_submitted);
err = usb_submit_urb(urb, GFP_ATOMIC);
if (unlikely(err))
usb_unanchor_urb(urb);
usb_free_urb(urb);
return err;
}
static void ar9170_usb_callback_cmd(struct ar9170 *ar, u32 len , void *buffer)
{
struct ar9170_usb *aru = (void *) ar;
unsigned long flags;
u32 in, out;
if (!buffer)
return ;
in = le32_to_cpup((__le32 *)buffer);
out = le32_to_cpu(ar->cmdbuf[0]);
/* mask off length byte */
out &= ~0xFF;
if (aru->readlen >= 0) {
/* add expected length */
out |= aru->readlen;
} else {
/* add obtained length */
out |= in & 0xFF;
}
/*
* Some commands (e.g: AR9170_CMD_FREQUENCY) have a variable response
* length and we cannot predict the correct length in advance.
* So we only check if we provided enough space for the data.
*/
if (unlikely(out < in)) {
dev_warn(&aru->udev->dev, "received invalid command response "
"got %d bytes, instead of %d bytes "
"and the resp length is %d bytes\n",
in, out, len);
print_hex_dump_bytes("ar9170 invalid resp: ",
DUMP_PREFIX_OFFSET, buffer, len);
/*
* Do not complete, then the command times out,
* and we get a stack trace from there.
*/
return ;
}
spin_lock_irqsave(&aru->common.cmdlock, flags);
if (aru->readbuf && len > 0) {
memcpy(aru->readbuf, buffer + 4, len - 4);
aru->readbuf = NULL;
}
complete(&aru->cmd_wait);
spin_unlock_irqrestore(&aru->common.cmdlock, flags);
}
static int ar9170_usb_upload(struct ar9170_usb *aru, const void *data,
size_t len, u32 addr, bool complete)
{
int transfer, err;
u8 *buf = kmalloc(4096, GFP_KERNEL);
if (!buf)
return -ENOMEM;
while (len) {
transfer = min_t(int, len, 4096);
memcpy(buf, data, transfer);
err = usb_control_msg(aru->udev, usb_sndctrlpipe(aru->udev, 0),
0x30 /* FW DL */, 0x40 | USB_DIR_OUT,
addr >> 8, 0, buf, transfer, 1000);
if (err < 0) {
kfree(buf);
return err;
}
len -= transfer;
data += transfer;
addr += transfer;
}
kfree(buf);
if (complete) {
err = usb_control_msg(aru->udev, usb_sndctrlpipe(aru->udev, 0),
0x31 /* FW DL COMPLETE */,
0x40 | USB_DIR_OUT, 0, 0, NULL, 0, 5000);
}
return 0;
}
static int ar9170_usb_request_firmware(struct ar9170_usb *aru)
{
int err = 0;
err = request_firmware(&aru->init_values, "ar9170-1.fw",
&aru->udev->dev);
if (err) {
dev_err(&aru->udev->dev, "file with init values not found.\n");
return err;
}
err = request_firmware(&aru->firmware, "ar9170-2.fw", &aru->udev->dev);
if (err) {
release_firmware(aru->init_values);
dev_err(&aru->udev->dev, "firmware file not found.\n");
return err;
}
return err;
}
static int ar9170_usb_reset(struct ar9170_usb *aru)
{
int ret, lock = (aru->intf->condition != USB_INTERFACE_BINDING);
if (lock) {
ret = usb_lock_device_for_reset(aru->udev, aru->intf);
if (ret < 0) {
dev_err(&aru->udev->dev, "unable to lock device "
"for reset (%d).\n", ret);
return ret;
}
}
ret = usb_reset_device(aru->udev);
if (lock)
usb_unlock_device(aru->udev);
/* let it rest - for a second - */
msleep(1000);
return ret;
}
static int ar9170_usb_upload_firmware(struct ar9170_usb *aru)
{
int err;
/* First, upload initial values to device RAM */
err = ar9170_usb_upload(aru, aru->init_values->data,
aru->init_values->size, 0x102800, false);
if (err) {
dev_err(&aru->udev->dev, "firmware part 1 "
"upload failed (%d).\n", err);
return err;
}
/* Then, upload the firmware itself and start it */
return ar9170_usb_upload(aru, aru->firmware->data, aru->firmware->size,
0x200000, true);
}
static int ar9170_usb_init_transport(struct ar9170_usb *aru)
{
struct ar9170 *ar = (void *) &aru->common;
int err;
ar9170_regwrite_begin(ar);
/* Set USB Rx stream mode MAX packet number to 2 */
ar9170_regwrite(AR9170_USB_REG_MAX_AGG_UPLOAD, 0x4);
/* Set USB Rx stream mode timeout to 10us */
ar9170_regwrite(AR9170_USB_REG_UPLOAD_TIME_CTL, 0x80);
ar9170_regwrite_finish();
err = ar9170_regwrite_result();
if (err)
dev_err(&aru->udev->dev, "USB setup failed (%d).\n", err);
return err;
}
static void ar9170_usb_stop(struct ar9170 *ar)
{
struct ar9170_usb *aru = (void *) ar;
int ret;
if (IS_ACCEPTING_CMD(ar))
aru->common.state = AR9170_STOPPED;
/* lets wait a while until the tx - queues are dried out */
ret = usb_wait_anchor_empty_timeout(&aru->tx_submitted,
msecs_to_jiffies(1000));
if (ret == 0)
dev_err(&aru->udev->dev, "kill pending tx urbs.\n");
usb_poison_anchored_urbs(&aru->tx_submitted);
/*
* Note:
* So far we freed all tx urbs, but we won't dare to touch any rx urbs.
* Else we would end up with a unresponsive device...
*/
}
static int ar9170_usb_open(struct ar9170 *ar)
{
struct ar9170_usb *aru = (void *) ar;
int err;
usb_unpoison_anchored_urbs(&aru->tx_submitted);
err = ar9170_usb_init_transport(aru);
if (err) {
usb_poison_anchored_urbs(&aru->tx_submitted);
return err;
}
aru->common.state = AR9170_IDLE;
return 0;
}
static int ar9170_usb_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
struct ar9170_usb *aru;
struct ar9170 *ar;
struct usb_device *udev;
int err;
aru = ar9170_alloc(sizeof(*aru));
if (IS_ERR(aru)) {
err = PTR_ERR(aru);
goto out;
}
udev = interface_to_usbdev(intf);
usb_get_dev(udev);
aru->udev = udev;
aru->intf = intf;
ar = &aru->common;
usb_set_intfdata(intf, aru);
SET_IEEE80211_DEV(ar->hw, &udev->dev);
init_usb_anchor(&aru->rx_submitted);
init_usb_anchor(&aru->tx_submitted);
init_completion(&aru->cmd_wait);
aru->common.stop = ar9170_usb_stop;
aru->common.open = ar9170_usb_open;
aru->common.tx = ar9170_usb_tx;
aru->common.exec_cmd = ar9170_usb_exec_cmd;
aru->common.callback_cmd = ar9170_usb_callback_cmd;
err = ar9170_usb_reset(aru);
if (err)
goto err_unlock;
err = ar9170_usb_request_firmware(aru);
if (err)
goto err_unlock;
err = ar9170_usb_alloc_rx_irq_urb(aru);
if (err)
goto err_freefw;
err = ar9170_usb_alloc_rx_bulk_urbs(aru);
if (err)
goto err_unrx;
err = ar9170_usb_upload_firmware(aru);
if (err) {
err = ar9170_echo_test(&aru->common, 0x60d43110);
if (err) {
/* force user invention, by disabling the device */
err = usb_driver_set_configuration(aru->udev, -1);
dev_err(&aru->udev->dev, "device is in a bad state. "
"please reconnect it!\n");
goto err_unrx;
}
}
err = ar9170_usb_open(ar);
if (err)
goto err_unrx;
err = ar9170_register(ar, &udev->dev);
ar9170_usb_stop(ar);
if (err)
goto err_unrx;
return 0;
err_unrx:
ar9170_usb_cancel_urbs(aru);
err_freefw:
release_firmware(aru->init_values);
release_firmware(aru->firmware);
err_unlock:
usb_set_intfdata(intf, NULL);
usb_put_dev(udev);
ieee80211_free_hw(ar->hw);
out:
return err;
}
static void ar9170_usb_disconnect(struct usb_interface *intf)
{
struct ar9170_usb *aru = usb_get_intfdata(intf);
if (!aru)
return;
aru->common.state = AR9170_IDLE;
ar9170_unregister(&aru->common);
ar9170_usb_cancel_urbs(aru);
release_firmware(aru->init_values);
release_firmware(aru->firmware);
usb_put_dev(aru->udev);
usb_set_intfdata(intf, NULL);
ieee80211_free_hw(aru->common.hw);
}
static struct usb_driver ar9170_driver = {
.name = "ar9170usb",
.probe = ar9170_usb_probe,
.disconnect = ar9170_usb_disconnect,
.id_table = ar9170_usb_ids,
.soft_unbind = 1,
};
static int __init ar9170_init(void)
{
return usb_register(&ar9170_driver);
}
static void __exit ar9170_exit(void)
{
usb_deregister(&ar9170_driver);
}
module_init(ar9170_init);
module_exit(ar9170_exit);

查看文件

@@ -0,0 +1,74 @@
/*
* Atheros AR9170 USB driver
*
* Driver specific definitions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
* Copyright 2009, Christian Lamparter <chunkeey@web.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __USB_H
#define __USB_H
#include <linux/usb.h>
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <linux/leds.h>
#include <net/wireless.h>
#include <net/mac80211.h>
#include <linux/firmware.h>
#include "eeprom.h"
#include "hw.h"
#include "ar9170.h"
#define AR9170_NUM_RX_URBS 16
struct firmware;
struct ar9170_usb {
struct ar9170 common;
struct usb_device *udev;
struct usb_interface *intf;
struct usb_anchor rx_submitted;
struct usb_anchor tx_submitted;
spinlock_t cmdlock;
struct completion cmd_wait;
int readlen;
u8 *readbuf;
const struct firmware *init_values;
const struct firmware *firmware;
};
#endif /* __USB_H */

查看文件

@@ -1030,7 +1030,17 @@ static int arlan_mac_addr(struct net_device *dev, void *p)
return 0;
}
static const struct net_device_ops arlan_netdev_ops = {
.ndo_open = arlan_open,
.ndo_stop = arlan_close,
.ndo_start_xmit = arlan_tx,
.ndo_get_stats = arlan_statistics,
.ndo_set_multicast_list = arlan_set_multicast,
.ndo_change_mtu = arlan_change_mtu,
.ndo_set_mac_address = arlan_mac_addr,
.ndo_tx_timeout = arlan_tx_timeout,
.ndo_validate_addr = eth_validate_addr,
};
static int __init arlan_setup_device(struct net_device *dev, int num)
{
@@ -1042,14 +1052,7 @@ static int __init arlan_setup_device(struct net_device *dev, int num)
ap->conf = (struct arlan_shmem *)(ap+1);
dev->tx_queue_len = tx_queue_len;
dev->open = arlan_open;
dev->stop = arlan_close;
dev->hard_start_xmit = arlan_tx;
dev->get_stats = arlan_statistics;
dev->set_multicast_list = arlan_set_multicast;
dev->change_mtu = arlan_change_mtu;
dev->set_mac_address = arlan_mac_addr;
dev->tx_timeout = arlan_tx_timeout;
dev->netdev_ops = &arlan_netdev_ops;
dev->watchdog_timeo = 3*HZ;
ap->irq_test_done = 0;

查看文件

@@ -204,9 +204,9 @@
#define AR5K_TUNE_CWMAX_11B 1023
#define AR5K_TUNE_CWMAX_XR 7
#define AR5K_TUNE_NOISE_FLOOR -72
#define AR5K_TUNE_MAX_TXPOWER 60
#define AR5K_TUNE_DEFAULT_TXPOWER 30
#define AR5K_TUNE_TPC_TXPOWER true
#define AR5K_TUNE_MAX_TXPOWER 63
#define AR5K_TUNE_DEFAULT_TXPOWER 25
#define AR5K_TUNE_TPC_TXPOWER false
#define AR5K_TUNE_ANT_DIVERSITY true
#define AR5K_TUNE_HWTXTRIES 4
@@ -551,11 +551,11 @@ enum ath5k_pkt_type {
*/
#define AR5K_TXPOWER_OFDM(_r, _v) ( \
((0 & 1) << ((_v) + 6)) | \
(((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
(((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
)
#define AR5K_TXPOWER_CCK(_r, _v) ( \
(ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
(ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
)
/*
@@ -1085,13 +1085,25 @@ struct ath5k_hw {
struct ath5k_gain ah_gain;
u8 ah_offset[AR5K_MAX_RF_BANKS];
struct {
u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
u16 txp_rates[AR5K_MAX_RATES];
s16 txp_min;
s16 txp_max;
/* Temporary tables used for interpolation */
u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
[AR5K_EEPROM_POWER_TABLE_SIZE];
u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
[AR5K_EEPROM_POWER_TABLE_SIZE];
u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
u16 txp_rates_power_table[AR5K_MAX_RATES];
u8 txp_min_idx;
bool txp_tpc;
/* Values in 0.25dB units */
s16 txp_min_pwr;
s16 txp_max_pwr;
s16 txp_offset;
s16 txp_ofdm;
/* Values in dB units */
s16 txp_cck_ofdm_pwr_delta;
s16 txp_cck_ofdm_gainf_delta;
} ah_txpower;
struct {
@@ -1161,6 +1173,7 @@ extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_l
/* EEPROM access functions */
extern int ath5k_eeprom_init(struct ath5k_hw *ah);
extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
@@ -1256,8 +1269,8 @@ extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
/* TX power setup */
extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int txpower);
extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower);
extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 ee_mode, u8 txpower);
/*
* Functions used internaly

查看文件

@@ -341,6 +341,8 @@ void ath5k_hw_detach(struct ath5k_hw *ah)
if (ah->ah_rf_banks != NULL)
kfree(ah->ah_rf_banks);
ath5k_eeprom_detach(ah);
/* assume interrupts are down */
kfree(ah);
}

查看文件

@@ -685,13 +685,6 @@ ath5k_pci_resume(struct pci_dev *pdev)
if (err)
return err;
/*
* Suspend/Resume resets the PCI configuration space, so we have to
* re-disable the RETRY_TIMEOUT register (0x41) to keep
* PCI Tx retries from interfering with C3 CPU state
*/
pci_write_config_byte(pdev, 0x41, 0);
err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
if (err) {
ATH5K_ERR(sc, "request_irq failed\n");
@@ -1095,9 +1088,18 @@ ath5k_mode_setup(struct ath5k_softc *sc)
static inline int
ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
{
WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
"hw_rix out of bounds: %x\n", hw_rix);
return sc->rate_idx[sc->curband->band][hw_rix];
int rix;
/* return base rate on errors */
if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
"hw_rix out of bounds: %x\n", hw_rix))
return 0;
rix = sc->rate_idx[sc->curband->band][hw_rix];
if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
rix = 0;
return rix;
}
/***************\
@@ -1216,6 +1218,9 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
pktlen = skb->len;
/* FIXME: If we are in g mode and rate is a CCK rate
* subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
* from tx power (value is in dB units already) */
if (info->control.hw_key) {
keyidx = info->control.hw_key->hw_key_idx;
pktlen += info->control.hw_key->icv_len;
@@ -2044,6 +2049,9 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
antenna = sc->bsent & 4 ? 2 : 1;
}
/* FIXME: If we are in g mode and rate is a CCK rate
* subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
* from tx power (value is in dB units already) */
ds->ds_data = bf->skbaddr;
ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
ieee80211_get_hdrlen_from_skb(skb),
@@ -2305,7 +2313,7 @@ ath5k_init(struct ath5k_softc *sc)
sc->curband = &sc->sbands[sc->curchan->band];
sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
AR5K_INT_FATAL | AR5K_INT_GLOBAL;
ret = ath5k_reset(sc, false, false);
if (ret)
goto done;
@@ -2554,7 +2562,7 @@ ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
if (skb_headroom(skb) < padsize) {
ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
" headroom to pad %d\n", hdrlen, padsize);
return NETDEV_TX_BUSY;
goto drop_packet;
}
skb_push(skb, padsize);
memmove(skb->data, skb->data+padsize, hdrlen);
@@ -2565,7 +2573,7 @@ ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
spin_unlock_irqrestore(&sc->txbuflock, flags);
ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
return NETDEV_TX_BUSY;
goto drop_packet;
}
bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
list_del(&bf->list);
@@ -2582,10 +2590,12 @@ ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
list_add_tail(&bf->list, &sc->txbuf);
sc->txbuf_len++;
spin_unlock_irqrestore(&sc->txbuflock, flags);
dev_kfree_skb_any(skb);
return NETDEV_TX_OK;
goto drop_packet;
}
return NETDEV_TX_OK;
drop_packet:
dev_kfree_skb_any(skb);
return NETDEV_TX_OK;
}
@@ -2608,12 +2618,6 @@ ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
goto err;
}
/*
* This is needed only to setup initial state
* but it's best done after a reset.
*/
ath5k_hw_set_txpower_limit(sc->ah, 0);
ret = ath5k_rx_start(sc);
if (ret) {
ATH5K_ERR(sc, "can't start recv logic\n");

查看文件

@@ -112,7 +112,7 @@ struct ath5k_softc {
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
struct ieee80211_channel channels[ATH_CHAN_MAX];
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
u8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
enum nl80211_iftype opmode;
struct ath5k_hw *ah; /* Atheros HW */

查看文件

@@ -194,6 +194,10 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
return -EINVAL;
}
tx_power += ah->ah_txpower.txp_offset;
if (tx_power > AR5K_TUNE_MAX_TXPOWER)
tx_power = AR5K_TUNE_MAX_TXPOWER;
/* Clear descriptor */
memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));

文件差异内容过多而无法显示 加载差异

查看文件

@@ -173,6 +173,7 @@
#define AR5K_EEPROM_N_5GHZ_CHAN 10
#define AR5K_EEPROM_N_2GHZ_CHAN 3
#define AR5K_EEPROM_N_2GHZ_CHAN_2413 4
#define AR5K_EEPROM_N_2GHZ_CHAN_MAX 4
#define AR5K_EEPROM_MAX_CHAN 10
#define AR5K_EEPROM_N_PWR_POINTS_5111 11
#define AR5K_EEPROM_N_PCDAC 11
@@ -193,7 +194,7 @@
#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
#define AR5K_EEPROM_MAX_CTLS 32
#define AR5K_EEPROM_N_XPD_PER_CHANNEL 4
#define AR5K_EEPROM_N_PD_CURVES 4
#define AR5K_EEPROM_N_XPD0_POINTS 4
#define AR5K_EEPROM_N_XPD3_POINTS 3
#define AR5K_EEPROM_N_PD_GAINS 4
@@ -232,7 +233,7 @@ enum ath5k_ctl_mode {
AR5K_CTL_11B = 1,
AR5K_CTL_11G = 2,
AR5K_CTL_TURBO = 3,
AR5K_CTL_108G = 4,
AR5K_CTL_TURBOG = 4,
AR5K_CTL_2GHT20 = 5,
AR5K_CTL_5GHT20 = 6,
AR5K_CTL_2GHT40 = 7,
@@ -240,65 +241,114 @@ enum ath5k_ctl_mode {
AR5K_CTL_MODE_M = 15,
};
/* Default CTL ids for the 3 main reg domains.
* Atheros only uses these by default but vendors
* can have up to 32 different CTLs for different
* scenarios. Note that theese values are ORed with
* the mode id (above) so we can have up to 24 CTL
* datasets out of these 3 main regdomains. That leaves
* 8 ids that can be used by vendors and since 0x20 is
* missing from HAL sources i guess this is the set of
* custom CTLs vendors can use. */
#define AR5K_CTL_FCC 0x10
#define AR5K_CTL_CUSTOM 0x20
#define AR5K_CTL_ETSI 0x30
#define AR5K_CTL_MKK 0x40
/* Indicates a CTL with only mode set and
* no reg domain mapping, such CTLs are used
* for world roaming domains or simply when
* a reg domain is not set */
#define AR5K_CTL_NO_REGDOMAIN 0xf0
/* Indicates an empty (invalid) CTL */
#define AR5K_CTL_NO_CTL 0xff
/* Per channel calibration data, used for power table setup */
struct ath5k_chan_pcal_info_rf5111 {
/* Power levels in half dbm units
* for one power curve. */
u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
/* PCDAC table steps
* for the above values */
u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
/* Starting PCDAC step */
u8 pcdac_min;
u8 pcdac_min;
/* Final PCDAC step */
u8 pcdac_max;
u8 pcdac_max;
};
struct ath5k_chan_pcal_info_rf5112 {
/* Power levels in quarter dBm units
* for lower (0) and higher (3)
* level curves */
s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
* level curves in 0.25dB units */
s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
/* PCDAC table steps
* for the above values */
u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
};
struct ath5k_chan_pcal_info_rf2413 {
/* Starting pwr/pddac values */
s8 pwr_i[AR5K_EEPROM_N_PD_GAINS];
u8 pddac_i[AR5K_EEPROM_N_PD_GAINS];
/* (pwr,pddac) points */
s8 pwr[AR5K_EEPROM_N_PD_GAINS]
[AR5K_EEPROM_N_PD_POINTS];
u8 pddac[AR5K_EEPROM_N_PD_GAINS]
[AR5K_EEPROM_N_PD_POINTS];
s8 pwr_i[AR5K_EEPROM_N_PD_GAINS];
u8 pddac_i[AR5K_EEPROM_N_PD_GAINS];
/* (pwr,pddac) points
* power levels in 0.5dB units */
s8 pwr[AR5K_EEPROM_N_PD_GAINS]
[AR5K_EEPROM_N_PD_POINTS];
u8 pddac[AR5K_EEPROM_N_PD_GAINS]
[AR5K_EEPROM_N_PD_POINTS];
};
enum ath5k_powertable_type {
AR5K_PWRTABLE_PWR_TO_PCDAC = 0,
AR5K_PWRTABLE_LINEAR_PCDAC = 1,
AR5K_PWRTABLE_PWR_TO_PDADC = 2,
};
struct ath5k_pdgain_info {
u8 pd_points;
u8 *pd_step;
/* Power values are in
* 0.25dB units */
s16 *pd_pwr;
};
struct ath5k_chan_pcal_info {
/* Frequency */
u16 freq;
/* Max available power */
s8 max_pwr;
/* Tx power boundaries */
s16 max_pwr;
s16 min_pwr;
union {
struct ath5k_chan_pcal_info_rf5111 rf5111_info;
struct ath5k_chan_pcal_info_rf5112 rf5112_info;
struct ath5k_chan_pcal_info_rf2413 rf2413_info;
};
/* Raw values used by phy code
* Curves are stored in order from lower
* gain to higher gain (max txpower -> min txpower) */
struct ath5k_pdgain_info *pd_curves;
};
/* Per rate calibration data for each mode, used for power table setup */
/* Per rate calibration data for each mode,
* used for rate power table setup.
* Note: Values in 0.5dB units */
struct ath5k_rate_pcal_info {
u16 freq; /* Frequency */
/* Power level for 6-24Mbit/s rates */
/* Power level for 6-24Mbit/s rates or
* 1Mb rate */
u16 target_power_6to24;
/* Power level for 36Mbit rate */
/* Power level for 36Mbit rate or
* 2Mb rate */
u16 target_power_36;
/* Power level for 48Mbit rate */
/* Power level for 48Mbit rate or
* 5.5Mbit rate */
u16 target_power_48;
/* Power level for 54Mbit rate */
/* Power level for 54Mbit rate or
* 11Mbit rate */
u16 target_power_54;
};
@@ -330,12 +380,6 @@ struct ath5k_eeprom_info {
u16 ee_cck_ofdm_power_delta;
u16 ee_scaled_cck_delta;
/* Used for tx thermal adjustment (eeprom_init, rfregs) */
u16 ee_tx_clip;
u16 ee_pwd_84;
u16 ee_pwd_90;
u16 ee_gain_select;
/* RF Calibration settings (reset, rfregs) */
u16 ee_i_cal[AR5K_EEPROM_N_MODES];
u16 ee_q_cal[AR5K_EEPROM_N_MODES];
@@ -363,23 +407,25 @@ struct ath5k_eeprom_info {
/* Power calibration data */
u16 ee_false_detect[AR5K_EEPROM_N_MODES];
/* Number of pd gain curves per mode (RF2413) */
u8 ee_pd_gains[AR5K_EEPROM_N_MODES];
/* Number of pd gain curves per mode */
u8 ee_pd_gains[AR5K_EEPROM_N_MODES];
/* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */
u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
u8 ee_n_piers[AR5K_EEPROM_N_MODES];
u8 ee_n_piers[AR5K_EEPROM_N_MODES];
struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN];
struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN];
struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
/* Per rate target power levels */
u16 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN];
struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN];
struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
/* Conformance test limits (Unused) */
u16 ee_ctls;
u16 ee_ctl[AR5K_EEPROM_MAX_CTLS];
u8 ee_ctls;
u8 ee_ctl[AR5K_EEPROM_MAX_CTLS];
struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
/* Noise Floor Calibration settings */

查看文件

@@ -1510,8 +1510,8 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
rf2425_ini_mode_end, mode);
ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf2413_ini_common_end),
rf2413_ini_common_end, change_channel);
ARRAY_SIZE(rf2425_ini_common_end),
rf2425_ini_common_end, change_channel);
ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5112_ini_bbgain),

查看文件

@@ -65,6 +65,8 @@ static const struct pci_device_id ath5k_led_devices[] = {
{ ATH_SDEVICE(PCI_VENDOR_ID_AMBIT, 0x0422), ATH_LED(1, 1) },
/* E-machines E510 (tuliom@gmail.com) */
{ ATH_SDEVICE(PCI_VENDOR_ID_AMBIT, 0x0428), ATH_LED(3, 0) },
/* Acer Extensa 5620z (nekoreeve@gmail.com) */
{ ATH_SDEVICE(PCI_VENDOR_ID_QMI, 0x0105), ATH_LED(3, 0) },
{ }
};

文件差异内容过多而无法显示 加载差异

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@@ -1553,6 +1553,19 @@
/*===5212 Specific PCU registers===*/
/*
* Transmit power control register
*/
#define AR5K_TPC 0x80e8
#define AR5K_TPC_ACK 0x0000003f /* ack frames */
#define AR5K_TPC_ACK_S 0
#define AR5K_TPC_CTS 0x00003f00 /* cts frames */
#define AR5K_TPC_CTS_S 8
#define AR5K_TPC_CHIRP 0x003f0000 /* chirp frames */
#define AR5K_TPC_CHIRP_S 16
#define AR5K_TPC_DOPPLER 0x0f000000 /* doppler chirp span */
#define AR5K_TPC_DOPPLER_S 24
/*
* XR (eXtended Range) mode register
*/
@@ -2550,6 +2563,12 @@
#define AR5K_PHY_TPC_RG1 0xa258
#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000
#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14
#define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000
#define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16
#define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000
#define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18
#define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000
#define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20
#define AR5K_PHY_TPC_RG5 0xa26C
#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F

查看文件

@@ -664,29 +664,35 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
struct ieee80211_channel *channel, u8 *ant, u8 ee_mode)
{
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
s16 cck_ofdm_pwr_delta;
/* Set CCK to OFDM power delta */
/* Adjust power delta for channel 14 */
if (channel->center_freq == 2484)
cck_ofdm_pwr_delta =
((ee->ee_cck_ofdm_power_delta -
ee->ee_scaled_cck_delta) * 2) / 10;
else
cck_ofdm_pwr_delta =
(ee->ee_cck_ofdm_power_delta * 2) / 10;
/* Set CCK to OFDM power delta on tx power
* adjustment register */
if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
int16_t cck_ofdm_pwr_delta;
/* Adjust power delta for channel 14 */
if (channel->center_freq == 2484)
cck_ofdm_pwr_delta =
((ee->ee_cck_ofdm_power_delta -
ee->ee_scaled_cck_delta) * 2) / 10;
else
cck_ofdm_pwr_delta =
(ee->ee_cck_ofdm_power_delta * 2) / 10;
if (channel->hw_value == CHANNEL_G)
ath5k_hw_reg_write(ah,
AR5K_REG_SM((ee->ee_cck_ofdm_power_delta * -1),
AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
AR5K_PHY_TX_PWR_ADJ);
else
ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
} else {
/* For older revs we scale power on sw during tx power
* setup */
ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
ah->ah_txpower.txp_cck_ofdm_gainf_delta =
ee->ee_cck_ofdm_gain_delta;
}
/* Set antenna idle switch table */
@@ -994,7 +1000,8 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
/*
* Set TX power (FIXME)
*/
ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
ret = ath5k_hw_txpower(ah, channel, ee_mode,
AR5K_TUNE_DEFAULT_TXPOWER);
if (ret)
return ret;

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
* Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>
*

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -295,13 +295,9 @@ struct ath_tx_control {
enum ath9k_internal_frame_type frame_type;
};
struct ath_xmit_status {
int retries;
int flags;
#define ATH_TX_ERROR 0x01
#define ATH_TX_XRETRY 0x02
#define ATH_TX_BAR 0x04
};
/* All RSSI values are noise floor adjusted */
struct ath_tx_stat {
@@ -390,6 +386,7 @@ void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid
struct ath_vif {
int av_bslot;
__le64 tsf_adjust; /* TSF adjustment for staggered beacons */
enum nl80211_iftype av_opmode;
struct ath_buf *av_bcbuf;
struct ath_tx_control av_btxctl;
@@ -406,7 +403,7 @@ struct ath_vif {
* number of beacon intervals, the game's up.
*/
#define BSTUCK_THRESH (9 * ATH_BCBUF)
#define ATH_BCBUF 1
#define ATH_BCBUF 4
#define ATH_DEFAULT_BINTVAL 100 /* TU */
#define ATH_DEFAULT_BMISS_LIMIT 10
#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -70,7 +70,8 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
ds = bf->bf_desc;
flags = ATH9K_TXDESC_NOACK;
if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC &&
if (((sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
(sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) &&
(ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
ds->ds_link = bf->bf_daddr; /* self-linked */
flags |= ATH9K_TXDESC_VEOL;
@@ -153,6 +154,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
bf->bf_mpdu = skb;
if (skb == NULL)
return NULL;
((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
avp->tsf_adjust;
info = IEEE80211_SKB_CB(skb);
if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
@@ -253,7 +256,6 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
{
struct ath_softc *sc = aphy->sc;
struct ath_vif *avp;
struct ieee80211_hdr *hdr;
struct ath_buf *bf;
struct sk_buff *skb;
__le64 tstamp;
@@ -316,42 +318,33 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
sc->beacon.bc_tstamp = le64_to_cpu(tstamp);
/*
* Calculate a TSF adjustment factor required for
* staggered beacons. Note that we assume the format
* of the beacon frame leaves the tstamp field immediately
* following the header.
*/
/* Calculate a TSF adjustment factor required for staggered beacons. */
if (avp->av_bslot > 0) {
u64 tsfadjust;
__le64 val;
int intval;
intval = sc->hw->conf.beacon_int ?
sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL;
/*
* The beacon interval is in TU's; the TSF in usecs.
* We figure out how many TU's to add to align the
* timestamp then convert to TSF units and handle
* byte swapping before writing it in the frame.
* The hardware will then add this each time a beacon
* frame is sent. Note that we align vif's 1..N
* and leave vif 0 untouched. This means vap 0
* has a timestamp in one beacon interval while the
* others get a timestamp aligned to the next interval.
* Calculate the TSF offset for this beacon slot, i.e., the
* number of usecs that need to be added to the timestamp field
* in Beacon and Probe Response frames. Beacon slot 0 is
* processed at the correct offset, so it does not require TSF
* adjustment. Other slots are adjusted to get the timestamp
* close to the TBTT for the BSS.
*/
tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF;
val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */
tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
DPRINTF(sc, ATH_DBG_BEACON,
"stagger beacons, bslot %d intval %u tsfadjust %llu\n",
avp->av_bslot, intval, (unsigned long long)tsfadjust);
hdr = (struct ieee80211_hdr *)skb->data;
memcpy(&hdr[1], &val, sizeof(val));
}
((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
avp->tsf_adjust;
} else
avp->tsf_adjust = cpu_to_le64(0);
bf->bf_mpdu = skb;
bf->bf_buf_addr = bf->bf_dmacontext =
@@ -447,8 +440,16 @@ void ath_beacon_tasklet(unsigned long data)
tsf = ath9k_hw_gettsf64(ah);
tsftu = TSF_TO_TU(tsf>>32, tsf);
slot = ((tsftu % intval) * ATH_BCBUF) / intval;
vif = sc->beacon.bslot[(slot + 1) % ATH_BCBUF];
aphy = sc->beacon.bslot_aphy[(slot + 1) % ATH_BCBUF];
/*
* Reverse the slot order to get slot 0 on the TBTT offset that does
* not require TSF adjustment and other slots adding
* slot/ATH_BCBUF * beacon_int to timestamp. For example, with
* ATH_BCBUF = 4, we process beacon slots as follows: 3 2 1 0 3 2 1 ..
* and slot 0 is at correct offset to TBTT.
*/
slot = ATH_BCBUF - slot - 1;
vif = sc->beacon.bslot[slot];
aphy = sc->beacon.bslot_aphy[slot];
DPRINTF(sc, ATH_DBG_BEACON,
"slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
@@ -728,6 +729,7 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
ath_beacon_config_ap(sc, &conf, avp);
break;
case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_MESH_POINT:
ath_beacon_config_adhoc(sc, &conf, avp, vif);
break;
case NL80211_IFTYPE_STATION:

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -342,8 +342,7 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
{
#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
u16 *eep_data;
u16 *eep_data = (u16 *)&ah->eeprom.map4k;
int addr, eep_start_loc = 0;
eep_start_loc = 64;
@@ -353,8 +352,6 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
"Reading from EEPROM, not flash\n");
}
eep_data = (u16 *)eep;
for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
@@ -363,6 +360,7 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
}
eep_data++;
}
return true;
#undef SIZE_EEPROM_4K
}
@@ -379,16 +377,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
if (!ath9k_hw_use_flash(ah)) {
if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
&magic)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Reading Magic # failed\n");
return false;
}
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"Read Magic = 0x%04X\n", magic);
"Read Magic = 0x%04X\n", magic);
if (magic != AR5416_EEPROM_MAGIC) {
magic2 = swab16(magic);
@@ -401,16 +398,9 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
temp = swab16(*eepdata);
*eepdata = temp;
eepdata++;
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"0x%04X ", *eepdata);
if (((addr + 1) % 6) == 0)
DPRINTF(ah->ah_sc,
ATH_DBG_EEPROM, "\n");
}
} else {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Invalid EEPROM Magic. "
"endianness mismatch.\n");
return -EINVAL;
@@ -426,7 +416,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
else
el = ah->eeprom.map4k.baseEepHeader.length;
if (el > sizeof(struct ar5416_eeprom_def))
if (el > sizeof(struct ar5416_eeprom_4k))
el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
else
el = el / sizeof(u16);
@@ -441,7 +431,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
u16 word;
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"EEPROM Endianness is not native.. Changing \n");
"EEPROM Endianness is not native.. Changing\n");
word = swab16(eep->baseEepHeader.length);
eep->baseEepHeader.length = word;
@@ -483,7 +473,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Bad EEPROM checksum 0x%x or revision 0x%04x\n",
sum, ah->eep_ops->get_eeprom_ver(ah));
return -EINVAL;
@@ -1203,57 +1193,63 @@ static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
}
}
static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
struct modal_eep_4k_header *pModal,
struct ar5416_eeprom_4k *eep,
u8 txRxAttenLocal, int regChainOffset)
{
REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
pModal->antCtrlChain[0]);
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
(REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
AR5416_EEP_MINOR_VER_3) {
txRxAttenLocal = pModal->txRxAttenCh[0];
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
pModal->xatten2Margin[0]);
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
}
REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
if (AR_SREV_9285_11(ah))
REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
}
static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
struct ath9k_channel *chan)
{
struct modal_eep_4k_header *pModal;
struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
int regChainOffset;
u8 txRxAttenLocal;
u8 ob[5], db1[5], db2[5];
u8 ant_div_control1, ant_div_control2;
u32 regVal;
pModal = &eep->modalHeader;
txRxAttenLocal = 23;
REG_WRITE(ah, AR_PHY_SWITCH_COM,
ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
regChainOffset = 0;
REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
pModal->antCtrlChain[0]);
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
(REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
AR5416_EEP_MINOR_VER_3) {
txRxAttenLocal = pModal->txRxAttenCh[0];
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
pModal->xatten2Margin[0]);
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
}
REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
if (AR_SREV_9285_11(ah))
REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
/* Single chain for 4K EEPROM*/
ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal, 0);
/* Initialize Ant Diversity settings from EEPROM */
if (pModal->version == 3) {
@@ -1295,9 +1291,6 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
db2[4] = ((pModal->db2_234 >> 8) & 0xf);
} else if (pModal->version == 1) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"EEPROM Model version is set to 1 \n");
ob[0] = (pModal->ob_01 & 0xf);
ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
db1[0] = (pModal->db1_01 & 0xf);
@@ -1385,8 +1378,6 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
AR_PHY_SETTLING_SWITCH,
pModal->swSettleHt40);
}
return true;
}
static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
@@ -1464,16 +1455,13 @@ static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
{
#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
struct ar5416_eeprom_def *eep = &ah->eeprom.def;
u16 *eep_data;
u16 *eep_data = (u16 *)&ah->eeprom.def;
int addr, ar5416_eep_start_loc = 0x100;
eep_data = (u16 *)eep;
for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
eep_data)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Unable to read eeprom region\n");
return false;
}
@@ -1492,17 +1480,14 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
bool need_swap = false;
int i, addr, size;
if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
&magic)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"Reading Magic # failed\n");
if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n");
return false;
}
if (!ath9k_hw_use_flash(ah)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"Read Magic = 0x%04X\n", magic);
"Read Magic = 0x%04X\n", magic);
if (magic != AR5416_EEPROM_MAGIC) {
magic2 = swab16(magic);
@@ -1516,18 +1501,11 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
temp = swab16(*eepdata);
*eepdata = temp;
eepdata++;
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"0x%04X ", *eepdata);
if (((addr + 1) % 6) == 0)
DPRINTF(ah->ah_sc,
ATH_DBG_EEPROM, "\n");
}
} else {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Invalid EEPROM Magic. "
"endianness mismatch.\n");
"Endianness mismatch.\n");
return -EINVAL;
}
}
@@ -1556,7 +1534,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
u16 word;
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"EEPROM Endianness is not native.. Changing \n");
"EEPROM Endianness is not native.. Changing.\n");
word = swab16(eep->baseEepHeader.length);
eep->baseEepHeader.length = word;
@@ -1602,7 +1580,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Bad EEPROM checksum 0x%x or revision 0x%04x\n",
sum, ah->eep_ops->get_eeprom_ver(ah));
return -EINVAL;
@@ -1614,7 +1592,6 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
enum eeprom_param param)
{
#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
struct ar5416_eeprom_def *eep = &ah->eeprom.def;
struct modal_eep_header *pModal = eep->modalHeader;
struct base_eep_header *pBase = &eep->baseEepHeader;
@@ -1681,21 +1658,73 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
default:
return 0;
}
#undef AR5416_VER_MASK
}
/* XXX: Clean me up, make me more legible */
static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
static void ath9k_hw_def_set_gain(struct ath_hw *ah,
struct modal_eep_header *pModal,
struct ar5416_eeprom_def *eep,
u8 txRxAttenLocal, int regChainOffset, int i)
{
if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
txRxAttenLocal = pModal->txRxAttenCh[i];
if (AR_SREV_9280_10_OR_LATER(ah)) {
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
pModal->bswMargin[i]);
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN1_DB,
pModal->bswAtten[i]);
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
pModal->xatten2Margin[i]);
REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN2_DB,
pModal->xatten2Db[i]);
} else {
REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
(REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
| SM(pModal-> bswMargin[i],
AR_PHY_GAIN_2GHZ_BSW_MARGIN));
REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
(REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
| SM(pModal->bswAtten[i],
AR_PHY_GAIN_2GHZ_BSW_ATTEN));
}
}
if (AR_SREV_9280_10_OR_LATER(ah)) {
REG_RMW_FIELD(ah,
AR_PHY_RXGAIN + regChainOffset,
AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
REG_RMW_FIELD(ah,
AR_PHY_RXGAIN + regChainOffset,
AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
} else {
REG_WRITE(ah,
AR_PHY_RXGAIN + regChainOffset,
(REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
~AR_PHY_RXGAIN_TXRX_ATTEN)
| SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
REG_WRITE(ah,
AR_PHY_GAIN_2GHZ + regChainOffset,
(REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
}
}
static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
struct ath9k_channel *chan)
{
#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
struct modal_eep_header *pModal;
struct ar5416_eeprom_def *eep = &ah->eeprom.def;
int i, regChainOffset;
u8 txRxAttenLocal;
pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
REG_WRITE(ah, AR_PHY_SWITCH_COM,
@@ -1708,8 +1737,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
}
if (AR_SREV_5416_20_OR_LATER(ah) &&
(ah->rxchainmask == 5 || ah->txchainmask == 5)
&& (i != 0))
(ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
regChainOffset = (i == 1) ? 0x2000 : 0x1000;
else
regChainOffset = i * 0x1000;
@@ -1718,9 +1746,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
pModal->antCtrlChain[i]);
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
(REG_READ(ah,
AR_PHY_TIMING_CTRL4(0) +
regChainOffset) &
(REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
SM(pModal->iqCalICh[i],
@@ -1728,87 +1754,9 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
SM(pModal->iqCalQCh[i],
AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
txRxAttenLocal = pModal->txRxAttenCh[i];
if (AR_SREV_9280_10_OR_LATER(ah)) {
REG_RMW_FIELD(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
pModal->
bswMargin[i]);
REG_RMW_FIELD(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN1_DB,
pModal->
bswAtten[i]);
REG_RMW_FIELD(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
pModal->
xatten2Margin[i]);
REG_RMW_FIELD(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN2_DB,
pModal->
xatten2Db[i]);
} else {
REG_WRITE(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset,
(REG_READ(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset) &
~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
| SM(pModal->
bswMargin[i],
AR_PHY_GAIN_2GHZ_BSW_MARGIN));
REG_WRITE(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset,
(REG_READ(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset) &
~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
| SM(pModal->bswAtten[i],
AR_PHY_GAIN_2GHZ_BSW_ATTEN));
}
}
if (AR_SREV_9280_10_OR_LATER(ah)) {
REG_RMW_FIELD(ah,
AR_PHY_RXGAIN +
regChainOffset,
AR9280_PHY_RXGAIN_TXRX_ATTEN,
txRxAttenLocal);
REG_RMW_FIELD(ah,
AR_PHY_RXGAIN +
regChainOffset,
AR9280_PHY_RXGAIN_TXRX_MARGIN,
pModal->rxTxMarginCh[i]);
} else {
REG_WRITE(ah,
AR_PHY_RXGAIN + regChainOffset,
(REG_READ(ah,
AR_PHY_RXGAIN +
regChainOffset) &
~AR_PHY_RXGAIN_TXRX_ATTEN) |
SM(txRxAttenLocal,
AR_PHY_RXGAIN_TXRX_ATTEN));
REG_WRITE(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset,
(REG_READ(ah,
AR_PHY_GAIN_2GHZ +
regChainOffset) &
~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
SM(pModal->rxTxMarginCh[i],
AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
}
}
if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
regChainOffset, i);
}
if (AR_SREV_9280_10_OR_LATER(ah)) {
@@ -1855,8 +1803,6 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
AR_AN_TOP2_LOCALBIAS,
AR_AN_TOP2_LOCALBIAS_S,
pModal->local_bias);
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n",
pModal->force_xpaon);
REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
pModal->force_xpaon);
}
@@ -1882,6 +1828,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
pModal->txEndToRxOn);
if (AR_SREV_9280_10_OR_LATER(ah)) {
REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
pModal->thresh62);
@@ -1912,10 +1859,10 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
}
if (AR_SREV_9280_20_OR_LATER(ah) &&
AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
pModal->miscBits);
AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
pModal->miscBits);
if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
@@ -1926,18 +1873,15 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
else
REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
eep->baseEepHeader.dacLpMode);
eep->baseEepHeader.dacLpMode);
REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
pModal->miscBits >> 2);
pModal->miscBits >> 2);
REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
AR_PHY_TX_DESIRED_SCALE_CCK,
eep->baseEepHeader.desiredScaleCCK);
AR_PHY_TX_DESIRED_SCALE_CCK,
eep->baseEepHeader.desiredScaleCCK);
}
return true;
#undef AR5416_VER_MASK
}
static void ath9k_hw_def_set_addac(struct ath_hw *ah,

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -95,6 +95,7 @@
#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
@@ -489,7 +490,7 @@ struct eeprom_ops {
u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
struct ath9k_channel *chan);
bool (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
int (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
u16 cfgCtl, u8 twiceAntennaReduction,

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -588,6 +588,10 @@ static int ath9k_hw_post_attach(struct ath_hw *ah)
ecode = ath9k_hw_eeprom_attach(ah);
if (ecode != 0)
return ecode;
DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
ecode = ath9k_hw_rfattach(ah);
if (ecode != 0)
return ecode;
@@ -1444,6 +1448,7 @@ static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
break;
case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_MESH_POINT:
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
| AR_STA_ID1_KSRCH_MODE);
REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
@@ -2273,11 +2278,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
else
ath9k_hw_spur_mitigate(ah, chan);
if (!ah->eep_ops->set_board_values(ah, chan)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"error setting board options\n");
return -EIO;
}
ah->eep_ops->set_board_values(ah, chan);
ath9k_hw_decrease_chain_power(ah, chan);
@@ -3149,6 +3150,7 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
flags |= AR_TBTT_TIMER_EN;
break;
case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_MESH_POINT:
REG_SET_BIT(ah, AR_TXCFG,
AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
REG_WRITE(ah, AR_NEXT_NDP_TIMER,

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -940,18 +940,25 @@ static void ath_led_blink_work(struct work_struct *work)
if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
return;
ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
(sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
(sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
else
ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
(sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
(sc->sc_flags & SC_OP_LED_ON) ?
msecs_to_jiffies(sc->led_off_duration) :
msecs_to_jiffies(sc->led_on_duration));
sc->led_on_duration =
max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
sc->led_off_duration =
max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
sc->led_on_duration = sc->led_on_cnt ?
max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
ATH_LED_ON_DURATION_IDLE;
sc->led_off_duration = sc->led_off_cnt ?
max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
ATH_LED_OFF_DURATION_IDLE;
sc->led_on_cnt = sc->led_off_cnt = 0;
if (sc->sc_flags & SC_OP_LED_ON)
sc->sc_flags &= ~SC_OP_LED_ON;
@@ -1592,7 +1599,8 @@ void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
hw->wiphy->interface_modes =
BIT(NL80211_IFTYPE_AP) |
BIT(NL80211_IFTYPE_STATION) |
BIT(NL80211_IFTYPE_ADHOC);
BIT(NL80211_IFTYPE_ADHOC) |
BIT(NL80211_IFTYPE_MESH_POINT);
hw->wiphy->reg_notifier = ath9k_reg_notifier;
hw->wiphy->strict_regulatory = true;
@@ -2200,18 +2208,13 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
ic_opmode = NL80211_IFTYPE_STATION;
break;
case NL80211_IFTYPE_ADHOC:
if (sc->nbcnvifs >= ATH_BCBUF) {
ret = -ENOBUFS;
goto out;
}
ic_opmode = NL80211_IFTYPE_ADHOC;
break;
case NL80211_IFTYPE_AP:
case NL80211_IFTYPE_MESH_POINT:
if (sc->nbcnvifs >= ATH_BCBUF) {
ret = -ENOBUFS;
goto out;
}
ic_opmode = NL80211_IFTYPE_AP;
ic_opmode = conf->type;
break;
default:
DPRINTF(sc, ATH_DBG_FATAL,
@@ -2247,7 +2250,8 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
* Note we only do this (at the moment) for station mode.
*/
if ((conf->type == NL80211_IFTYPE_STATION) ||
(conf->type == NL80211_IFTYPE_ADHOC)) {
(conf->type == NL80211_IFTYPE_ADHOC) ||
(conf->type == NL80211_IFTYPE_MESH_POINT)) {
if (ath9k_hw_phycounters(sc->sc_ah))
sc->imask |= ATH9K_INT_MIB;
sc->imask |= ATH9K_INT_TSFOOR;
@@ -2294,8 +2298,9 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
del_timer_sync(&sc->ani.timer);
/* Reclaim beacon resources */
if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
(sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
(sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
ath_beacon_return(sc, avp);
}
@@ -2428,6 +2433,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
switch (vif->type) {
case NL80211_IFTYPE_STATION:
case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_MESH_POINT:
/* Set BSSID */
memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
memcpy(avp->bssid, conf->bssid, ETH_ALEN);
@@ -2451,7 +2457,8 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
}
if ((vif->type == NL80211_IFTYPE_ADHOC) ||
(vif->type == NL80211_IFTYPE_AP)) {
(vif->type == NL80211_IFTYPE_AP) ||
(vif->type == NL80211_IFTYPE_MESH_POINT)) {
if ((conf->changed & IEEE80211_IFCC_BEACON) ||
(conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
conf->enable_beacon)) {
@@ -2723,7 +2730,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
break;
case IEEE80211_AMPDU_TX_RESUME:
case IEEE80211_AMPDU_TX_OPERATIONAL:
ath_tx_aggr_resume(sc, sta, tid);
break;
default:

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -87,7 +87,6 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
struct ath_softc *sc;
struct ieee80211_hw *hw;
u8 csz;
u32 val;
int ret = 0;
struct ath_hw *ah;
@@ -134,14 +133,6 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
pci_set_master(pdev);
/*
* Disable the RETRY_TIMEOUT register (0x41) to keep
* PCI Tx retries from interfering with C3 CPU state.
*/
pci_read_config_dword(pdev, 0x40, &val);
if ((val & 0x0000ff00) != 0)
pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
ret = pci_request_region(pdev, 0, "ath9k");
if (ret) {
dev_err(&pdev->dev, "PCI memory region reserve error\n");
@@ -253,21 +244,12 @@ static int ath_pci_resume(struct pci_dev *pdev)
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
struct ath_wiphy *aphy = hw->priv;
struct ath_softc *sc = aphy->sc;
u32 val;
int err;
err = pci_enable_device(pdev);
if (err)
return err;
pci_restore_state(pdev);
/*
* Suspend/Resume resets the PCI configuration space, so we have to
* re-disable the RETRY_TIMEOUT register (0x41) to keep
* PCI Tx retries from interfering with C3 CPU state
*/
pci_read_config_dword(pdev, 0x40, &val);
if ((val & 0x0000ff00) != 0)
pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
/* Enable LED */
ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2004 Video54 Technologies, Inc.
* Copyright (c) 2004-2008 Atheros Communications, Inc.
* Copyright (c) 2004-2009 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -864,6 +864,8 @@ static void ath_rc_ratefind(struct ath_softc *sc,
rate_table, nrix, 1, 0);
ath_rc_rate_set_series(rate_table, &rates[i++], txrc,
try_per_rate, nrix, 0);
tx_info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
} else {
try_per_rate = (ATH_11N_TXMAXTRY/4);
/* Set the choosen rate. No RTS for first series entry. */
@@ -1468,16 +1470,18 @@ static void ath_rc_init(struct ath_softc *sc,
ath_rc_priv->ht_cap);
}
static u8 ath_rc_build_ht_caps(struct ath_softc *sc, bool is_ht, bool is_cw40,
bool is_sgi40)
static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
bool is_cw40, bool is_sgi40)
{
u8 caps = 0;
if (is_ht) {
if (sta->ht_cap.ht_supported) {
caps = WLAN_RC_HT_FLAG;
if (sc->sc_ah->caps.tx_chainmask != 1 &&
ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_DS, 0, NULL))
caps |= WLAN_RC_DS_FLAG;
ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_DS, 0, NULL)) {
if (sta->ht_cap.mcs.rx_mask[1])
caps |= WLAN_RC_DS_FLAG;
}
if (is_cw40)
caps |= WLAN_RC_40_FLAG;
if (is_sgi40)
@@ -1615,6 +1619,7 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
/* Choose rate table first */
if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) ||
(sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT) ||
(sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)) {
rate_table = ath_choose_rate_table(sc, sband->band,
sta->ht_cap.ht_supported,
@@ -1624,8 +1629,7 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
rate_table = sc->cur_rate_table;
}
ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta->ht_cap.ht_supported,
is_cw40, is_sgi40);
ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta, is_cw40, is_sgi40);
ath_rc_init(sc, priv_sta, sband, sta, rate_table);
}
@@ -1659,8 +1663,7 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
rate_table = ath_choose_rate_table(sc, sband->band,
sta->ht_cap.ht_supported,
oper_cw40);
ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc,
sta->ht_cap.ht_supported,
ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta,
oper_cw40, oper_sgi40);
ath_rc_init(sc, priv_sta, sband, sta, rate_table);

查看文件

@@ -1,7 +1,7 @@
/*
* Copyright (c) 2004 Sam Leffler, Errno Consulting
* Copyright (c) 2004 Video54 Technologies, Inc.
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -344,8 +344,13 @@ void ath_rx_cleanup(struct ath_softc *sc)
list_for_each_entry(bf, &sc->rx.rxbuf, list) {
skb = bf->bf_mpdu;
if (skb)
if (skb) {
dma_unmap_single(sc->dev,
bf->bf_buf_addr,
sc->rx.bufsize,
DMA_FROM_DEVICE);
dev_kfree_skb(skb);
}
}
if (sc->rx.rxdma.dd_desc_len != 0)

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -64,6 +64,10 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
struct list_head *head);
static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
int txok);
static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
int nbad, int txok, bool update_rc);
/*********************/
/* Aggregation logic */
@@ -274,9 +278,10 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
struct ath_desc *ds = bf_last->bf_desc;
struct list_head bf_head, bf_pending;
u16 seq_st = 0;
u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
u32 ba[WME_BA_BMP_SIZE >> 5];
int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
bool rc_update = true;
skb = (struct sk_buff *)bf->bf_mpdu;
hdr = (struct ieee80211_hdr *)skb->data;
@@ -316,6 +321,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
INIT_LIST_HEAD(&bf_pending);
INIT_LIST_HEAD(&bf_head);
nbad = ath_tx_num_badfrms(sc, bf, txok);
while (bf) {
txfail = txpending = 0;
bf_next = bf->bf_next;
@@ -323,8 +329,10 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
/* transmit completion, subframe is
* acked by block ack */
acked_cnt++;
} else if (!isaggr && txok) {
/* transmit completion */
acked_cnt++;
} else {
if (!(tid->state & AGGR_CLEANUP) &&
ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
@@ -335,6 +343,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
bf->bf_state.bf_type |= BUF_XRETRY;
txfail = 1;
sendbar = 1;
txfail_cnt++;
}
} else {
/*
@@ -361,6 +370,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
ath_tx_update_baw(sc, tid, bf->bf_seqno);
spin_unlock_bh(&txq->axq_lock);
if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
ath_tx_rc_status(bf, ds, nbad, txok, true);
rc_update = false;
} else {
ath_tx_rc_status(bf, ds, nbad, txok, false);
}
ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
} else {
/* retry the un-acked ones */
@@ -1734,7 +1750,7 @@ exit:
/*****************/
static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
struct ath_xmit_status *tx_status)
int tx_flags)
{
struct ieee80211_hw *hw = sc->hw;
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -1755,18 +1771,14 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
tx_info->rate_driver_data[0] = NULL;
}
if (tx_status->flags & ATH_TX_BAR) {
if (tx_flags & ATH_TX_BAR)
tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
tx_status->flags &= ~ATH_TX_BAR;
}
if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
/* Frame was ACKed */
tx_info->flags |= IEEE80211_TX_STAT_ACK;
}
tx_info->status.rates[0].count = tx_status->retries + 1;
hdrlen = ieee80211_get_hdrlen_from_skb(skb);
padsize = hdrlen & 3;
if (padsize && hdrlen >= 24) {
@@ -1789,29 +1801,22 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
int txok, int sendbar)
{
struct sk_buff *skb = bf->bf_mpdu;
struct ath_xmit_status tx_status;
unsigned long flags;
int tx_flags = 0;
/*
* Set retry information.
* NB: Don't use the information in the descriptor, because the frame
* could be software retried.
*/
tx_status.retries = bf->bf_retries;
tx_status.flags = 0;
if (sendbar)
tx_status.flags = ATH_TX_BAR;
tx_flags = ATH_TX_BAR;
if (!txok) {
tx_status.flags |= ATH_TX_ERROR;
tx_flags |= ATH_TX_ERROR;
if (bf_isxretried(bf))
tx_status.flags |= ATH_TX_XRETRY;
tx_flags |= ATH_TX_XRETRY;
}
dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
ath_tx_complete(sc, skb, &tx_status);
ath_tx_complete(sc, skb, tx_flags);
/*
* Return the list of ath_buf of this mpdu to free queue
@@ -1852,27 +1857,40 @@ static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
return nbad;
}
static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, int nbad)
static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
int nbad, int txok, bool update_rc)
{
struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
u8 i, tx_rateindex;
tx_info_priv->update_rc = false;
if (txok)
tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
tx_rateindex = ds->ds_txstat.ts_rateindex;
WARN_ON(tx_rateindex >= hw->max_rates);
tx_info_priv->update_rc = update_rc;
if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
(bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
(bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
if (ieee80211_is_data(hdr->frame_control)) {
memcpy(&tx_info_priv->tx, &ds->ds_txstat,
sizeof(tx_info_priv->tx));
tx_info_priv->n_frames = bf->bf_nframes;
tx_info_priv->n_bad_frames = nbad;
tx_info_priv->update_rc = true;
}
}
for (i = tx_rateindex + 1; i < hw->max_rates; i++)
tx_info->status.rates[i].count = 0;
tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
}
static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
@@ -1897,7 +1915,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
struct ath_buf *bf, *lastbf, *bf_held = NULL;
struct list_head bf_head;
struct ath_desc *ds;
int txok, nbad = 0;
int txok;
int status;
DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
@@ -1991,13 +2009,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
bf->bf_retries = ds->ds_txstat.ts_longretry;
if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
bf->bf_state.bf_type |= BUF_XRETRY;
nbad = 0;
} else {
nbad = ath_tx_num_badfrms(sc, bf, txok);
ath_tx_rc_status(bf, ds, 0, txok, true);
}
ath_tx_rc_status(bf, ds, nbad);
if (bf_isampdu(bf))
ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
else

查看文件

@@ -3993,6 +3993,8 @@ static void setup_struct_wldev_for_init(struct b43_wldev *dev)
dev->irq_reason = 0;
memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
dev->irq_savedstate &= ~B43_IRQ_PHY_TXERR;
dev->mac_suspended = 1;

查看文件

@@ -50,7 +50,7 @@ static int b43_plcp_get_bitrate_idx_cck(struct b43_plcp_hdr6 *plcp)
}
/* Extract the bitrate index out of an OFDM PLCP header. */
static u8 b43_plcp_get_bitrate_idx_ofdm(struct b43_plcp_hdr6 *plcp, bool aphy)
static int b43_plcp_get_bitrate_idx_ofdm(struct b43_plcp_hdr6 *plcp, bool aphy)
{
int base = aphy ? 0 : 4;

查看文件

@@ -233,7 +233,7 @@ struct iwl3945_eeprom {
#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
#define TFD_QUEUE_MIN 0
#define TFD_QUEUE_MAX 6
#define TFD_QUEUE_MAX 5 /* 4 DATA + 1 CMD */
#define IWL_NUM_SCAN_RATES (2)

查看文件

@@ -124,7 +124,7 @@ static struct iwl3945_tpt_entry iwl3945_tpt_table_g[] = {
#define IWL39_RATE_HIGH_TH 11520
#define IWL_SUCCESS_UP_TH 8960
#define IWL_SUCCESS_DOWN_TH 10880
#define IWL_RATE_MIN_FAILURE_TH 8
#define IWL_RATE_MIN_FAILURE_TH 6
#define IWL_RATE_MIN_SUCCESS_TH 8
#define IWL_RATE_DECREASE_TH 1920
#define IWL_RATE_RETRY_TH 15
@@ -488,7 +488,7 @@ static void rs_tx_status(void *priv_rate, struct ieee80211_supported_band *sband
IWL_DEBUG_RATE(priv, "enter\n");
retries = info->status.rates[0].count - 1;
retries = info->status.rates[0].count;
/* Sanity Check for retries */
if (retries > IWL_RATE_RETRY_TH)
retries = IWL_RATE_RETRY_TH;
@@ -791,16 +791,15 @@ static void rs_get_rate(void *priv_r, struct ieee80211_sta *sta,
if ((window->success_ratio < IWL_RATE_DECREASE_TH) || !current_tpt) {
IWL_DEBUG_RATE(priv, "decrease rate because of low success_ratio\n");
scale_action = -1;
/* No throughput measured yet for adjacent rates,
* try increase */
} else if ((low_tpt == IWL_INVALID_VALUE) &&
(high_tpt == IWL_INVALID_VALUE)) {
if (high != IWL_RATE_INVALID && window->success_counter >= IWL_RATE_INCREASE_TH)
if (high != IWL_RATE_INVALID && window->success_ratio >= IWL_RATE_INCREASE_TH)
scale_action = 1;
else if (low != IWL_RATE_INVALID)
scale_action = -1;
scale_action = 0;
/* Both adjacent throughputs are measured, but neither one has
* better throughput; we're using the best rate, don't change
@@ -826,14 +825,14 @@ static void rs_get_rate(void *priv_r, struct ieee80211_sta *sta,
else {
IWL_DEBUG_RATE(priv,
"decrease rate because of high tpt\n");
scale_action = -1;
scale_action = 0;
}
} else if (low_tpt != IWL_INVALID_VALUE) {
if (low_tpt > current_tpt) {
IWL_DEBUG_RATE(priv,
"decrease rate because of low tpt\n");
scale_action = -1;
} else if (window->success_counter >= IWL_RATE_INCREASE_TH) {
} else if (window->success_ratio >= IWL_RATE_INCREASE_TH) {
/* Lower rate has better
* throughput,decrease rate */
scale_action = 1;

查看文件

@@ -293,7 +293,7 @@ static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
(txq_id != IWL_CMD_QUEUE_NUM) &&
priv->mac80211_registered)
ieee80211_wake_queue(priv->hw, txq_id);
iwl_wake_queue(priv, txq_id);
}
/**
@@ -747,11 +747,6 @@ void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
int i;
int counter;
/* classify bd */
if (txq->q.id == IWL_CMD_QUEUE_NUM)
/* nothing to cleanup after for host commands */
return;
/* sanity check */
counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
if (counter > NUM_TFD_CHUNKS) {
@@ -1046,7 +1041,7 @@ static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
goto error;
/* Tx queue(s) */
for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++) {
slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
@@ -1184,7 +1179,7 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
if(rc)
if (rc)
return rc;
priv->cfg->ops->lib->apm_ops.config(priv);
@@ -1239,8 +1234,12 @@ void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
int txq_id;
/* Tx queues */
for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
iwl_tx_queue_free(priv, txq_id);
for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++)
if (txq_id == IWL_CMD_QUEUE_NUM)
iwl_cmd_queue_free(priv);
else
iwl_tx_queue_free(priv, txq_id);
}
void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
@@ -1259,7 +1258,7 @@ void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
/* reset TFD queues */
for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++) {
iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
@@ -2488,6 +2487,9 @@ int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
return -ENOMEM;
}
/* Assign number of Usable TX queues */
priv->hw_params.max_txq_num = TFD_QUEUE_MAX;
priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
priv->hw_params.max_pkt_size = 2342;

查看文件

@@ -2178,10 +2178,9 @@ static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
(iwl_queue_space(&txq->q) > txq->q.low_mark) &&
(agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
if (agg->state == IWL_AGG_OFF)
ieee80211_wake_queue(priv->hw, txq_id);
iwl_wake_queue(priv, txq_id);
else
ieee80211_wake_queue(priv->hw,
txq->swq_id);
iwl_wake_queue(priv, txq->swq_id);
}
}
} else {
@@ -2205,7 +2204,7 @@ static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
if (priv->mac80211_registered &&
(iwl_queue_space(&txq->q) > txq->q.low_mark))
ieee80211_wake_queue(priv->hw, txq_id);
iwl_wake_queue(priv, txq_id);
}
if (qc && likely(sta_id != IWL_INVALID_STATION))

查看文件

@@ -1077,7 +1077,7 @@ static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
(IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
IWL_WARN(priv,
IWL_ERR(priv,
"queue number out of range: %d, must be %d to %d\n",
txq_id, IWL50_FIRST_AMPDU_QUEUE,
IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
@@ -1295,10 +1295,9 @@ static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
(iwl_queue_space(&txq->q) > txq->q.low_mark) &&
(agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
if (agg->state == IWL_AGG_OFF)
ieee80211_wake_queue(priv->hw, txq_id);
iwl_wake_queue(priv, txq_id);
else
ieee80211_wake_queue(priv->hw,
txq->swq_id);
iwl_wake_queue(priv, txq->swq_id);
}
}
} else {
@@ -1324,7 +1323,7 @@ static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
if (priv->mac80211_registered &&
(iwl_queue_space(&txq->q) > txq->q.low_mark))
ieee80211_wake_queue(priv->hw, txq_id);
iwl_wake_queue(priv, txq_id);
}
if (ieee80211_is_data_qos(tx_resp->frame_ctrl))

查看文件

@@ -1567,9 +1567,8 @@ static void iwl_alive_start(struct iwl_priv *priv)
if (iwl_is_associated(priv)) {
struct iwl_rxon_cmd *active_rxon =
(struct iwl_rxon_cmd *)&priv->active_rxon;
memcpy(&priv->staging_rxon, &priv->active_rxon,
sizeof(priv->staging_rxon));
/* apply any changes in staging */
priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
} else {
/* Initialize our rx_config data */
@@ -2184,110 +2183,112 @@ static int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
struct iwl_priv *priv = hw->priv;
const struct iwl_channel_info *ch_info;
struct ieee80211_conf *conf = &hw->conf;
unsigned long flags;
unsigned long flags = 0;
int ret = 0;
u16 channel;
u16 ch;
int scan_active = 0;
mutex_lock(&priv->mutex);
IWL_DEBUG_MAC80211(priv, "enter to channel %d\n", conf->channel->hw_value);
priv->current_ht_config.is_ht = conf_is_ht(conf);
if (conf->radio_enabled && iwl_radio_kill_sw_enable_radio(priv)) {
IWL_DEBUG_MAC80211(priv, "leave - RF-KILL - waiting for uCode\n");
goto out;
}
if (!conf->radio_enabled)
iwl_radio_kill_sw_disable_radio(priv);
if (!iwl_is_ready(priv)) {
IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
ret = -EIO;
goto out;
}
IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
conf->channel->hw_value, changed);
if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
test_bit(STATUS_SCANNING, &priv->status))) {
test_bit(STATUS_SCANNING, &priv->status))) {
scan_active = 1;
IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
mutex_unlock(&priv->mutex);
return 0;
}
channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
ch_info = iwl_get_channel_info(priv, conf->channel->band, channel);
if (!is_channel_valid(ch_info)) {
IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
ret = -EINVAL;
goto out;
/* during scanning mac80211 will delay channel setting until
* scan finish with changed = 0
*/
if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
if (scan_active)
goto set_ch_out;
ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
if (!is_channel_valid(ch_info)) {
IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
ret = -EINVAL;
goto set_ch_out;
}
if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
!is_channel_ibss(ch_info)) {
IWL_ERR(priv, "channel %d in band %d not "
"IBSS channel\n",
conf->channel->hw_value, conf->channel->band);
ret = -EINVAL;
goto set_ch_out;
}
priv->current_ht_config.is_ht = conf_is_ht(conf);
spin_lock_irqsave(&priv->lock, flags);
/* if we are switching from ht to 2.4 clear flags
* from any ht related info since 2.4 does not
* support ht */
if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
priv->staging_rxon.flags = 0;
iwl_set_rxon_channel(priv, conf->channel);
iwl_set_flags_for_band(priv, conf->channel->band);
spin_unlock_irqrestore(&priv->lock, flags);
set_ch_out:
/* The list of supported rates and rate mask can be different
* for each band; since the band may have changed, reset
* the rate mask to what mac80211 lists */
iwl_set_rate(priv);
}
if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
!is_channel_ibss(ch_info)) {
IWL_ERR(priv, "channel %d in band %d not IBSS channel\n",
conf->channel->hw_value, conf->channel->band);
ret = -EINVAL;
goto out;
if (changed & IEEE80211_CONF_CHANGE_PS) {
if (conf->flags & IEEE80211_CONF_PS)
ret = iwl_power_set_user_mode(priv, IWL_POWER_INDEX_3);
else
ret = iwl_power_set_user_mode(priv, IWL_POWER_MODE_CAM);
if (ret)
IWL_DEBUG_MAC80211(priv, "Error setting power level\n");
}
spin_lock_irqsave(&priv->lock, flags);
if (changed & IEEE80211_CONF_CHANGE_POWER) {
IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
priv->tx_power_user_lmt, conf->power_level);
/* if we are switching from ht to 2.4 clear flags
* from any ht related info since 2.4 does not
* support ht */
if ((le16_to_cpu(priv->staging_rxon.channel) != channel)
#ifdef IEEE80211_CONF_CHANNEL_SWITCH
&& !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH)
#endif
)
priv->staging_rxon.flags = 0;
iwl_set_rxon_channel(priv, conf->channel);
iwl_set_flags_for_band(priv, conf->channel->band);
/* The list of supported rates and rate mask can be different
* for each band; since the band may have changed, reset
* the rate mask to what mac80211 lists */
iwl_set_rate(priv);
spin_unlock_irqrestore(&priv->lock, flags);
#ifdef IEEE80211_CONF_CHANNEL_SWITCH
if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
iwl_hw_channel_switch(priv, conf->channel);
goto out;
iwl_set_tx_power(priv, conf->power_level, false);
}
/* call to ensure that 4965 rx_chain is set properly in monitor mode */
iwl_set_rxon_chain(priv);
if (changed & IEEE80211_CONF_CHANGE_RADIO_ENABLED) {
if (conf->radio_enabled &&
iwl_radio_kill_sw_enable_radio(priv)) {
IWL_DEBUG_MAC80211(priv, "leave - RF-KILL - "
"waiting for uCode\n");
goto out;
}
if (!conf->radio_enabled)
iwl_radio_kill_sw_disable_radio(priv);
}
#endif
if (!conf->radio_enabled) {
IWL_DEBUG_MAC80211(priv, "leave - radio disabled\n");
goto out;
}
if (iwl_is_rfkill(priv)) {
IWL_DEBUG_MAC80211(priv, "leave - RF kill\n");
ret = -EIO;
if (!iwl_is_ready(priv)) {
IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
goto out;
}
if (conf->flags & IEEE80211_CONF_PS)
ret = iwl_power_set_user_mode(priv, IWL_POWER_INDEX_3);
else
ret = iwl_power_set_user_mode(priv, IWL_POWER_MODE_CAM);
if (ret)
IWL_DEBUG_MAC80211(priv, "Error setting power level\n");
IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
priv->tx_power_user_lmt, conf->power_level);
iwl_set_tx_power(priv, conf->power_level, false);
iwl_set_rate(priv);
/* call to ensure that 4965 rx_chain is set properly in monitor mode */
iwl_set_rxon_chain(priv);
if (scan_active)
goto out;
if (memcmp(&priv->active_rxon,
&priv->staging_rxon, sizeof(priv->staging_rxon)))
@@ -2295,9 +2296,9 @@ static int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
else
IWL_DEBUG_INFO(priv, "No re-sending same RXON configuration.\n");
IWL_DEBUG_MAC80211(priv, "leave\n");
out:
IWL_DEBUG_MAC80211(priv, "leave\n");
mutex_unlock(&priv->mutex);
return ret;
}
@@ -2682,6 +2683,7 @@ static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid, u16 *ssn)
{
struct iwl_priv *priv = hw->priv;
int ret;
IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
sta->addr, tid);
@@ -2695,13 +2697,21 @@ static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
case IEEE80211_AMPDU_RX_STOP:
IWL_DEBUG_HT(priv, "stop Rx\n");
return iwl_sta_rx_agg_stop(priv, sta->addr, tid);
ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
if (test_bit(STATUS_EXIT_PENDING, &priv->status))
return 0;
else
return ret;
case IEEE80211_AMPDU_TX_START:
IWL_DEBUG_HT(priv, "start Tx\n");
return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
case IEEE80211_AMPDU_TX_STOP:
IWL_DEBUG_HT(priv, "stop Tx\n");
return iwl_tx_agg_stop(priv, sta->addr, tid);
ret = iwl_tx_agg_stop(priv, sta->addr, tid);
if (test_bit(STATUS_EXIT_PENDING, &priv->status))
return 0;
else
return ret;
default:
IWL_DEBUG_HT(priv, "unknown\n");
return -EINVAL;
@@ -3083,11 +3093,6 @@ static ssize_t store_power_level(struct device *d,
mutex_lock(&priv->mutex);
if (!iwl_is_ready(priv)) {
ret = -EAGAIN;
goto out;
}
ret = strict_strtoul(buf, 10, &mode);
if (ret)
goto out;

查看文件

@@ -1298,6 +1298,7 @@ int iwl_setup_mac(struct iwl_priv *priv)
hw->flags = IEEE80211_HW_SIGNAL_DBM |
IEEE80211_HW_NOISE_DBM |
IEEE80211_HW_AMPDU_AGGREGATION |
IEEE80211_HW_SPECTRUM_MGMT |
IEEE80211_HW_SUPPORTS_PS;
hw->wiphy->interface_modes =
BIT(NL80211_IFTYPE_STATION) |
@@ -1308,9 +1309,6 @@ int iwl_setup_mac(struct iwl_priv *priv)
/* Default value; 4 EDCA QOS priorities */
hw->queues = 4;
/* queues to support 11n aggregation */
if (priv->cfg->sku & IWL_SKU_N)
hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
hw->conf.beacon_int = 100;
hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
@@ -1437,6 +1435,10 @@ int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
priv->tx_power_user_lmt = tx_power;
/* if nic is not up don't send command */
if (!iwl_is_ready_rf(priv))
return ret;
if (force && priv->cfg->ops->lib->send_tx_power)
ret = priv->cfg->ops->lib->send_tx_power(priv);

查看文件

@@ -264,6 +264,7 @@ void iwl_rx_reply_error(struct iwl_priv *priv,
* RX
******************************************************/
void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
void iwl_cmd_queue_free(struct iwl_priv *priv);
int iwl_rx_queue_alloc(struct iwl_priv *priv);
void iwl_rx_handle(struct iwl_priv *priv);
int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,

查看文件

@@ -425,6 +425,56 @@ static ssize_t iwl_dbgfs_channels_read(struct file *file, char __user *user_buf,
return ret;
}
static ssize_t iwl_dbgfs_status_read(struct file *file,
char __user *user_buf,
size_t count, loff_t *ppos) {
struct iwl_priv *priv = (struct iwl_priv *)file->private_data;
char buf[512];
int pos = 0;
const size_t bufsz = sizeof(buf);
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_HCMD_ACTIVE:\t %d\n",
test_bit(STATUS_HCMD_ACTIVE, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_HCMD_SYNC_ACTIVE: %d\n",
test_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_INT_ENABLED:\t %d\n",
test_bit(STATUS_INT_ENABLED, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_RF_KILL_HW:\t %d\n",
test_bit(STATUS_RF_KILL_HW, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_RF_KILL_SW:\t %d\n",
test_bit(STATUS_RF_KILL_SW, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_INIT:\t\t %d\n",
test_bit(STATUS_INIT, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_ALIVE:\t\t %d\n",
test_bit(STATUS_ALIVE, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_READY:\t\t %d\n",
test_bit(STATUS_READY, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_TEMPERATURE:\t %d\n",
test_bit(STATUS_TEMPERATURE, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_GEO_CONFIGURED:\t %d\n",
test_bit(STATUS_GEO_CONFIGURED, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_EXIT_PENDING:\t %d\n",
test_bit(STATUS_EXIT_PENDING, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_IN_SUSPEND:\t %d\n",
test_bit(STATUS_IN_SUSPEND, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_STATISTICS:\t %d\n",
test_bit(STATUS_STATISTICS, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_SCANNING:\t %d\n",
test_bit(STATUS_SCANNING, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_SCAN_ABORTING:\t %d\n",
test_bit(STATUS_SCAN_ABORTING, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_SCAN_HW:\t\t %d\n",
test_bit(STATUS_SCAN_HW, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_POWER_PMI:\t %d\n",
test_bit(STATUS_POWER_PMI, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_FW_ERROR:\t %d\n",
test_bit(STATUS_FW_ERROR, &priv->status));
pos += scnprintf(buf + pos, bufsz - pos, "STATUS_MODE_PENDING:\t %d\n",
test_bit(STATUS_MODE_PENDING, &priv->status));
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}
DEBUGFS_READ_WRITE_FILE_OPS(sram);
DEBUGFS_WRITE_FILE_OPS(log_event);
DEBUGFS_READ_FILE_OPS(eeprom);
@@ -432,6 +482,7 @@ DEBUGFS_READ_FILE_OPS(stations);
DEBUGFS_READ_FILE_OPS(rx_statistics);
DEBUGFS_READ_FILE_OPS(tx_statistics);
DEBUGFS_READ_FILE_OPS(channels);
DEBUGFS_READ_FILE_OPS(status);
/*
* Create the debugfs files and directories
@@ -466,7 +517,7 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name)
DEBUGFS_ADD_FILE(rx_statistics, data);
DEBUGFS_ADD_FILE(tx_statistics, data);
DEBUGFS_ADD_FILE(channels, data);
DEBUGFS_ADD_X32(status, data, (u32 *)&priv->status);
DEBUGFS_ADD_FILE(status, data);
DEBUGFS_ADD_BOOL(disable_sensitivity, rf, &priv->disable_sens_cal);
DEBUGFS_ADD_BOOL(disable_chain_noise, rf,
&priv->disable_chain_noise_cal);
@@ -496,6 +547,7 @@ void iwl_dbgfs_unregister(struct iwl_priv *priv)
DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_log_event);
DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_stations);
DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_channels);
DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_status);
DEBUGFS_REMOVE(priv->dbgfs->dir_data);
DEBUGFS_REMOVE(priv->dbgfs->dbgfs_rf_files.file_disable_sensitivity);
DEBUGFS_REMOVE(priv->dbgfs->dbgfs_rf_files.file_disable_chain_noise);

查看文件

@@ -996,6 +996,12 @@ struct iwl_priv {
u8 key_mapping_key;
unsigned long ucode_key_table;
/* queue refcounts */
#define IWL_MAX_HW_QUEUES 32
unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
/* for each AC */
atomic_t queue_stop_count[4];
/* Indication if ieee80211_ops->open has been called */
u8 is_open;

查看文件

@@ -93,4 +93,56 @@ static inline int iwl_alloc_fw_desc(struct pci_dev *pci_dev,
return (desc->v_addr != NULL) ? 0 : -ENOMEM;
}
/*
* we have 8 bits used like this:
*
* 7 6 5 4 3 2 1 0
* | | | | | | | |
* | | | | | | +-+-------- AC queue (0-3)
* | | | | | |
* | +-+-+-+-+------------ HW A-MPDU queue
* |
* +---------------------- indicates agg queue
*/
static inline u8 iwl_virtual_agg_queue_num(u8 ac, u8 hwq)
{
BUG_ON(ac > 3); /* only have 2 bits */
BUG_ON(hwq > 31); /* only have 5 bits */
return 0x80 | (hwq << 2) | ac;
}
static inline void iwl_wake_queue(struct iwl_priv *priv, u8 queue)
{
u8 ac = queue;
u8 hwq = queue;
if (queue & 0x80) {
ac = queue & 3;
hwq = (queue >> 2) & 0x1f;
}
if (test_and_clear_bit(hwq, priv->queue_stopped))
if (atomic_dec_return(&priv->queue_stop_count[ac]) <= 0)
ieee80211_wake_queue(priv->hw, ac);
}
static inline void iwl_stop_queue(struct iwl_priv *priv, u8 queue)
{
u8 ac = queue;
u8 hwq = queue;
if (queue & 0x80) {
ac = queue & 3;
hwq = (queue >> 2) & 0x1f;
}
if (!test_and_set_bit(hwq, priv->queue_stopped))
if (atomic_inc_return(&priv->queue_stop_count[ac]) > 0)
ieee80211_stop_queue(priv->hw, ac);
}
#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
#endif /* __iwl_helpers_h__ */

查看文件

@@ -273,7 +273,7 @@ int iwl_power_update_mode(struct iwl_priv *priv, bool force)
if (priv->iw_mode != NL80211_IFTYPE_STATION)
final_mode = IWL_POWER_MODE_CAM;
if (!iwl_is_rfkill(priv) && !setting->power_disabled &&
if (iwl_is_ready_rf(priv) && !setting->power_disabled &&
((setting->power_mode != final_mode) || force)) {
struct iwl_powertable_cmd cmd;

查看文件

@@ -1138,8 +1138,10 @@ int iwl_sta_rx_agg_stop(struct iwl_priv *priv, const u8 *addr, int tid)
int sta_id;
sta_id = iwl_find_station(priv, addr);
if (sta_id == IWL_INVALID_STATION)
if (sta_id == IWL_INVALID_STATION) {
IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
return -ENXIO;
}
spin_lock_irqsave(&priv->sta_lock, flags);
priv->stations[sta_id].sta.station_flags_msk = 0;

查看文件

@@ -174,7 +174,7 @@ EXPORT_SYMBOL(iwl_tx_queue_free);
* Free all buffers.
* 0-fill, but do not free "txq" descriptor structure.
*/
static void iwl_cmd_queue_free(struct iwl_priv *priv)
void iwl_cmd_queue_free(struct iwl_priv *priv)
{
struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
struct iwl_queue *q = &txq->q;
@@ -193,12 +193,14 @@ static void iwl_cmd_queue_free(struct iwl_priv *priv)
/* De-alloc circular buffer of TFDs */
if (txq->q.n_bd)
pci_free_consistent(dev, sizeof(struct iwl_tfd) *
pci_free_consistent(dev, priv->hw_params.tfd_size *
txq->q.n_bd, txq->tfds, txq->q.dma_addr);
/* 0-fill queue descriptor structure */
memset(txq, 0, sizeof(*txq));
}
EXPORT_SYMBOL(iwl_cmd_queue_free);
/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
* DMA services
*
@@ -761,8 +763,10 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
hdr->seq_ctrl |= cpu_to_le16(seq_number);
seq_number += 0x10;
/* aggregation is on for this <sta,tid> */
if (info->flags & IEEE80211_TX_CTL_AMPDU)
if (info->flags & IEEE80211_TX_CTL_AMPDU) {
txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
swq_id = iwl_virtual_agg_queue_num(swq_id, txq_id);
}
priv->stations[sta_id].tid[tid].tfds_in_queue++;
}
@@ -893,7 +897,7 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
iwl_txq_update_write_ptr(priv, txq);
spin_unlock_irqrestore(&priv->lock, flags);
} else {
ieee80211_stop_queue(priv->hw, txq->swq_id);
iwl_stop_queue(priv, txq->swq_id);
}
}
@@ -1221,8 +1225,10 @@ int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
sta_id = iwl_find_station(priv, ra);
if (sta_id == IWL_INVALID_STATION)
if (sta_id == IWL_INVALID_STATION) {
IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
return -ENXIO;
}
if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
@@ -1429,7 +1435,7 @@ void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
priv->mac80211_registered &&
(agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
ieee80211_wake_queue(priv->hw, txq->swq_id);
iwl_wake_queue(priv, txq->swq_id);
iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
}

查看文件

@@ -485,14 +485,14 @@ static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
keyconf->keylen);
if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
if ((priv->stations_39[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
== STA_KEY_FLG_NO_ENC)
priv->stations[sta_id].sta.key.key_offset =
priv->stations_39[sta_id].sta.key.key_offset =
iwl_get_free_ucode_key_index(priv);
/* else, we are overriding an existing key => no need to allocated room
* in uCode. */
WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
WARN(priv->stations_39[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
"no space for a new key");
priv->stations_39[sta_id].sta.key.key_flags = key_flags;
@@ -560,7 +560,7 @@ static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
break;
default:
IWL_ERR(priv,"Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
ret = -EINVAL;
}
@@ -1168,7 +1168,7 @@ static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
spin_unlock_irqrestore(&priv->lock, flags);
}
ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
iwl_stop_queue(priv, skb_get_queue_mapping(skb));
}
return 0;
@@ -3773,15 +3773,19 @@ static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
}
#endif
if (conf->radio_enabled && iwl_radio_kill_sw_enable_radio(priv)) {
IWL_DEBUG_MAC80211(priv, "leave - RF-KILL - waiting for uCode\n");
goto out;
}
if (changed & IEEE80211_CONF_CHANGE_RADIO_ENABLED) {
if (conf->radio_enabled &&
iwl_radio_kill_sw_enable_radio(priv)) {
IWL_DEBUG_MAC80211(priv, "leave - RF-KILL - "
"waiting for uCode\n");
goto out;
}
if (!conf->radio_enabled) {
iwl_radio_kill_sw_disable_radio(priv);
IWL_DEBUG_MAC80211(priv, "leave - radio disabled\n");
goto out;
if (!conf->radio_enabled) {
iwl_radio_kill_sw_disable_radio(priv);
IWL_DEBUG_MAC80211(priv, "leave - radio disabled\n");
goto out;
}
}
if (iwl_is_rfkill(priv)) {
@@ -4546,11 +4550,6 @@ static ssize_t store_power_level(struct device *d,
mutex_lock(&priv->mutex);
if (!iwl_is_ready(priv)) {
ret = -EAGAIN;
goto out;
}
ret = strict_strtoul(buf, 10, &mode);
if (ret)
goto out;
@@ -4905,7 +4904,8 @@ static int iwl3945_setup_mac(struct iwl_priv *priv)
/* Tell mac80211 our characteristics */
hw->flags = IEEE80211_HW_SIGNAL_DBM |
IEEE80211_HW_NOISE_DBM;
IEEE80211_HW_NOISE_DBM |
IEEE80211_HW_SPECTRUM_MGMT;
hw->wiphy->interface_modes =
BIT(NL80211_IFTYPE_STATION) |

查看文件

@@ -33,22 +33,12 @@ struct rx_radiotap_hdr {
struct ieee80211_radiotap_header hdr;
u8 flags;
u8 rate;
u16 chan_freq;
u16 chan_flags;
u8 antenna;
u8 antsignal;
u16 rx_flags;
#if 0
u8 pad[IEEE80211_RADIOTAP_HDRLEN - 18];
#endif
} __attribute__ ((packed));
#define RX_RADIOTAP_PRESENT ( \
(1 << IEEE80211_RADIOTAP_FLAGS) | \
(1 << IEEE80211_RADIOTAP_RATE) | \
(1 << IEEE80211_RADIOTAP_CHANNEL) | \
(1 << IEEE80211_RADIOTAP_ANTENNA) | \
(1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) |\
(1 << IEEE80211_RADIOTAP_RX_FLAGS) | \
0)

查看文件

@@ -351,19 +351,11 @@ static int process_rxed_802_11_packet(struct lbs_private *priv,
radiotap_hdr.hdr.it_pad = 0;
radiotap_hdr.hdr.it_len = cpu_to_le16 (sizeof(struct rx_radiotap_hdr));
radiotap_hdr.hdr.it_present = cpu_to_le32 (RX_RADIOTAP_PRESENT);
/* unknown values */
radiotap_hdr.flags = 0;
radiotap_hdr.chan_freq = 0;
radiotap_hdr.chan_flags = 0;
radiotap_hdr.antenna = 0;
/* known values */
if (!(prxpd->status & cpu_to_le16(MRVDRV_RXPD_STATUS_OK)))
radiotap_hdr.flags |= IEEE80211_RADIOTAP_F_BADFCS;
radiotap_hdr.rate = convert_mv_rate_to_radiotap(prxpd->rx_rate);
/* XXX must check no carryout */
radiotap_hdr.antsignal = prxpd->snr + prxpd->nf;
radiotap_hdr.rx_flags = 0;
if (!(prxpd->status & cpu_to_le16(MRVDRV_RXPD_STATUS_OK)))
radiotap_hdr.rx_flags |= IEEE80211_RADIOTAP_F_RX_BADFCS;
//memset(radiotap_hdr.pad, 0x11, IEEE80211_RADIOTAP_HDRLEN - 18);
/* chop the rxpd */
skb_pull(skb, sizeof(struct rxpd));

查看文件

@@ -933,7 +933,6 @@ static int __init init_mac80211_hwsim(void)
BIT(NL80211_IFTYPE_STATION) |
BIT(NL80211_IFTYPE_AP) |
BIT(NL80211_IFTYPE_MESH_POINT);
hw->ampdu_queues = 1;
hw->flags = IEEE80211_HW_MFP_CAPABLE;
@@ -1041,6 +1040,9 @@ static int __init init_mac80211_hwsim(void)
break;
}
/* give the regulatory workqueue a chance to run */
if (regtest)
schedule_timeout_interruptible(1);
err = ieee80211_register_hw(hw);
if (err < 0) {
printk(KERN_DEBUG "mac80211_hwsim: "

查看文件

@@ -1,9 +1,10 @@
config P54_COMMON
tristate "Softmac Prism54 support"
depends on MAC80211 && WLAN_80211 && FW_LOADER && EXPERIMENTAL
depends on MAC80211 && WLAN_80211 && EXPERIMENTAL
select FW_LOADER
---help---
This is common code for isl38xx based cards.
This module does nothing by itself - the USB/PCI frontends
This is common code for isl38xx/stlc45xx based modules.
This module does nothing by itself - the USB/PCI/SPI front-ends
also need to be enabled in order to support any devices.
These devices require softmac firmware which can be found at
@@ -17,31 +18,6 @@ config P54_USB
select CRC32
---help---
This driver is for USB isl38xx based wireless cards.
These are USB based adapters found in devices such as:
3COM 3CRWE254G72
SMC 2862W-G
Accton 802.11g WN4501 USB
Siemens Gigaset USB
Netgear WG121
Netgear WG111
Medion 40900, Roper Europe
Shuttle PN15, Airvast WM168g, IOGear GWU513
Linksys WUSB54G
Linksys WUSB54G Portable
DLink DWL-G120 Spinnaker
DLink DWL-G122
Belkin F5D7050 ver 1000
Cohiba Proto board
SMC 2862W-G version 2
U.S. Robotics U5 802.11g Adapter
FUJITSU E-5400 USB D1700
Sagem XG703A
DLink DWL-G120 Cohiba
Spinnaker Proto board
Linksys WUSB54AG
Inventel UR054G
Spinnaker DUT
These devices require softmac firmware which can be found at
http://prism54.org/
@@ -64,10 +40,15 @@ config P54_PCI
config P54_SPI
tristate "Prism54 SPI (stlc45xx) support"
depends on P54_COMMON && SPI_MASTER
depends on P54_COMMON && SPI_MASTER && GENERIC_HARDIRQS
---help---
This driver is for stlc4550 or stlc4560 based wireless chips.
This driver is experimental, untested and will probably only work on
Nokia's N800/N810 Portable Internet Tablet.
If you choose to build a module, it'll be called p54spi.
config P54_LEDS
bool
depends on P54_COMMON && MAC80211_LEDS && (LEDS_CLASS = y || LEDS_CLASS = P54_COMMON)
default y

查看文件

@@ -21,9 +21,9 @@
#include <linux/etherdevice.h>
#include <net/mac80211.h>
#ifdef CONFIG_MAC80211_LEDS
#ifdef CONFIG_P54_LEDS
#include <linux/leds.h>
#endif /* CONFIG_MAC80211_LEDS */
#endif /* CONFIG_P54_LEDS */
#include "p54.h"
#include "p54common.h"
@@ -2420,7 +2420,7 @@ static int p54_set_key(struct ieee80211_hw *dev, enum set_key_cmd cmd,
return 0;
}
#ifdef CONFIG_MAC80211_LEDS
#ifdef CONFIG_P54_LEDS
static void p54_led_brightness_set(struct led_classdev *led_dev,
enum led_brightness brightness)
{
@@ -2508,7 +2508,7 @@ static void p54_unregister_leds(struct ieee80211_hw *dev)
if (priv->assoc_led.registered)
led_classdev_unregister(&priv->assoc_led.led_dev);
}
#endif /* CONFIG_MAC80211_LEDS */
#endif /* CONFIG_P54_LEDS */
static const struct ieee80211_ops p54_ops = {
.tx = p54_tx,
@@ -2592,11 +2592,11 @@ int p54_register_common(struct ieee80211_hw *dev, struct device *pdev)
return err;
}
#ifdef CONFIG_MAC80211_LEDS
#ifdef CONFIG_P54_LEDS
err = p54_init_leds(dev);
if (err)
return err;
#endif /* CONFIG_MAC80211_LEDS */
#endif /* CONFIG_P54_LEDS */
dev_info(pdev, "is registered as '%s'\n", wiphy_name(dev->wiphy));
return 0;
@@ -2610,9 +2610,9 @@ void p54_free_common(struct ieee80211_hw *dev)
kfree(priv->output_limit);
kfree(priv->curve_data);
#ifdef CONFIG_MAC80211_LEDS
#ifdef CONFIG_P54_LEDS
p54_unregister_leds(dev);
#endif /* CONFIG_MAC80211_LEDS */
#endif /* CONFIG_P54_LEDS */
}
EXPORT_SYMBOL_GPL(p54_free_common);

查看文件

@@ -2425,6 +2425,8 @@ static struct usb_device_id rt73usb_device_table[] = {
{ USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
/* Surecom */
{ USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
/* Tilgin */
{ USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
/* Philips */
{ USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
/* Planex */

查看文件

@@ -735,9 +735,9 @@ if (lp->tx_n_in_use > 0)
if (tx_status & AC_SFLD_OK) {
int ncollisions;
lp->stats.tx_packets++;
dev->stats.tx_packets++;
ncollisions = tx_status & AC_SFLD_MAXCOL;
lp->stats.collisions += ncollisions;
dev->stats.collisions += ncollisions;
#ifdef DEBUG_TX_INFO
if (ncollisions > 0)
printk(KERN_DEBUG
@@ -745,9 +745,9 @@ if (lp->tx_n_in_use > 0)
dev->name, ncollisions);
#endif
} else {
lp->stats.tx_errors++;
dev->stats.tx_errors++;
if (tx_status & AC_SFLD_S10) {
lp->stats.tx_carrier_errors++;
dev->stats.tx_carrier_errors++;
#ifdef DEBUG_TX_FAIL
printk(KERN_DEBUG
"%s: wv_complete(): tx error: no CS.\n",
@@ -755,7 +755,7 @@ if (lp->tx_n_in_use > 0)
#endif
}
if (tx_status & AC_SFLD_S9) {
lp->stats.tx_carrier_errors++;
dev->stats.tx_carrier_errors++;
#ifdef DEBUG_TX_FAIL
printk(KERN_DEBUG
"%s: wv_complete(): tx error: lost CTS.\n",
@@ -763,7 +763,7 @@ if (lp->tx_n_in_use > 0)
#endif
}
if (tx_status & AC_SFLD_S8) {
lp->stats.tx_fifo_errors++;
dev->stats.tx_fifo_errors++;
#ifdef DEBUG_TX_FAIL
printk(KERN_DEBUG
"%s: wv_complete(): tx error: slow DMA.\n",
@@ -771,7 +771,7 @@ if (lp->tx_n_in_use > 0)
#endif
}
if (tx_status & AC_SFLD_S6) {
lp->stats.tx_heartbeat_errors++;
dev->stats.tx_heartbeat_errors++;
#ifdef DEBUG_TX_FAIL
printk(KERN_DEBUG
"%s: wv_complete(): tx error: heart beat.\n",
@@ -779,7 +779,7 @@ if (lp->tx_n_in_use > 0)
#endif
}
if (tx_status & AC_SFLD_S5) {
lp->stats.tx_aborted_errors++;
dev->stats.tx_aborted_errors++;
#ifdef DEBUG_TX_FAIL
printk(KERN_DEBUG
"%s: wv_complete(): tx error: too many collisions.\n",
@@ -1346,20 +1346,6 @@ static void wv_init_info(struct net_device * dev)
* or wireless extensions
*/
/*------------------------------------------------------------------*/
/*
* Get the current Ethernet statistics. This may be called with the
* card open or closed.
* Used when the user read /proc/net/dev
*/
static en_stats *wavelan_get_stats(struct net_device * dev)
{
#ifdef DEBUG_IOCTL_TRACE
printk(KERN_DEBUG "%s: <>wavelan_get_stats()\n", dev->name);
#endif
return &((net_local *)netdev_priv(dev))->stats;
}
/*------------------------------------------------------------------*/
/*
@@ -2466,7 +2452,7 @@ wv_packet_read(struct net_device * dev, u16 buf_off, int sksize)
"%s: wv_packet_read(): could not alloc_skb(%d, GFP_ATOMIC).\n",
dev->name, sksize);
#endif
lp->stats.rx_dropped++;
dev->stats.rx_dropped++;
return;
}
@@ -2526,8 +2512,8 @@ wv_packet_read(struct net_device * dev, u16 buf_off, int sksize)
netif_rx(skb);
/* Keep statistics up to date */
lp->stats.rx_packets++;
lp->stats.rx_bytes += sksize;
dev->stats.rx_packets++;
dev->stats.rx_bytes += sksize;
#ifdef DEBUG_RX_TRACE
printk(KERN_DEBUG "%s: <-wv_packet_read()\n", dev->name);
@@ -2608,7 +2594,7 @@ static void wv_receive(struct net_device * dev)
#endif
} else { /* If reception was no successful */
lp->stats.rx_errors++;
dev->stats.rx_errors++;
#ifdef DEBUG_RX_INFO
printk(KERN_DEBUG
@@ -2624,7 +2610,7 @@ static void wv_receive(struct net_device * dev)
#endif
if ((fd.fd_status & FD_STATUS_S7) != 0) {
lp->stats.rx_length_errors++;
dev->stats.rx_length_errors++;
#ifdef DEBUG_RX_FAIL
printk(KERN_DEBUG
"%s: wv_receive(): frame too short.\n",
@@ -2633,7 +2619,7 @@ static void wv_receive(struct net_device * dev)
}
if ((fd.fd_status & FD_STATUS_S8) != 0) {
lp->stats.rx_over_errors++;
dev->stats.rx_over_errors++;
#ifdef DEBUG_RX_FAIL
printk(KERN_DEBUG
"%s: wv_receive(): rx DMA overrun.\n",
@@ -2642,7 +2628,7 @@ static void wv_receive(struct net_device * dev)
}
if ((fd.fd_status & FD_STATUS_S9) != 0) {
lp->stats.rx_fifo_errors++;
dev->stats.rx_fifo_errors++;
#ifdef DEBUG_RX_FAIL
printk(KERN_DEBUG
"%s: wv_receive(): ran out of resources.\n",
@@ -2651,7 +2637,7 @@ static void wv_receive(struct net_device * dev)
}
if ((fd.fd_status & FD_STATUS_S10) != 0) {
lp->stats.rx_frame_errors++;
dev->stats.rx_frame_errors++;
#ifdef DEBUG_RX_FAIL
printk(KERN_DEBUG
"%s: wv_receive(): alignment error.\n",
@@ -2660,7 +2646,7 @@ static void wv_receive(struct net_device * dev)
}
if ((fd.fd_status & FD_STATUS_S11) != 0) {
lp->stats.rx_crc_errors++;
dev->stats.rx_crc_errors++;
#ifdef DEBUG_RX_FAIL
printk(KERN_DEBUG
"%s: wv_receive(): CRC error.\n",
@@ -2826,7 +2812,7 @@ static int wv_packet_write(struct net_device * dev, void *buf, short length)
dev->trans_start = jiffies;
/* Keep stats up to date. */
lp->stats.tx_bytes += length;
dev->stats.tx_bytes += length;
if (lp->tx_first_in_use == I82586NULL)
lp->tx_first_in_use = txblock;
@@ -4038,6 +4024,22 @@ static int wavelan_close(struct net_device * dev)
return 0;
}
static const struct net_device_ops wavelan_netdev_ops = {
.ndo_open = wavelan_open,
.ndo_stop = wavelan_close,
.ndo_start_xmit = wavelan_packet_xmit,
.ndo_set_multicast_list = wavelan_set_multicast_list,
.ndo_tx_timeout = wavelan_watchdog,
.ndo_change_mtu = eth_change_mtu,
.ndo_validate_addr = eth_validate_addr,
#ifdef SET_MAC_ADDRESS
.ndo_set_mac_address = wavelan_set_mac_address
#else
.ndo_set_mac_address = eth_mac_addr,
#endif
};
/*------------------------------------------------------------------*/
/*
* Probe an I/O address, and if the WaveLAN is there configure the
@@ -4130,17 +4132,8 @@ static int __init wavelan_config(struct net_device *dev, unsigned short ioaddr)
/* Init spinlock */
spin_lock_init(&lp->spinlock);
dev->open = wavelan_open;
dev->stop = wavelan_close;
dev->hard_start_xmit = wavelan_packet_xmit;
dev->get_stats = wavelan_get_stats;
dev->set_multicast_list = &wavelan_set_multicast_list;
dev->tx_timeout = &wavelan_watchdog;
dev->watchdog_timeo = WATCHDOG_JIFFIES;
#ifdef SET_MAC_ADDRESS
dev->set_mac_address = &wavelan_set_mac_address;
#endif /* SET_MAC_ADDRESS */
dev->netdev_ops = &wavelan_netdev_ops;
dev->watchdog_timeo = WATCHDOG_JIFFIES;
dev->wireless_handlers = &wavelan_handler_def;
lp->wireless_data.spy_data = &lp->spy_data;
dev->wireless_data = &lp->wireless_data;

查看文件

@@ -459,11 +459,9 @@ static const char *version = "wavelan.c : v24 (SMP + wireless extensions) 11/12/
/****************************** TYPES ******************************/
/* Shortcuts */
typedef struct net_device_stats en_stats;
typedef struct iw_statistics iw_stats;
typedef struct iw_quality iw_qual;
typedef struct iw_freq iw_freq;
typedef struct net_local net_local;
typedef struct iw_freq iw_freq;typedef struct net_local net_local;
typedef struct timer_list timer_list;
/* Basic types */
@@ -475,15 +473,12 @@ typedef u_char mac_addr[WAVELAN_ADDR_SIZE]; /* Hardware address */
* For each network interface, Linux keeps data in two structures: "device"
* keeps the generic data (same format for everybody) and "net_local" keeps
* additional specific data.
* Note that some of this specific data is in fact generic (en_stats, for
* example).
*/
struct net_local
{
net_local * next; /* linked list of the devices */
struct net_device * dev; /* reverse link */
spinlock_t spinlock; /* Serialize access to the hardware (SMP) */
en_stats stats; /* Ethernet interface statistics */
int nresets; /* number of hardware resets */
u_char reconfig_82586; /* We need to reconfigure the controller. */
u_char promiscuous; /* promiscuous mode */
@@ -601,8 +596,6 @@ static void
static inline void
wv_init_info(struct net_device *); /* display startup info */
/* ------------------- IOCTL, STATS & RECONFIG ------------------- */
static en_stats *
wavelan_get_stats(struct net_device *); /* Give stats /proc/net/dev */
static iw_stats *
wavelan_get_wireless_stats(struct net_device *);
static void