clk: add CLK_SET_RATE_NO_REPARENT flag
Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
James Hogan
committed by
Mike Turquette
Mike Turquette
parent
71472c0c06
commit
819c1de344
@@ -294,7 +294,8 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
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clk_register_clkdev(clk, NULL, "a9400000.i2s");
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clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
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ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(i2s_ref_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
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I2S_REF_PCLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "i2s_ref_clk", NULL);
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@@ -313,57 +314,66 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
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clk_register_clkdev(clk, "hclk", "ab000000.eth");
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clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
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ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(uartx_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
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SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "a9300000.serial");
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clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
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ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(sdhci_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
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0, &_lock);
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clk_register_clkdev(clk, NULL, "70000000.sdhci");
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clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
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ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
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SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
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ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT,
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SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK,
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0, &_lock);
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clk_register_clkdev(clk, NULL, "smii_pclk");
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clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
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clk_register_clkdev(clk, NULL, "smii");
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clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
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ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(uartx_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
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0, &_lock);
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clk_register_clkdev(clk, NULL, "a3000000.serial");
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clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
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ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(uartx_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
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SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "a4000000.serial");
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clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
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ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(uartx_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
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SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "a9100000.serial");
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clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
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ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(uartx_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
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SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "a9200000.serial");
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clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
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ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(uartx_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
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SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "60000000.serial");
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clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
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ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(uartx_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
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SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "60100000.serial");
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@@ -427,7 +437,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
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clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
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ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(uart0_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
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&_lock);
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clk_register_clkdev(clk, "uart0_mclk", NULL);
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@@ -444,7 +455,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
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clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
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ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(firda_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
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&_lock);
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clk_register_clkdev(clk, "firda_mclk", NULL);
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@@ -458,14 +470,16 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
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clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
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ARRAY_SIZE(gpt_rtbl), &_lock);
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clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
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ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(gpt0_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt0");
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clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
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ARRAY_SIZE(gpt_rtbl), &_lock);
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clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
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ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(gpt1_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt1_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
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@@ -476,7 +490,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
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clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
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ARRAY_SIZE(gpt_rtbl), &_lock);
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clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
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ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT,
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ARRAY_SIZE(gpt2_parents),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt2_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
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@@ -498,9 +513,9 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
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clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
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ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
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GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
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&_lock);
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ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT,
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CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT,
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GEN_SYNTH2_3_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
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clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
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@@ -540,8 +555,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
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clk_register_clkdev(clk, "ahbmult2_clk", NULL);
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clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
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ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
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MCTR_CLK_MASK, 0, &_lock);
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ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
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PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "ddr_clk", NULL);
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clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
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