MIPS: Alchemy: Au1300 SoC support
Add basic support for the Au1300 variant(s): - New GPIO/Interrupt controller - DBDMA ids - USB setup - MMC support - enable various PSC drivers - detection code. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
committed by
Ralf Baechle
Ralf Baechle
parent
fb469f084f
commit
809f36c6f4
@@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
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#define ALCHEMY_CPU_AU1100 2
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#define ALCHEMY_CPU_AU1550 3
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#define ALCHEMY_CPU_AU1200 4
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#define ALCHEMY_CPU_AU1300 5
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static inline int alchemy_get_cputype(void)
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{
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@@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void)
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case 0x05030000:
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return ALCHEMY_CPU_AU1200;
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break;
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case 0x800c0000:
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return ALCHEMY_CPU_AU1300;
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break;
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}
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return ALCHEMY_CPU_UNKNOWN;
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@@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type)
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{
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switch (type) {
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case ALCHEMY_CPU_AU1000:
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case ALCHEMY_CPU_AU1300:
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return 4;
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case ALCHEMY_CPU_AU1500:
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case ALCHEMY_CPU_AU1200:
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@@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void);
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/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
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void alchemy_sleep_au1000(void);
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void alchemy_sleep_au1550(void);
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void alchemy_sleep_au1300(void);
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void au_sleep(void);
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/* USB: drivers/usb/host/alchemy-common.c */
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@@ -251,6 +257,7 @@ enum alchemy_usb_block {
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ALCHEMY_USB_UDC0,
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ALCHEMY_USB_EHCI0,
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ALCHEMY_USB_OTG0,
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ALCHEMY_USB_OHCI1,
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};
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int alchemy_usb_control(int block, int enable);
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@@ -263,14 +270,92 @@ struct alchemy_pci_platdata {
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unsigned long pci_cfg_clr;
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};
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/* SOC Interrupt numbers */
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/* Multifunction pins: Each of these pins can either be assigned to the
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* GPIO controller or a on-chip peripheral.
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* Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
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* assign one of these to either the GPIO controller or the device.
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*/
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enum au1300_multifunc_pins {
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/* wake-from-str pins 0-3 */
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AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
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AU1300_PIN_WAKE3,
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/* external clock sources for PSCs: 4-5 */
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AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
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/* 8bit MMC interface on SD0: 6-9 */
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AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
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AU1300_PIN_SD0DAT7,
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/* aux clk input for freqgen 3: 10 */
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AU1300_PIN_FG3AUX,
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/* UART1 pins: 11-18 */
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AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
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AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
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AU1300_PIN_U1RX, AU1300_PIN_U1TX,
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/* UART0 pins: 19-24 */
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AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
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AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
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/* UART2: 25-26 */
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AU1300_PIN_U2RX, AU1300_PIN_U2TX,
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/* UART3: 27-28 */
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AU1300_PIN_U3RX, AU1300_PIN_U3TX,
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/* LCD controller PWMs, ext pixclock: 29-31 */
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AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
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/* SD1 interface: 32-37 */
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AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
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AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
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/* SD2 interface: 38-43 */
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AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
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AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
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/* PSC0/1 clocks: 44-45 */
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AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
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/* PSCs: 46-49/50-53/54-57/58-61 */
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AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
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AU1300_PIN_PSC0D1,
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AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
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AU1300_PIN_PSC1D1,
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AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
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AU1300_PIN_PSC2D1,
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AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
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AU1300_PIN_PSC3D1,
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/* PCMCIA interface: 62-70 */
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AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
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AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
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AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
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/* camera interface H/V sync inputs: 71-72 */
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AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
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/* PSC2/3 clocks: 73-74 */
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AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
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};
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/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
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extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
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extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
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extern void au1300_set_irq_priority(unsigned int irq, int p);
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extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
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/* Au1300 allows to disconnect certain blocks from internal power supply */
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enum au1300_vss_block {
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AU1300_VSS_MPE = 0,
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AU1300_VSS_BSA,
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AU1300_VSS_GPE,
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AU1300_VSS_MGP,
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};
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extern void au1300_vss_block_control(int block, int enable);
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/* SOC Interrupt numbers */
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/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
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#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
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#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
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#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
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#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
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#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
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/* Au1300-style (GPIC): 1 controller with up to 128 sources */
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#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
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#define ALCHEMY_GPIC_INT_NUM 128
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#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
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enum soc_au1000_ints {
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AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
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AU1000_UART0_INT = AU1000_FIRST_INT,
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@@ -591,24 +676,77 @@ enum soc_au1200_ints {
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#endif /* !defined (_LANGUAGE_ASSEMBLY) */
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/* Au1300 peripheral interrupt numbers */
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#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
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#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
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#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
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#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
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#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
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#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
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#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
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#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
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#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
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#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
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#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
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#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
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#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
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#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
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#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
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#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
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#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
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#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
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#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
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#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
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#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
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#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
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#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
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#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
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#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
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#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
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#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
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#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
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#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
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#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
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#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
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#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
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#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
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/**********************************************************************/
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/*
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* Physical base addresses for integrated peripherals
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* 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
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* 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
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*/
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#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
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#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
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#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
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#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
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#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
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#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
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#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
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#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
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#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
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#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
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#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
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#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
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#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */
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#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
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#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
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#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
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#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
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#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
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#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
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#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */
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#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
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#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
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#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
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#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
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#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
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#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
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#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
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#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
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#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
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#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
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#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
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#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
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#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
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#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
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@@ -622,37 +760,96 @@ enum soc_au1200_ints {
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#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
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#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
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#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
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#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */
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#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
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#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
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#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
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#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
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#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
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#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
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#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
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#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
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#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
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#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
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#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
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#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
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#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
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#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */
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#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
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#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
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#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
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#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
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#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
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#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
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#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
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#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
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#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
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#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
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#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
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#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
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#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
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#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
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#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
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#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
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#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
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#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
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#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
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#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
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#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */
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#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
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#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
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#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
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#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
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#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
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#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */
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#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */
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#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */
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#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
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#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
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#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
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/**********************************************************************/
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/*
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* Au1300 GPIO+INT controller (GPIC) register offsets and bits
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* Registers are 128bits (0x10 bytes), divided into 4 "banks".
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*/
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#define AU1300_GPIC_PINVAL 0x0000
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#define AU1300_GPIC_PINVALCLR 0x0010
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#define AU1300_GPIC_IPEND 0x0020
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#define AU1300_GPIC_PRIENC 0x0030
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#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
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#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
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#define AU1300_GPIC_DMASEL 0x0060
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#define AU1300_GPIC_DEVSEL 0x0080
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#define AU1300_GPIC_DEVCLR 0x0090
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#define AU1300_GPIC_RSTVAL 0x00a0
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/* pin configuration space. one 32bit register for up to 128 IRQs */
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#define AU1300_GPIC_PINCFG 0x1000
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#define GPIC_GPIO_TO_BIT(gpio) \
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(1 << ((gpio) & 0x1f))
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#define GPIC_GPIO_BANKOFF(gpio) \
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(((gpio) >> 5) * 4)
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/* Pin Control bits: who owns the pin, what does it do */
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#define GPIC_CFG_PC_GPIN 0
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#define GPIC_CFG_PC_DEV 1
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#define GPIC_CFG_PC_GPOLOW 2
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#define GPIC_CFG_PC_GPOHIGH 3
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#define GPIC_CFG_PC_MASK 3
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/* assign pin to MIPS IRQ line */
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#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
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#define GPIC_CFG_IL_MASK (3 << 2)
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/* pin interrupt type setup */
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#define GPIC_CFG_IC_OFF (0 << 4)
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#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
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#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
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#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
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#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
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#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
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#define GPIC_CFG_IC_MASK (7 << 4)
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/* allow interrupt to wake cpu from 'wait' */
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#define GPIC_CFG_IDLEWAKE (1 << 7)
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/***********************************************************************/
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|
||||
/* Au1000 SDRAM memory controller register offsets */
|
||||
#define AU1000_MEM_SDMODE0 0x0000
|
||||
|
||||
@@ -130,8 +130,10 @@ struct au1xmmc_platform_data {
|
||||
#define SD_CONFIG2_DF (0x00000008)
|
||||
#define SD_CONFIG2_DC (0x00000010)
|
||||
#define SD_CONFIG2_xx2 (0x000000e0)
|
||||
#define SD_CONFIG2_BB (0x00000080)
|
||||
#define SD_CONFIG2_WB (0x00000100)
|
||||
#define SD_CONFIG2_RW (0x00000200)
|
||||
#define SD_CONFIG2_DP (0x00000400)
|
||||
|
||||
|
||||
/*
|
||||
|
||||
@@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc {
|
||||
#define AU1200_DSCR_CMD0_PSC1_SYNC 25
|
||||
#define AU1200_DSCR_CMD0_CIM_SYNC 26
|
||||
|
||||
#define AU1300_DSCR_CMD0_UART0_TX 0
|
||||
#define AU1300_DSCR_CMD0_UART0_RX 1
|
||||
#define AU1300_DSCR_CMD0_UART1_TX 2
|
||||
#define AU1300_DSCR_CMD0_UART1_RX 3
|
||||
#define AU1300_DSCR_CMD0_UART2_TX 4
|
||||
#define AU1300_DSCR_CMD0_UART2_RX 5
|
||||
#define AU1300_DSCR_CMD0_UART3_TX 6
|
||||
#define AU1300_DSCR_CMD0_UART3_RX 7
|
||||
#define AU1300_DSCR_CMD0_SDMS_TX0 8
|
||||
#define AU1300_DSCR_CMD0_SDMS_RX0 9
|
||||
#define AU1300_DSCR_CMD0_SDMS_TX1 10
|
||||
#define AU1300_DSCR_CMD0_SDMS_RX1 11
|
||||
#define AU1300_DSCR_CMD0_AES_TX 12
|
||||
#define AU1300_DSCR_CMD0_AES_RX 13
|
||||
#define AU1300_DSCR_CMD0_PSC0_TX 14
|
||||
#define AU1300_DSCR_CMD0_PSC0_RX 15
|
||||
#define AU1300_DSCR_CMD0_PSC1_TX 16
|
||||
#define AU1300_DSCR_CMD0_PSC1_RX 17
|
||||
#define AU1300_DSCR_CMD0_PSC2_TX 18
|
||||
#define AU1300_DSCR_CMD0_PSC2_RX 19
|
||||
#define AU1300_DSCR_CMD0_PSC3_TX 20
|
||||
#define AU1300_DSCR_CMD0_PSC3_RX 21
|
||||
#define AU1300_DSCR_CMD0_LCD 22
|
||||
#define AU1300_DSCR_CMD0_NAND_FLASH 23
|
||||
#define AU1300_DSCR_CMD0_SDMS_TX2 24
|
||||
#define AU1300_DSCR_CMD0_SDMS_RX2 25
|
||||
#define AU1300_DSCR_CMD0_CIM_SYNC 26
|
||||
#define AU1300_DSCR_CMD0_UDMA 27
|
||||
#define AU1300_DSCR_CMD0_DMA_REQ0 28
|
||||
#define AU1300_DSCR_CMD0_DMA_REQ1 29
|
||||
|
||||
#define DSCR_CMD0_THROTTLE 30
|
||||
#define DSCR_CMD0_ALWAYS 31
|
||||
#define DSCR_NDEV_IDS 32
|
||||
|
||||
241
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
Normal file
241
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
Normal file
@@ -0,0 +1,241 @@
|
||||
/*
|
||||
* gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
|
||||
*
|
||||
* Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
|
||||
*/
|
||||
|
||||
#ifndef _GPIO_AU1300_H_
|
||||
#define _GPIO_AU1300_H_
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
|
||||
/* with the current GPIC design, up to 128 GPIOs are possible.
|
||||
* The only implementation so far is in the Au1300, which has 75 externally
|
||||
* available GPIOs.
|
||||
*/
|
||||
#define AU1300_GPIO_BASE 0
|
||||
#define AU1300_GPIO_NUM 75
|
||||
#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
|
||||
|
||||
#define AU1300_GPIC_ADDR \
|
||||
(void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
|
||||
|
||||
static inline int au1300_gpio_get_value(unsigned int gpio)
|
||||
{
|
||||
void __iomem *roff = AU1300_GPIC_ADDR;
|
||||
int bit;
|
||||
|
||||
gpio -= AU1300_GPIO_BASE;
|
||||
roff += GPIC_GPIO_BANKOFF(gpio);
|
||||
bit = GPIC_GPIO_TO_BIT(gpio);
|
||||
return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
|
||||
}
|
||||
|
||||
static inline int au1300_gpio_direction_input(unsigned int gpio)
|
||||
{
|
||||
void __iomem *roff = AU1300_GPIC_ADDR;
|
||||
unsigned long bit;
|
||||
|
||||
gpio -= AU1300_GPIO_BASE;
|
||||
|
||||
roff += GPIC_GPIO_BANKOFF(gpio);
|
||||
bit = GPIC_GPIO_TO_BIT(gpio);
|
||||
__raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
|
||||
wmb();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int au1300_gpio_set_value(unsigned int gpio, int v)
|
||||
{
|
||||
void __iomem *roff = AU1300_GPIC_ADDR;
|
||||
unsigned long bit;
|
||||
|
||||
gpio -= AU1300_GPIO_BASE;
|
||||
|
||||
roff += GPIC_GPIO_BANKOFF(gpio);
|
||||
bit = GPIC_GPIO_TO_BIT(gpio);
|
||||
__raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
|
||||
: AU1300_GPIC_PINVALCLR));
|
||||
wmb();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
|
||||
{
|
||||
/* hw switches to output automatically */
|
||||
return au1300_gpio_set_value(gpio, v);
|
||||
}
|
||||
|
||||
static inline int au1300_gpio_to_irq(unsigned int gpio)
|
||||
{
|
||||
return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
|
||||
}
|
||||
|
||||
static inline int au1300_irq_to_gpio(unsigned int irq)
|
||||
{
|
||||
return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
|
||||
}
|
||||
|
||||
static inline int au1300_gpio_is_valid(unsigned int gpio)
|
||||
{
|
||||
int ret;
|
||||
|
||||
switch (alchemy_get_cputype()) {
|
||||
case ALCHEMY_CPU_AU1300:
|
||||
ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
|
||||
break;
|
||||
default:
|
||||
ret = 0;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int au1300_gpio_cansleep(unsigned int gpio)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* hardware remembers gpio 0-63 levels on powerup */
|
||||
static inline int au1300_gpio_getinitlvl(unsigned int gpio)
|
||||
{
|
||||
void __iomem *roff = AU1300_GPIC_ADDR;
|
||||
unsigned long v;
|
||||
|
||||
if (unlikely(gpio > 63))
|
||||
return 0;
|
||||
else if (gpio > 31) {
|
||||
gpio -= 32;
|
||||
roff += 4;
|
||||
}
|
||||
|
||||
v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
|
||||
return (v >> gpio) & 1;
|
||||
}
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
/* Linux gpio framework integration.
|
||||
*
|
||||
* 4 use cases of Alchemy GPIOS:
|
||||
*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
|
||||
* Board must register gpiochips.
|
||||
*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
|
||||
* A gpiochip for the 75 GPIOs is registered.
|
||||
*
|
||||
*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
|
||||
* the boards' gpio.h must provide the linux gpio wrapper functions,
|
||||
*
|
||||
*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
|
||||
* inlinable gpio functions are provided which enable access to the
|
||||
* Au1300 gpios only by using the numbers straight out of the data-
|
||||
* sheets.
|
||||
|
||||
* Cases 1 and 3 are intended for boards which want to provide their own
|
||||
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
|
||||
* which are in part provided by spare Au1300 GPIO pins and in part by
|
||||
* an external FPGA but you still want them to be accssible in linux
|
||||
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
|
||||
* as required).
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_GPIOLIB
|
||||
|
||||
#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
|
||||
|
||||
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
|
||||
|
||||
static inline int gpio_direction_input(unsigned int gpio)
|
||||
{
|
||||
return au1300_gpio_direction_input(gpio);
|
||||
}
|
||||
|
||||
static inline int gpio_direction_output(unsigned int gpio, int v)
|
||||
{
|
||||
return au1300_gpio_direction_output(gpio, v);
|
||||
}
|
||||
|
||||
static inline int gpio_get_value(unsigned int gpio)
|
||||
{
|
||||
return au1300_gpio_get_value(gpio);
|
||||
}
|
||||
|
||||
static inline void gpio_set_value(unsigned int gpio, int v)
|
||||
{
|
||||
au1300_gpio_set_value(gpio, v);
|
||||
}
|
||||
|
||||
static inline int gpio_get_value_cansleep(unsigned gpio)
|
||||
{
|
||||
return gpio_get_value(gpio);
|
||||
}
|
||||
|
||||
static inline void gpio_set_value_cansleep(unsigned gpio, int value)
|
||||
{
|
||||
gpio_set_value(gpio, value);
|
||||
}
|
||||
|
||||
static inline int gpio_is_valid(unsigned int gpio)
|
||||
{
|
||||
return au1300_gpio_is_valid(gpio);
|
||||
}
|
||||
|
||||
static inline int gpio_cansleep(unsigned int gpio)
|
||||
{
|
||||
return au1300_gpio_cansleep(gpio);
|
||||
}
|
||||
|
||||
static inline int gpio_to_irq(unsigned int gpio)
|
||||
{
|
||||
return au1300_gpio_to_irq(gpio);
|
||||
}
|
||||
|
||||
static inline int irq_to_gpio(unsigned int irq)
|
||||
{
|
||||
return au1300_irq_to_gpio(irq);
|
||||
}
|
||||
|
||||
static inline int gpio_request(unsigned int gpio, const char *label)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void gpio_free(unsigned int gpio)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline void gpio_unexport(unsigned gpio)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int gpio_export(unsigned gpio, bool direction_may_change)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int gpio_export_link(struct device *dev, const char *name,
|
||||
unsigned gpio)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
|
||||
|
||||
#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
|
||||
|
||||
#endif /* CONFIG GPIOLIB */
|
||||
|
||||
#endif /* _GPIO_AU1300_H_ */
|
||||
@@ -12,6 +12,7 @@
|
||||
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-au1x00/gpio-au1000.h>
|
||||
#include <asm/mach-au1x00/gpio-au1300.h>
|
||||
|
||||
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
|
||||
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
|
||||
@@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq)
|
||||
switch (alchemy_get_cputype()) {
|
||||
case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
|
||||
return alchemy_irq_to_gpio(irq);
|
||||
case ALCHEMY_CPU_AU1300:
|
||||
return au1300_irq_to_gpio(irq);
|
||||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user