drm/i915: Fix gen2 and hsw+ scanline counter
On gen2 the scanline counter behaves a bit differently from the later generations. Instead of adding one to the raw scanline counter value, we must subtract one. On HSW/BDW the scanline counter requires a +2 adjustment on HDMI outputs. DP outputs on the on the other require the typical +1 adjustment. As the fixup we must apply to the hardware scanline counter depends on several factors, compute the desired offset at modeset time and tuck it away for when it's needed. v2: Clarify HSW+ situation Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: "Akash Goel <akash.goels@gmail.com>" Reviewed-by: "Sourab Gupta <sourabgupta@gmail.com>" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78997 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@@ -889,9 +889,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
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struct drm_i915_private *dev_priv = dev->dev_private;
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const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
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enum pipe pipe = crtc->pipe;
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int vtotal = mode->crtc_vtotal;
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int position;
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int position, vtotal;
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vtotal = mode->crtc_vtotal;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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vtotal /= 2;
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@@ -901,14 +901,10 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
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position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
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/*
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* Scanline counter increments at leading edge of hsync, and
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* it starts counting from vtotal-1 on the first active line.
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* That means the scanline counter value is always one less
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* than what we would expect. Ie. just after start of vblank,
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* which also occurs at start of hsync (on the last active line),
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* the scanline counter will read vblank_start-1.
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* See update_scanline_offset() for the details on the
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* scanline_offset adjustment.
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*/
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return (position + 1) % vtotal;
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return (position + crtc->scanline_offset) % vtotal;
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}
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static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
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