xiaomi-sm8450/android_kernel_xiaomi_sm8450
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Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next

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* clk-hisi-usb:
  clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC

* clk-silent-bulk:
  clk: bulk: silently error out on EPROBE_DEFER

* clk-mtk-hdmi:
  clk: mediatek: correct the clocks for MT2701 HDMI PHY module

* clk-mtk-mali:
  clk: mediatek: add g3dsys support for MT2701 and MT7623
  dt-bindings: reset: mediatek: add entry for Mali-450 node to refer
  dt-bindings: clock: mediatek: add entry for Mali-450 node to refer
  dt-bindings: clock: mediatek: add g3dsys bindings

* clk-imx6ul-ccosr:
  clk: imx: Add new clo01 and clo2 controlled by CCOSR
This commit is contained in:
Stephen Boyd
2018-06-04 12:27:40 -07:00
parent b7c82cec04 80820a7bc8 329470f2d5 bf61099a21 a11ca68969 f5a4670de9
commit 7fa50aa559
12 changed files with 219 additions and 25 deletions
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20
include/dt-bindings/clock/mt2701-clk.h
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@@ -171,13 +171,12 @@
#define CLK_TOP_8BDAC 151
#define CLK_TOP_WBG_DIG_416M 152
#define CLK_TOP_DPI 153
#define CLK_TOP_HDMITX_CLKDIG_CTS 154
#define CLK_TOP_DSI0_LNTC_DSI 155
#define CLK_TOP_AUD_EXT1 156
#define CLK_TOP_AUD_EXT2 157
#define CLK_TOP_NFI1X_PAD 158
#define CLK_TOP_AXISEL_D4 159
#define CLK_TOP_NR 160
#define CLK_TOP_DSI0_LNTC_DSI 154
#define CLK_TOP_AUD_EXT1 155
#define CLK_TOP_AUD_EXT2 156
#define CLK_TOP_NFI1X_PAD 157
#define CLK_TOP_AXISEL_D4 158
#define CLK_TOP_NR 159
/* APMIXEDSYS */
@@ -194,7 +193,8 @@
#define CLK_APMIXED_HADDS2PLL 11
#define CLK_APMIXED_AUD2PLL 12
#define CLK_APMIXED_TVD2PLL 13
#define CLK_APMIXED_NR 14
#define CLK_APMIXED_HDMI_REF 14
#define CLK_APMIXED_NR 15
/* DDRPHY */
@@ -431,6 +431,10 @@
#define CLK_ETHSYS_CRYPTO 8
#define CLK_ETHSYS_NR 9
/* G3DSYS */
#define CLK_G3DSYS_CORE 1
#define CLK_G3DSYS_NR 2
/* BDP */
#define CLK_BDP_BRG_BA 1