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Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next

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* clk-hisi-usb:
  clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC

* clk-silent-bulk:
  clk: bulk: silently error out on EPROBE_DEFER

* clk-mtk-hdmi:
  clk: mediatek: correct the clocks for MT2701 HDMI PHY module

* clk-mtk-mali:
  clk: mediatek: add g3dsys support for MT2701 and MT7623
  dt-bindings: reset: mediatek: add entry for Mali-450 node to refer
  dt-bindings: clock: mediatek: add entry for Mali-450 node to refer
  dt-bindings: clock: mediatek: add g3dsys bindings

* clk-imx6ul-ccosr:
  clk: imx: Add new clo01 and clo2 controlled by CCOSR
This commit is contained in:
Stephen Boyd
2018-06-04 12:27:40 -07:00
parent b7c82cec04 80820a7bc8 329470f2d5 bf61099a21 a11ca68969 f5a4670de9
commit 7fa50aa559
12 changed files with 219 additions and 25 deletions
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8
include/dt-bindings/clock/histb-clock.h
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@@ -62,6 +62,14 @@
#define HISTB_USB2_PHY1_REF_CLK 40
#define HISTB_USB2_PHY2_REF_CLK 41
#define HISTB_COMBPHY0_CLK 42
#define HISTB_USB3_BUS_CLK 43
#define HISTB_USB3_UTMI_CLK 44
#define HISTB_USB3_PIPE_CLK 45
#define HISTB_USB3_SUSPEND_CLK 46
#define HISTB_USB3_BUS_CLK1 47
#define HISTB_USB3_UTMI_CLK1 48
#define HISTB_USB3_PIPE_CLK1 49
#define HISTB_USB3_SUSPEND_CLK1 50
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1

33
include/dt-bindings/clock/imx6ul-clock.h
View File

@@ -235,20 +235,27 @@
#define IMX6UL_CLK_CSI_PODF 222
#define IMX6UL_CLK_PLL3_120M 223
#define IMX6UL_CLK_KPP 224
#define IMX6UL_CLK_CKO1_SEL 225
#define IMX6UL_CLK_CKO1_PODF 226
#define IMX6UL_CLK_CKO1 227
#define IMX6UL_CLK_CKO2_SEL 228
#define IMX6UL_CLK_CKO2_PODF 229
#define IMX6UL_CLK_CKO2 230
#define IMX6UL_CLK_CKO 231
/* For i.MX6ULL */
#define IMX6ULL_CLK_ESAI_PRED 225
#define IMX6ULL_CLK_ESAI_PODF 226
#define IMX6ULL_CLK_ESAI_EXTAL 227
#define IMX6ULL_CLK_ESAI_MEM 228
#define IMX6ULL_CLK_ESAI_IPG 229
#define IMX6ULL_CLK_DCP_CLK 230
#define IMX6ULL_CLK_EPDC_PRE_SEL 231
#define IMX6ULL_CLK_EPDC_SEL 232
#define IMX6ULL_CLK_EPDC_PODF 233
#define IMX6ULL_CLK_EPDC_ACLK 234
#define IMX6ULL_CLK_EPDC_PIX 235
#define IMX6ULL_CLK_ESAI_SEL 236
#define IMX6UL_CLK_END 237
#define IMX6ULL_CLK_ESAI_PRED 232
#define IMX6ULL_CLK_ESAI_PODF 233
#define IMX6ULL_CLK_ESAI_EXTAL 234
#define IMX6ULL_CLK_ESAI_MEM 235
#define IMX6ULL_CLK_ESAI_IPG 236
#define IMX6ULL_CLK_DCP_CLK 237
#define IMX6ULL_CLK_EPDC_PRE_SEL 238
#define IMX6ULL_CLK_EPDC_SEL 239
#define IMX6ULL_CLK_EPDC_PODF 240
#define IMX6ULL_CLK_EPDC_ACLK 241
#define IMX6ULL_CLK_EPDC_PIX 242
#define IMX6ULL_CLK_ESAI_SEL 243
#define IMX6UL_CLK_END 244
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */

20
include/dt-bindings/clock/mt2701-clk.h
View File

@@ -171,13 +171,12 @@
#define CLK_TOP_8BDAC 151
#define CLK_TOP_WBG_DIG_416M 152
#define CLK_TOP_DPI 153
#define CLK_TOP_HDMITX_CLKDIG_CTS 154
#define CLK_TOP_DSI0_LNTC_DSI 155
#define CLK_TOP_AUD_EXT1 156
#define CLK_TOP_AUD_EXT2 157
#define CLK_TOP_NFI1X_PAD 158
#define CLK_TOP_AXISEL_D4 159
#define CLK_TOP_NR 160
#define CLK_TOP_DSI0_LNTC_DSI 154
#define CLK_TOP_AUD_EXT1 155
#define CLK_TOP_AUD_EXT2 156
#define CLK_TOP_NFI1X_PAD 157
#define CLK_TOP_AXISEL_D4 158
#define CLK_TOP_NR 159
/* APMIXEDSYS */
@@ -194,7 +193,8 @@
#define CLK_APMIXED_HADDS2PLL 11
#define CLK_APMIXED_AUD2PLL 12
#define CLK_APMIXED_TVD2PLL 13
#define CLK_APMIXED_NR 14
#define CLK_APMIXED_HDMI_REF 14
#define CLK_APMIXED_NR 15
/* DDRPHY */
@@ -431,6 +431,10 @@
#define CLK_ETHSYS_CRYPTO 8
#define CLK_ETHSYS_NR 9
/* G3DSYS */
#define CLK_G3DSYS_CORE 1
#define CLK_G3DSYS_NR 2
/* BDP */
#define CLK_BDP_BRG_BA 1