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Merge tag 'v4.10-rc6' into devel

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Linux 4.10-rc6

Resolved conflicts in:
	drivers/pinctrl/pinctrl-amd.c
	drivers/pinctrl/samsung/pinctrl-exynos.c
This commit is contained in:
Linus Walleij
2017-01-30 14:39:20 +01:00
parent 2b24efa8e5 566cf877a1
commit 7f36f5d11c
1081 changed files with 10685 additions and 6369 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@@ -1092,6 +1092,7 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
enum pin_config_param param = pinconf_to_config_param(*config);
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
unsigned long flags;
u32 conf, pull, val, debounce;
u16 arg = 0;
@@ -1128,7 +1129,7 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
return -EINVAL;
raw_spin_lock_irqsave(&vg->lock, flags);
debounce = readl(byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG));
debounce = readl(db_reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
@@ -1176,6 +1177,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
unsigned int param, arg;
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
unsigned long flags;
u32 conf, val, debounce;
int i, ret = 0;
@@ -1238,36 +1240,40 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
debounce = readl(byt_gpio_reg(vg, offset,
BYT_DEBOUNCE_REG));
conf &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce = readl(db_reg);
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
switch (arg) {
case 0:
conf &= BYT_DEBOUNCE_EN;
break;
case 375:
conf |= BYT_DEBOUNCE_PULSE_375US;
debounce |= BYT_DEBOUNCE_PULSE_375US;
break;
case 750:
conf |= BYT_DEBOUNCE_PULSE_750US;
debounce |= BYT_DEBOUNCE_PULSE_750US;
break;
case 1500:
conf |= BYT_DEBOUNCE_PULSE_1500US;
debounce |= BYT_DEBOUNCE_PULSE_1500US;
break;
case 3000:
conf |= BYT_DEBOUNCE_PULSE_3MS;
debounce |= BYT_DEBOUNCE_PULSE_3MS;
break;
case 6000:
conf |= BYT_DEBOUNCE_PULSE_6MS;
debounce |= BYT_DEBOUNCE_PULSE_6MS;
break;
case 12000:
conf |= BYT_DEBOUNCE_PULSE_12MS;
debounce |= BYT_DEBOUNCE_PULSE_12MS;
break;
case 24000:
conf |= BYT_DEBOUNCE_PULSE_24MS;
debounce |= BYT_DEBOUNCE_PULSE_24MS;
break;
default:
ret = -EINVAL;
}
if (!ret)
writel(debounce, db_reg);
break;
default:
ret = -ENOTSUPP;
@@ -1617,6 +1623,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
{
struct gpio_chip *gc = &vg->chip;
struct device *dev = &vg->pdev->dev;
void __iomem *reg;
u32 base, value;
int i;
@@ -1638,10 +1646,12 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
}
value = readl(reg);
if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
!(value & BYT_DIRECT_IRQ_EN)) {
if (value & BYT_DIRECT_IRQ_EN) {
clear_bit(i, gc->irq_valid_mask);
dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
byt_gpio_clear_triggering(vg, i);
dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
dev_dbg(dev, "disabling GPIO %d\n", i);
}
}
@@ -1680,6 +1690,7 @@ static int byt_gpio_probe(struct byt_gpio *vg)
gc->can_sleep = false;
gc->parent = &vg->pdev->dev;
gc->ngpio = vg->soc_data->npins;
gc->irq_need_valid_mask = true;
#ifdef CONFIG_PM_SLEEP
vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,

2
drivers/pinctrl/intel/pinctrl-broxton.c
View File

@@ -19,7 +19,7 @@
#define BXT_PAD_OWN 0x020
#define BXT_HOSTSW_OWN 0x080
#define BXT_PADCFGLOCK 0x090
#define BXT_PADCFGLOCK 0x060
#define BXT_GPI_IE 0x110
#define BXT_COMMUNITY(s, e) \

30
drivers/pinctrl/intel/pinctrl-intel.c
View File

@@ -353,6 +353,21 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
return 0;
}
static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
{
u32 value;
value = readl(padcfg0);
if (input) {
value &= ~PADCFG0_GPIORXDIS;
value |= PADCFG0_GPIOTXDIS;
} else {
value &= ~PADCFG0_GPIOTXDIS;
value |= PADCFG0_GPIORXDIS;
}
writel(value, padcfg0);
}
static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned pin)
@@ -375,11 +390,11 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
/* Disable SCI/SMI/NMI generation */
value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
/* Disable TX buffer and enable RX (this will be input) */
value &= ~PADCFG0_GPIORXDIS;
value |= PADCFG0_GPIOTXDIS;
writel(value, padcfg0);
/* Disable TX buffer and enable RX (this will be input) */
__intel_gpio_set_direction(padcfg0, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
@@ -392,18 +407,11 @@ static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
void __iomem *padcfg0;
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&pctrl->lock, flags);
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
value = readl(padcfg0);
if (input)
value |= PADCFG0_GPIOTXDIS;
else
value &= ~PADCFG0_GPIOTXDIS;
writel(value, padcfg0);
__intel_gpio_set_direction(padcfg0, input);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);