Merge tag 'armsoc-platforms' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM/arm64 SoC platform updates from Olof Johansson: "This branch contains platform updates for 32- and 64-bit ARM, including defconfig updates to enable new options, drivers and platforms. There are also a few fixes and cleanups for some existing vendors. Some of the things worth highlighting here are: - Enabling new crypt drivers on arm64 defconfig - QCOM IPQ8074 clocks and pinctrl drivers on arm64 defconfig - Debug support enabled for Renesas r8a7743 - Various config updates for Renesas platforms (sound, USB, other drivers) - Platform support (including SMP) for TI dra762 - OMAP cleanups: Move to use generic 8250 debug_ll, removal of stale DMA code" * tag 'armsoc-platforms' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (109 commits) ARM: multi_v7_defconfig: make eSDHC driver built-in arm64: defconfig: enable rockchip graphics MAINTAINERS: Update Cavium ThunderX2 entry ARM: config: aspeed: Add I2C, VUART, LPC Snoop ARM: configs: aspeed: Update Aspeed G4 with VMSPLIT_2G ARM: s3c24xx: Fix NAND ECC mode for mini2440 board ARM: davinci_all_defconfig: enable tinydrm and ST7586 arm64: defconfig: Enable QCOM IPQ8074 clock and pinctrl ARM: defconfig: tegra: Enable ChipIdea UDC driver ARM: configs: Add Tegra I2S interfaces to multi_v7_defconfig ARM: tegra: Add Tegra I2S interfaces to defconfig ARM: tegra: Update default configuration for v4.13-rc1 MAINTAINERS: update ARM/ZTE entry soc: versatile: remove unnecessary static in realview_soc_probe() ARM: Convert to using %pOF instead of full_name ARM: hisi: Fix typo in comment ARM: multi_v7_defconfig: add CONFIG_BRCMSTB_THERMAL arm64: defconfig: add CONFIG_BRCMSTB_THERMAL arm64: defconfig: add recently added crypto drivers as modules arm64: defconfig: enable CONFIG_UNIPHIER_WATCHDOG ...
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@@ -229,7 +229,7 @@ config ARCH_H1940
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config H1940BT
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tristate "Control the state of H1940 bluetooth chip"
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depends on ARCH_H1940
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select RFKILL
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depends on RFKILL
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help
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This is a simple driver that is able to control
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the state of built in bluetooth chip on h1940.
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@@ -173,7 +173,7 @@ static unsigned long s3c24xx_read_idcode_v5(void)
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return gs;
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#endif
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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#if defined(CONFIG_CPU_S3C2412)
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return __raw_readl(S3C2412_GSTATUS1);
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#else
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return 1UL; /* don't look like an 2400 */
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@@ -77,7 +77,7 @@
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#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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#if defined(CONFIG_CPU_S3C2412)
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#define S3C2412_OSCSET S3C2410_CLKREG(0x18)
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#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
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@@ -141,7 +141,7 @@
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#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
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#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
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#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
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#endif /* CONFIG_CPU_S3C2412 */
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#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28)
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@@ -287,7 +287,7 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
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.nr_sets = ARRAY_SIZE(mini2440_nand_sets),
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.sets = mini2440_nand_sets,
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.ignore_unset_ecc = 1,
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.ecc_mode = NAND_ECC_SOFT,
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.ecc_mode = NAND_ECC_HW,
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};
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/* DM9000AEP 10/100 ethernet controller */
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@@ -111,9 +111,6 @@ static struct platform_device *smdk2443_devices[] __initdata = {
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&s3c_device_wdt,
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&s3c_device_i2c0,
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&s3c_device_hsmmc1,
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#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
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&s3c_device_ac97,
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#endif
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&s3c2443_device_dma,
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};
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@@ -133,11 +130,6 @@ static void __init smdk2443_init_time(void)
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static void __init smdk2443_machine_init(void)
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{
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s3c_i2c0_set_platdata(NULL);
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#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
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s3c24xx_ac97_setup_gpio(S3C24XX_AC97_GPE0);
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#endif
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platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
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smdk_machine_init();
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}
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@@ -33,10 +33,11 @@
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
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/*
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* S3C24XX_DEBUG_RESUME is dangerous if your bootloader does not
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* reset the UART configuration, only enable if you really need this!
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*/
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//#define CONFIG_DEBUG_RESUME
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*/
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//#define S3C24XX_DEBUG_RESUME
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.text
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@@ -71,13 +72,13 @@ ENTRY(s3c_cpu_resume)
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str r12, [ r14, #0x54 ]
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#endif
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#ifdef CONFIG_DEBUG_RESUME
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#ifdef S3C24XX_DEBUG_RESUME
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mov r3, #'L'
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strb r3, [ r2, #S3C2410_UTXH ]
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1001:
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ldrb r14, [ r3, #S3C2410_UTRSTAT ]
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tst r14, #S3C2410_UTRSTAT_TXE
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beq 1001b
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#endif /* CONFIG_DEBUG_RESUME */
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#endif /* S3C24XX_DEBUG_RESUME */
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b cpu_resume
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