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Merge 2b71482060 ("Merge tag 'modules-for-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/jeyu/linux") into android-mainline

Browse Source 
Steps on the way to 5.10-rc1

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I01ffb419ee26d1c02046a0d22f960f29a3c47e7c
This commit is contained in:
Greg Kroah-Hartman
2020-10-26 11:29:12 +01:00
parent 4349cb92c3 2b71482060
commit 7ef6d19190
204 changed files with 9372 additions and 1090 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
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@@ -15,6 +15,7 @@ Required Properties:
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- "mediatek,mt7629-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8167-apmixedsys", "syscon"
- "mediatek,mt8173-apmixedsys"
- "mediatek,mt8183-apmixedsys", "syscon"
- "mediatek,mt8516-apmixedsys"

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
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@@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6779-audio", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt8167-audiosys", "syscon"
- "mediatek,mt8183-audiosys", "syscon"
- "mediatek,mt8516-audsys", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
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@@ -12,6 +12,7 @@ Required Properties:
- "mediatek,mt6779-imgsys", "syscon"
- "mediatek,mt6797-imgsys", "syscon"
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt8167-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
- "mediatek,mt8183-imgsys", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
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@@ -16,6 +16,7 @@ Required Properties:
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt7629-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8167-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- "mediatek,mt8183-infracfg", "syscon"
- "mediatek,mt8516-infracfg", "syscon"

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
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@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2712-mfgcfg", "syscon"
- "mediatek,mt6779-mfgcfg", "syscon"
- "mediatek,mt8167-mfgcfg", "syscon"
- "mediatek,mt8183-mfgcfg", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
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@@ -15,6 +15,7 @@ Required Properties:
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- "mediatek,mt7629-topckgen"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8167-topckgen", "syscon"
- "mediatek,mt8173-topckgen"
- "mediatek,mt8183-topckgen", "syscon"
- "mediatek,mt8516-topckgen"

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
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@@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6779-vdecsys", "syscon"
- "mediatek,mt6797-vdecsys", "syscon"
- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt8167-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
- "mediatek,mt8183-vdecsys", "syscon"
- #clock-cells: Must be 1

7
Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
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@@ -36,6 +36,8 @@ properties:
- allwinner,sun9i-a80-ccu
- allwinner,sun50i-a64-ccu
- allwinner,sun50i-a64-r-ccu
- allwinner,sun50i-a100-ccu
- allwinner,sun50i-a100-r-ccu
- allwinner,sun50i-h5-ccu
- allwinner,sun50i-h6-ccu
- allwinner,sun50i-h6-r-ccu
@@ -78,6 +80,7 @@ if:
- allwinner,sun8i-a83t-r-ccu
- allwinner,sun8i-h3-r-ccu
- allwinner,sun50i-a64-r-ccu
- allwinner,sun50i-a100-r-ccu
- allwinner,sun50i-h6-r-ccu
then:
@@ -94,7 +97,9 @@ else:
if:
properties:
compatible:
const: allwinner,sun50i-h6-ccu
enum:
- allwinner,sun50i-a100-ccu
- allwinner,sun50i-h6-ccu
then:
properties:

93
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml Normal file
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@@ -0,0 +1,93 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM8150 and SM8250.
See also:
dt-bindings/clock/qcom,dispcc-sm8150.h
dt-bindings/clock/qcom,dispcc-sm8250.h
properties:
compatible:
enum:
- qcom,sm8150-dispcc
- qcom,sm8250-dispcc
clocks:
items:
- description: Board XO source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
clock-names:
items:
- const: bi_tcxo
- const: dsi0_phy_pll_out_byteclk
- const: dsi0_phy_pll_out_dsiclk
- const: dsi1_phy_pll_out_byteclk
- const: dsi1_phy_pll_out_dsiclk
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@af00000 {
compatible = "qcom,sm8250-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&dp_phy 0>,
<&dp_phy 1>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

65
Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
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@@ -1,65 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7180-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller Binding for SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm video clock control module which supports the clocks, resets and
power domains on SC7180.
See also dt-bindings/clock/qcom,videocc-sc7180.h.
properties:
compatible:
const: qcom,sc7180-videocc
clocks:
items:
- description: Board XO source
clock-names:
items:
- const: bi_tcxo
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@ab00000 {
compatible = "qcom,sc7180-videocc";
reg = <0x0ab00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

18
Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml → Documentation/devicetree/bindings/clock/qcom,videocc.yaml
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@@ -1,23 +1,31 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sdm845-videocc.yaml#
$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller Binding for SDM845
title: Qualcomm Video Clock & Reset Controller Binding
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm video clock control module which supports the clocks, resets and
power domains on SDM845.
power domains on SDM845/SC7180/SM8150/SM8250.
See also dt-bindings/clock/qcom,videocc-sdm845.h.
See also:
dt-bindings/clock/qcom,videocc-sc7180.h
dt-bindings/clock/qcom,videocc-sdm845.h
dt-bindings/clock/qcom,videocc-sm8150.h
dt-bindings/clock/qcom,videocc-sm8250.h
properties:
compatible:
const: qcom,sdm845-videocc
enum:
- qcom,sc7180-videocc
- qcom,sdm845-videocc
- qcom,sm8150-videocc
- qcom,sm8250-videocc
clocks:
items:

1
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
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@@ -47,6 +47,7 @@ properties:
- renesas,r8a77980-cpg-mssr # R-Car V3H
- renesas,r8a77990-cpg-mssr # R-Car E3
- renesas,r8a77995-cpg-mssr # R-Car D3
- renesas,r8a779a0-cpg-mssr # R-Car V3U
reg:
maxItems: 1

2
Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
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@@ -13,6 +13,7 @@ properties:
compatible:
items:
- enum:
- renesas,pwm-r8a7742 # RZ/G1H
- renesas,pwm-r8a7743 # RZ/G1M
- renesas,pwm-r8a7744 # RZ/G1N
- renesas,pwm-r8a7745 # RZ/G1E
@@ -20,6 +21,7 @@ properties:
- renesas,pwm-r8a774a1 # RZ/G2M
- renesas,pwm-r8a774b1 # RZ/G2N
- renesas,pwm-r8a774c0 # RZ/G2E
- renesas,pwm-r8a774e1 # RZ/G2H
- renesas,pwm-r8a7778 # R-Car M1A
- renesas,pwm-r8a7779 # R-Car H1
- renesas,pwm-r8a7790 # R-Car H2

1
Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
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@@ -15,6 +15,7 @@ properties:
- enum:
- renesas,tpu-r8a73a4 # R-Mobile APE6
- renesas,tpu-r8a7740 # R-Mobile A1
- renesas,tpu-r8a7742 # RZ/G1H
- renesas,tpu-r8a7743 # RZ/G1M
- renesas,tpu-r8a7744 # RZ/G1N
- renesas,tpu-r8a7745 # RZ/G1E

281
Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml Normal file
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@@ -0,0 +1,281 @@
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI K3 R5F processor subsystems
maintainers:
- Suman Anna <s-anna@ti.com>
description: |
The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
processor subsystems/clusters (R5FSS). The dual core cluster can be used
either in a LockStep mode providing safety/fault tolerance features or in a
Split mode providing two individual compute cores for doubling the compute
capacity. These are used together with other processors present on the SoC
to achieve various system level goals.
Each Dual-Core R5F sub-system is represented as a single DTS node
representing the cluster, with a pair of child DT nodes representing
the individual R5F cores. Each node has a number of required or optional
properties that enable the OS running on the host processor to perform
the device management of the remote processor and to communicate with the
remote processor.
properties:
$nodename:
pattern: "^r5fss(@.*)?"
compatible:
enum:
- ti,am654-r5fss
- ti,j721e-r5fss
power-domains:
description: |
Should contain a phandle to a PM domain provider node and an args
specifier containing the R5FSS device id value.
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges:
description: |
Standard ranges definition providing address translations for
local R5F TCM address spaces to bus addresses.
# Optional properties:
# --------------------
ti,cluster-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Configuration Mode for the Dual R5F cores within the R5F cluster.
Should be either a value of 1 (LockStep mode) or 0 (Split mode),
default is LockStep mode if omitted.
# R5F Processor Child Nodes:
# ==========================
patternProperties:
"^r5f@[a-f0-9]+$":
type: object
description: |
The R5F Sub-System device node should define two R5F child nodes, each
node representing a TI instantiation of the Arm Cortex R5F core. There
are some specific integration differences for the IP like the usage of
a Region Address Translator (RAT) for translating the larger SoC bus
addresses into a 32-bit address space for the processor.
Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
internal memories split between two banks - TCMA and TCMB (further
interleaved into two banks TCMB0 and TCMB1). These memories (also called
ATCM and BTCM) provide read/write performance on par with the core's L1
caches. Each of the TCMs can be enabled or disabled independently and
either of them can be configured to appear at that R5F's address 0x0.
The cores do not use an MMU, but has a Region Address Translater
(RAT) module that is accessible only from the R5Fs for providing
translations between 32-bit CPU addresses into larger system bus
addresses. Cache and memory access settings are provided through a
Memory Protection Unit (MPU), programmable only from the R5Fs.
allOf:
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
properties:
compatible:
enum:
- ti,am654-r5f
- ti,j721e-r5f
reg:
items:
- description: Address and Size of the ATCM internal memory region
- description: Address and Size of the BTCM internal memory region
reg-names:
items:
- const: atcm
- const: btcm
resets:
description: |
Should contain the phandle to the reset controller node managing the
local resets for this device, and a reset specifier.
maxItems: 1
firmware-name:
description: |
Should contain the name of the default firmware image
file located on the firmware search path
# The following properties are mandatory for R5F Core0 in both LockStep and Split
# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
# R5F Core1 in LockStep mode:
mboxes:
description: |
OMAP Mailbox specifier denoting the sub-mailbox, to be used for
communication with the remote processor. This property should match
with the sub-mailbox node used in the firmware image.
maxItems: 1
memory-region:
description: |
phandle to the reserved memory nodes to be associated with the
remoteproc device. There should be at least two reserved memory nodes
defined. The reserved memory nodes should be carveout nodes, and
should be defined with a "no-map" property as per the bindings in
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
minItems: 2
maxItems: 8
items:
- description: region used for dynamic DMA allocations like vrings and
vring buffers
- description: region reserved for firmware image sections
additionalItems: true
# Optional properties:
# --------------------
# The following properties are optional properties for each of the R5F cores:
ti,atcm-enable:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
R5F core configuration mode dictating if ATCM should be enabled. The
R5F address of ATCM is dictated by ti,loczrama property. Should be
either a value of 1 (enabled) or 0 (disabled), default is disabled
if omitted. Recommended to enable it for maximizing TCMs.
ti,btcm-enable:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
R5F core configuration mode dictating if BTCM should be enabled. The
R5F address of BTCM is dictated by ti,loczrama property. Should be
either a value of 1 (enabled) or 0 (disabled), default is enabled if
omitted.
ti,loczrama:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
R5F core configuration mode dictating which TCM should appear at
address 0 (from core's view). Should be either a value of 1 (ATCM
at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
sram:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
description: |
phandles to one or more reserved on-chip SRAM regions. The regions
should be defined as child nodes of the respective SRAM node, and
should be defined as per the generic bindings in,
Documentation/devicetree/bindings/sram/sram.yaml
required:
- compatible
- reg
- reg-names
- ti,sci
- ti,sci-dev-id
- ti,sci-proc-ids
- resets
- firmware-name
unevaluatedProperties: false
required:
- compatible
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
/ {
model = "Texas Instruments K3 AM654 SoC";
compatible = "ti,am654-evm", "ti,am654";
#address-cells = <2>;
#size-cells = <2>;
bus@100000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
bus@28380000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
/* AM65x MCU R5FSS node */
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,am654-r5fss";
power-domains = <&k3_pds 129>;
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
mcu_r5f0: r5f@41000000 {
compatible = "ti,am654-r5f";
reg = <0x41000000 0x00008000>,
<0x41010000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <159>;
ti,sci-proc-ids = <0x01 0xFF>;
resets = <&k3_reset 159 1>;
firmware-name = "am65x-mcu-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
sram = <&mcu_r5fss0_core0_sram>;
};
mcu_r5f1: r5f@41400000 {
compatible = "ti,am654-r5f";
reg = <0x41400000 0x00008000>,
<0x41410000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <245>;
ti,sci-proc-ids = <0x02 0xFF>;
resets = <&k3_reset 245 1>;
firmware-name = "am65x-mcu-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;
};
};
};
};
};