drm/vc4: Fix races when the CS reads from render targets.
With the introduction of bin/render pipelining, the previous job may
not be completed when we start binning the next one. If the previous
job wrote our VBO, IB, or CS textures, then the binning stage might
get stale or uninitialized results.
Fixes the major rendering failure in glmark2 -b terrain.
Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: ca26d28bba
("drm/vc4: improve throughput by pipelining binning and rendering jobs")
Cc: stable@vger.kernel.org
This commit is contained in:
@@ -267,6 +267,9 @@ validate_indexed_prim_list(VALIDATE_ARGS)
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if (!ib)
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return -EINVAL;
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exec->bin_dep_seqno = max(exec->bin_dep_seqno,
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to_vc4_bo(&ib->base)->write_seqno);
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if (offset > ib->base.size ||
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(ib->base.size - offset) / index_size < length) {
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DRM_ERROR("IB access overflow (%d + %d*%d > %zd)\n",
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@@ -555,8 +558,7 @@ static bool
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reloc_tex(struct vc4_exec_info *exec,
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void *uniform_data_u,
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struct vc4_texture_sample_info *sample,
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uint32_t texture_handle_index)
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uint32_t texture_handle_index, bool is_cs)
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{
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struct drm_gem_cma_object *tex;
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uint32_t p0 = *(uint32_t *)(uniform_data_u + sample->p_offset[0]);
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@@ -714,6 +716,11 @@ reloc_tex(struct vc4_exec_info *exec,
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*validated_p0 = tex->paddr + p0;
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if (is_cs) {
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exec->bin_dep_seqno = max(exec->bin_dep_seqno,
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to_vc4_bo(&tex->base)->write_seqno);
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}
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return true;
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fail:
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DRM_INFO("Texture p0 at %d: 0x%08x\n", sample->p_offset[0], p0);
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@@ -835,7 +842,8 @@ validate_gl_shader_rec(struct drm_device *dev,
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if (!reloc_tex(exec,
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uniform_data_u,
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&validated_shader->texture_samples[tex],
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texture_handles_u[tex])) {
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texture_handles_u[tex],
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i == 2)) {
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return -EINVAL;
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}
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}
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@@ -867,6 +875,9 @@ validate_gl_shader_rec(struct drm_device *dev,
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uint32_t stride = *(uint8_t *)(pkt_u + o + 5);
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uint32_t max_index;
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exec->bin_dep_seqno = max(exec->bin_dep_seqno,
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to_vc4_bo(&vbo->base)->write_seqno);
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if (state->addr & 0x8)
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stride |= (*(uint32_t *)(pkt_u + 100 + i * 4)) & ~0xff;
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