Merge branch 'remotes/lorenzo/pci/endpoint'
- Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI endpoint framework (Wen Yang) - Add interface to discover supported endpoint features to replace a bitfield that wasn't flexible enough (Kishon Vijay Abraham I) - Implement the new supported-feature interface for designware-plat, dra7xx, rockchip, cadence (Kishon Vijay Abraham I) - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I) - Add layerscape endpoint mode support (Xiaowei Bao) * remotes/lorenzo/pci/endpoint: misc: pci_endpoint_test: Add the layerscape EP device support PCI: layerscape: Add EP mode support arm64: dts: Add the PCIE EP node in dts dt-bindings: add DT binding for the layerscape PCIe controller with EP mode PCI: endpoint: Remove features member in struct pci_epc PCI: designware-plat: Remove setting epc->features in Designware plat EP driver PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit PCI: pci-epf-test: Remove setting epf_bar flags in function driver PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags PCI: endpoint: Add helper to get first unreserved BAR PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops PCI: endpoint: Add new pci_epc_ops to get EPC features PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()
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@@ -68,14 +68,10 @@ static const struct dw_pcie_ops dw_pcie_ops = {
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static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct pci_epc *epc = ep->epc;
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enum pci_barno bar;
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for (bar = BAR_0; bar <= BAR_5; bar++)
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dw_pcie_ep_reset_bar(pci, bar);
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epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
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epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
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}
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static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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@@ -98,9 +94,22 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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return 0;
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}
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static const struct pci_epc_features dw_plat_pcie_epc_features = {
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.linkup_notifier = false,
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.msi_capable = true,
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.msix_capable = true,
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};
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static const struct pci_epc_features*
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dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
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{
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return &dw_plat_pcie_epc_features;
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}
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static struct dw_pcie_ep_ops pcie_ep_ops = {
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.ep_init = dw_plat_pcie_ep_init,
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.raise_irq = dw_plat_pcie_ep_raise_irq,
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.get_features = dw_plat_pcie_get_features,
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};
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static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
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