drivers: clk: st: Remove stih415-416 clock support
STiH415 and STiH416 platforms are no longer used. these platforms will be deprecated for the next kernel. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Gabriel Fernandez
committed by
Stephen Boyd
Stephen Boyd
parent
f5644f10dc
commit
7df404c985
@@ -19,9 +19,6 @@
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#include <linux/clk-provider.h>
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#include "clkgen.h"
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static DEFINE_SPINLOCK(clkgena_divmux_lock);
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static DEFINE_SPINLOCK(clkgenf_lock);
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static const char ** __init clkgen_mux_get_parents(struct device_node *np,
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int *num_parents)
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{
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@@ -40,498 +37,6 @@ static const char ** __init clkgen_mux_get_parents(struct device_node *np,
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return parents;
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}
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/**
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* DOC: Clock mux with a programmable divider on each of its three inputs.
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* The mux has an input setting which effectively gates its output.
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable and clk_disable are functional & control gating
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* rate - set rate is supported
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* parent - set/get parent
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*/
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#define NUM_INPUTS 3
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struct clkgena_divmux {
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struct clk_hw hw;
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/* Subclassed mux and divider structures */
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struct clk_mux mux;
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struct clk_divider div[NUM_INPUTS];
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/* Enable/running feedback register bits for each input */
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void __iomem *feedback_reg[NUM_INPUTS];
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int feedback_bit_idx;
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u8 muxsel;
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};
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#define to_clkgena_divmux(_hw) container_of(_hw, struct clkgena_divmux, hw)
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struct clkgena_divmux_data {
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int num_outputs;
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int mux_offset;
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int mux_offset2;
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int mux_start_bit;
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int div_offsets[NUM_INPUTS];
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int fb_offsets[NUM_INPUTS];
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int fb_start_bit_idx;
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};
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#define CKGAX_CLKOPSRC_SWITCH_OFF 0x3
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static int clkgena_divmux_is_running(struct clkgena_divmux *mux)
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{
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u32 regval = readl(mux->feedback_reg[mux->muxsel]);
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u32 running = regval & BIT(mux->feedback_bit_idx);
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return !!running;
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}
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static int clkgena_divmux_enable(struct clk_hw *hw)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *mux_hw = &genamux->mux.hw;
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unsigned long timeout;
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int ret = 0;
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__clk_hw_set_clk(mux_hw, hw);
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ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);
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if (ret)
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return ret;
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timeout = jiffies + msecs_to_jiffies(10);
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while (!clkgena_divmux_is_running(genamux)) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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cpu_relax();
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}
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return 0;
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}
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static void clkgena_divmux_disable(struct clk_hw *hw)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *mux_hw = &genamux->mux.hw;
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__clk_hw_set_clk(mux_hw, hw);
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clk_mux_ops.set_parent(mux_hw, CKGAX_CLKOPSRC_SWITCH_OFF);
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}
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static int clkgena_divmux_is_enabled(struct clk_hw *hw)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *mux_hw = &genamux->mux.hw;
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__clk_hw_set_clk(mux_hw, hw);
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return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
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}
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static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *mux_hw = &genamux->mux.hw;
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__clk_hw_set_clk(mux_hw, hw);
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genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
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if ((s8)genamux->muxsel < 0) {
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pr_debug("%s: %s: Invalid parent, setting to default.\n",
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__func__, clk_hw_get_name(hw));
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genamux->muxsel = 0;
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}
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return genamux->muxsel;
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}
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static int clkgena_divmux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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if (index >= CKGAX_CLKOPSRC_SWITCH_OFF)
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return -EINVAL;
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genamux->muxsel = index;
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/*
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* If the mux is already enabled, call enable directly to set the
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* new mux position and wait for it to start running again. Otherwise
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* do nothing.
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*/
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if (clkgena_divmux_is_enabled(hw))
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clkgena_divmux_enable(hw);
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return 0;
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}
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static unsigned long clkgena_divmux_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
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__clk_hw_set_clk(div_hw, hw);
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return clk_divider_ops.recalc_rate(div_hw, parent_rate);
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}
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static int clkgena_divmux_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
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__clk_hw_set_clk(div_hw, hw);
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return clk_divider_ops.set_rate(div_hw, rate, parent_rate);
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}
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static long clkgena_divmux_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
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struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
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__clk_hw_set_clk(div_hw, hw);
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return clk_divider_ops.round_rate(div_hw, rate, prate);
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}
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static const struct clk_ops clkgena_divmux_ops = {
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.enable = clkgena_divmux_enable,
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.disable = clkgena_divmux_disable,
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.is_enabled = clkgena_divmux_is_enabled,
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.get_parent = clkgena_divmux_get_parent,
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.set_parent = clkgena_divmux_set_parent,
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.round_rate = clkgena_divmux_round_rate,
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.recalc_rate = clkgena_divmux_recalc_rate,
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.set_rate = clkgena_divmux_set_rate,
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};
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/**
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* clk_register_genamux - register a genamux clock with the clock framework
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*/
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static struct clk * __init clk_register_genamux(const char *name,
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const char **parent_names, u8 num_parents,
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void __iomem *reg,
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const struct clkgena_divmux_data *muxdata,
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u32 idx)
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{
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/*
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* Fixed constants across all ClockgenA variants
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*/
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const int mux_width = 2;
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const int divider_width = 5;
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struct clkgena_divmux *genamux;
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struct clk *clk;
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struct clk_init_data init;
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int i;
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genamux = kzalloc(sizeof(*genamux), GFP_KERNEL);
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if (!genamux)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clkgena_divmux_ops;
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init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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genamux->mux.lock = &clkgena_divmux_lock;
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genamux->mux.mask = BIT(mux_width) - 1;
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genamux->mux.shift = muxdata->mux_start_bit + (idx * mux_width);
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if (genamux->mux.shift > 31) {
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/*
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* We have spilled into the second mux register so
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* adjust the register address and the bit shift accordingly
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*/
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genamux->mux.reg = reg + muxdata->mux_offset2;
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genamux->mux.shift -= 32;
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} else {
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genamux->mux.reg = reg + muxdata->mux_offset;
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}
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for (i = 0; i < NUM_INPUTS; i++) {
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/*
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* Divider config for each input
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*/
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void __iomem *divbase = reg + muxdata->div_offsets[i];
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genamux->div[i].width = divider_width;
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genamux->div[i].reg = divbase + (idx * sizeof(u32));
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/*
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* Mux enabled/running feedback register for each input.
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*/
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genamux->feedback_reg[i] = reg + muxdata->fb_offsets[i];
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}
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genamux->feedback_bit_idx = muxdata->fb_start_bit_idx + idx;
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genamux->hw.init = &init;
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clk = clk_register(NULL, &genamux->hw);
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if (IS_ERR(clk)) {
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kfree(genamux);
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goto err;
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}
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pr_debug("%s: parent %s rate %lu\n",
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__clk_get_name(clk),
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__clk_get_name(clk_get_parent(clk)),
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clk_get_rate(clk));
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err:
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return clk;
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}
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static struct clkgena_divmux_data st_divmux_c65hs = {
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.num_outputs = 4,
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.mux_offset = 0x14,
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.mux_start_bit = 0,
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.div_offsets = { 0x800, 0x900, 0xb00 },
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.fb_offsets = { 0x18, 0x1c, 0x20 },
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.fb_start_bit_idx = 0,
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};
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static struct clkgena_divmux_data st_divmux_c65ls = {
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.num_outputs = 14,
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.mux_offset = 0x14,
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.mux_offset2 = 0x24,
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.mux_start_bit = 8,
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.div_offsets = { 0x810, 0xa10, 0xb10 },
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.fb_offsets = { 0x18, 0x1c, 0x20 },
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.fb_start_bit_idx = 4,
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};
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static struct clkgena_divmux_data st_divmux_c32odf0 = {
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.num_outputs = 8,
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.mux_offset = 0x1c,
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.mux_start_bit = 0,
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.div_offsets = { 0x800, 0x900, 0xa60 },
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.fb_offsets = { 0x2c, 0x24, 0x28 },
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.fb_start_bit_idx = 0,
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};
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static struct clkgena_divmux_data st_divmux_c32odf1 = {
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.num_outputs = 8,
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.mux_offset = 0x1c,
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.mux_start_bit = 16,
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.div_offsets = { 0x820, 0x980, 0xa80 },
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.fb_offsets = { 0x2c, 0x24, 0x28 },
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.fb_start_bit_idx = 8,
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};
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static struct clkgena_divmux_data st_divmux_c32odf2 = {
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.num_outputs = 8,
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.mux_offset = 0x20,
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.mux_start_bit = 0,
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.div_offsets = { 0x840, 0xa20, 0xb10 },
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.fb_offsets = { 0x2c, 0x24, 0x28 },
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.fb_start_bit_idx = 16,
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};
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static struct clkgena_divmux_data st_divmux_c32odf3 = {
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.num_outputs = 8,
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.mux_offset = 0x20,
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.mux_start_bit = 16,
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.div_offsets = { 0x860, 0xa40, 0xb30 },
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.fb_offsets = { 0x2c, 0x24, 0x28 },
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.fb_start_bit_idx = 24,
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};
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static const struct of_device_id clkgena_divmux_of_match[] = {
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{
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.compatible = "st,clkgena-divmux-c65-hs",
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.data = &st_divmux_c65hs,
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},
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{
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.compatible = "st,clkgena-divmux-c65-ls",
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.data = &st_divmux_c65ls,
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},
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{
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.compatible = "st,clkgena-divmux-c32-odf0",
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.data = &st_divmux_c32odf0,
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},
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{
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.compatible = "st,clkgena-divmux-c32-odf1",
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.data = &st_divmux_c32odf1,
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},
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{
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.compatible = "st,clkgena-divmux-c32-odf2",
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.data = &st_divmux_c32odf2,
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},
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{
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.compatible = "st,clkgena-divmux-c32-odf3",
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.data = &st_divmux_c32odf3,
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},
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{}
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};
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static void __iomem * __init clkgen_get_register_base(struct device_node *np)
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{
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struct device_node *pnode;
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void __iomem *reg;
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pnode = of_get_parent(np);
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if (!pnode)
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return NULL;
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reg = of_iomap(pnode, 0);
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of_node_put(pnode);
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return reg;
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}
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static void __init st_of_clkgena_divmux_setup(struct device_node *np)
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{
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const struct of_device_id *match;
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const struct clkgena_divmux_data *data;
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struct clk_onecell_data *clk_data;
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void __iomem *reg;
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const char **parents;
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int num_parents = 0, i;
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match = of_match_node(clkgena_divmux_of_match, np);
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if (WARN_ON(!match))
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return;
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data = match->data;
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reg = clkgen_get_register_base(np);
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if (!reg)
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return;
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parents = clkgen_mux_get_parents(np, &num_parents);
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if (IS_ERR(parents))
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goto err_parents;
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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goto err_alloc;
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clk_data->clk_num = data->num_outputs;
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clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
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GFP_KERNEL);
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if (!clk_data->clks)
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goto err_alloc_clks;
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for (i = 0; i < clk_data->clk_num; i++) {
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struct clk *clk;
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const char *clk_name;
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if (of_property_read_string_index(np, "clock-output-names",
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i, &clk_name))
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break;
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/*
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* If we read an empty clock name then the output is unused
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*/
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if (*clk_name == '\0')
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continue;
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clk = clk_register_genamux(clk_name, parents, num_parents,
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reg, data, i);
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if (IS_ERR(clk))
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goto err;
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clk_data->clks[i] = clk;
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}
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kfree(parents);
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of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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return;
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err:
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kfree(clk_data->clks);
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err_alloc_clks:
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kfree(clk_data);
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err_alloc:
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kfree(parents);
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err_parents:
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iounmap(reg);
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}
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CLK_OF_DECLARE(clkgenadivmux, "st,clkgena-divmux", st_of_clkgena_divmux_setup);
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struct clkgena_prediv_data {
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u32 offset;
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u8 shift;
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struct clk_div_table *table;
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};
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static struct clk_div_table prediv_table16[] = {
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{ .val = 0, .div = 1 },
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{ .val = 1, .div = 16 },
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{ .div = 0 },
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};
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static struct clkgena_prediv_data prediv_c65_data = {
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.offset = 0x4c,
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.shift = 31,
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.table = prediv_table16,
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};
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static struct clkgena_prediv_data prediv_c32_data = {
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.offset = 0x50,
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.shift = 1,
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.table = prediv_table16,
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};
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static const struct of_device_id clkgena_prediv_of_match[] = {
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{ .compatible = "st,clkgena-prediv-c65", .data = &prediv_c65_data },
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{ .compatible = "st,clkgena-prediv-c32", .data = &prediv_c32_data },
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{}
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};
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static void __init st_of_clkgena_prediv_setup(struct device_node *np)
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{
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const struct of_device_id *match;
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void __iomem *reg;
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const char *parent_name, *clk_name;
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struct clk *clk;
|
||||
const struct clkgena_prediv_data *data;
|
||||
|
||||
match = of_match_node(clkgena_prediv_of_match, np);
|
||||
if (!match) {
|
||||
pr_err("%s: No matching data\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
data = match->data;
|
||||
|
||||
reg = clkgen_get_register_base(np);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
if (!parent_name)
|
||||
goto err;
|
||||
|
||||
if (of_property_read_string_index(np, "clock-output-names",
|
||||
0, &clk_name))
|
||||
goto err;
|
||||
|
||||
clk = clk_register_divider_table(NULL, clk_name, parent_name,
|
||||
CLK_GET_RATE_NOCACHE,
|
||||
reg + data->offset, data->shift, 1,
|
||||
0, data->table, NULL);
|
||||
if (IS_ERR(clk))
|
||||
goto err;
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
pr_debug("%s: parent %s rate %u\n",
|
||||
__clk_get_name(clk),
|
||||
__clk_get_name(clk_get_parent(clk)),
|
||||
(unsigned int)clk_get_rate(clk));
|
||||
|
||||
return;
|
||||
err:
|
||||
iounmap(reg);
|
||||
}
|
||||
CLK_OF_DECLARE(clkgenaprediv, "st,clkgena-prediv", st_of_clkgena_prediv_setup);
|
||||
|
||||
struct clkgen_mux_data {
|
||||
u32 offset;
|
||||
u8 shift;
|
||||
@@ -541,49 +46,6 @@ struct clkgen_mux_data {
|
||||
u8 mux_flags;
|
||||
};
|
||||
|
||||
static struct clkgen_mux_data clkgen_mux_c_vcc_hd_416 = {
|
||||
.offset = 0,
|
||||
.shift = 0,
|
||||
.width = 1,
|
||||
};
|
||||
|
||||
static struct clkgen_mux_data clkgen_mux_f_vcc_fvdp_416 = {
|
||||
.offset = 0,
|
||||
.shift = 0,
|
||||
.width = 1,
|
||||
};
|
||||
|
||||
static struct clkgen_mux_data clkgen_mux_f_vcc_hva_416 = {
|
||||
.offset = 0,
|
||||
.shift = 0,
|
||||
.width = 1,
|
||||
};
|
||||
|
||||
static struct clkgen_mux_data clkgen_mux_f_vcc_hd_416 = {
|
||||
.offset = 0,
|
||||
.shift = 16,
|
||||
.width = 1,
|
||||
.lock = &clkgenf_lock,
|
||||
};
|
||||
|
||||
static struct clkgen_mux_data clkgen_mux_c_vcc_sd_416 = {
|
||||
.offset = 0,
|
||||
.shift = 17,
|
||||
.width = 1,
|
||||
.lock = &clkgenf_lock,
|
||||
};
|
||||
|
||||
static struct clkgen_mux_data stih415_a9_mux_data = {
|
||||
.offset = 0,
|
||||
.shift = 1,
|
||||
.width = 2,
|
||||
.lock = &clkgen_a9_lock,
|
||||
};
|
||||
static struct clkgen_mux_data stih416_a9_mux_data = {
|
||||
.offset = 0,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
};
|
||||
static struct clkgen_mux_data stih407_a9_mux_data = {
|
||||
.offset = 0x1a4,
|
||||
.shift = 0,
|
||||
@@ -592,48 +54,19 @@ static struct clkgen_mux_data stih407_a9_mux_data = {
|
||||
};
|
||||
|
||||
static const struct of_device_id mux_of_match[] = {
|
||||
{
|
||||
.compatible = "st,stih416-clkgenc-vcc-hd",
|
||||
.data = &clkgen_mux_c_vcc_hd_416,
|
||||
},
|
||||
{
|
||||
.compatible = "st,stih416-clkgenf-vcc-fvdp",
|
||||
.data = &clkgen_mux_f_vcc_fvdp_416,
|
||||
},
|
||||
{
|
||||
.compatible = "st,stih416-clkgenf-vcc-hva",
|
||||
.data = &clkgen_mux_f_vcc_hva_416,
|
||||
},
|
||||
{
|
||||
.compatible = "st,stih416-clkgenf-vcc-hd",
|
||||
.data = &clkgen_mux_f_vcc_hd_416,
|
||||
},
|
||||
{
|
||||
.compatible = "st,stih416-clkgenf-vcc-sd",
|
||||
.data = &clkgen_mux_c_vcc_sd_416,
|
||||
},
|
||||
{
|
||||
.compatible = "st,stih415-clkgen-a9-mux",
|
||||
.data = &stih415_a9_mux_data,
|
||||
},
|
||||
{
|
||||
.compatible = "st,stih416-clkgen-a9-mux",
|
||||
.data = &stih416_a9_mux_data,
|
||||
},
|
||||
{
|
||||
.compatible = "st,stih407-clkgen-a9-mux",
|
||||
.data = &stih407_a9_mux_data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init st_of_clkgen_mux_setup(struct device_node *np)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct clk *clk;
|
||||
void __iomem *reg;
|
||||
const char **parents;
|
||||
int num_parents;
|
||||
int num_parents = 0;
|
||||
const struct clkgen_mux_data *data;
|
||||
|
||||
match = of_match_node(mux_of_match, np);
|
||||
@@ -680,160 +113,3 @@ err_parents:
|
||||
iounmap(reg);
|
||||
}
|
||||
CLK_OF_DECLARE(clkgen_mux, "st,clkgen-mux", st_of_clkgen_mux_setup);
|
||||
|
||||
#define VCC_MAX_CHANNELS 16
|
||||
|
||||
#define VCC_GATE_OFFSET 0x0
|
||||
#define VCC_MUX_OFFSET 0x4
|
||||
#define VCC_DIV_OFFSET 0x8
|
||||
|
||||
struct clkgen_vcc_data {
|
||||
spinlock_t *lock;
|
||||
unsigned long clk_flags;
|
||||
};
|
||||
|
||||
static struct clkgen_vcc_data st_clkgenc_vcc_416 = {
|
||||
.clk_flags = CLK_SET_RATE_PARENT,
|
||||
};
|
||||
|
||||
static struct clkgen_vcc_data st_clkgenf_vcc_416 = {
|
||||
.lock = &clkgenf_lock,
|
||||
};
|
||||
|
||||
static const struct of_device_id vcc_of_match[] = {
|
||||
{ .compatible = "st,stih416-clkgenc", .data = &st_clkgenc_vcc_416 },
|
||||
{ .compatible = "st,stih416-clkgenf", .data = &st_clkgenf_vcc_416 },
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init st_of_clkgen_vcc_setup(struct device_node *np)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
void __iomem *reg;
|
||||
const char **parents;
|
||||
int num_parents, i;
|
||||
struct clk_onecell_data *clk_data;
|
||||
const struct clkgen_vcc_data *data;
|
||||
|
||||
match = of_match_node(vcc_of_match, np);
|
||||
if (WARN_ON(!match))
|
||||
return;
|
||||
data = match->data;
|
||||
|
||||
reg = of_iomap(np, 0);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
parents = clkgen_mux_get_parents(np, &num_parents);
|
||||
if (IS_ERR(parents))
|
||||
goto err_parents;
|
||||
|
||||
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
goto err_alloc;
|
||||
|
||||
clk_data->clk_num = VCC_MAX_CHANNELS;
|
||||
clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
|
||||
GFP_KERNEL);
|
||||
|
||||
if (!clk_data->clks)
|
||||
goto err_alloc_clks;
|
||||
|
||||
for (i = 0; i < clk_data->clk_num; i++) {
|
||||
struct clk *clk;
|
||||
const char *clk_name;
|
||||
struct clk_gate *gate;
|
||||
struct clk_divider *div;
|
||||
struct clk_mux *mux;
|
||||
|
||||
if (of_property_read_string_index(np, "clock-output-names",
|
||||
i, &clk_name))
|
||||
break;
|
||||
|
||||
/*
|
||||
* If we read an empty clock name then the output is unused
|
||||
*/
|
||||
if (*clk_name == '\0')
|
||||
continue;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
goto err;
|
||||
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div) {
|
||||
kfree(gate);
|
||||
goto err;
|
||||
}
|
||||
|
||||
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
||||
if (!mux) {
|
||||
kfree(gate);
|
||||
kfree(div);
|
||||
goto err;
|
||||
}
|
||||
|
||||
gate->reg = reg + VCC_GATE_OFFSET;
|
||||
gate->bit_idx = i;
|
||||
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
||||
gate->lock = data->lock;
|
||||
|
||||
div->reg = reg + VCC_DIV_OFFSET;
|
||||
div->shift = 2 * i;
|
||||
div->width = 2;
|
||||
div->flags = CLK_DIVIDER_POWER_OF_TWO |
|
||||
CLK_DIVIDER_ROUND_CLOSEST;
|
||||
|
||||
mux->reg = reg + VCC_MUX_OFFSET;
|
||||
mux->shift = 2 * i;
|
||||
mux->mask = 0x3;
|
||||
|
||||
clk = clk_register_composite(NULL, clk_name, parents,
|
||||
num_parents,
|
||||
&mux->hw, &clk_mux_ops,
|
||||
&div->hw, &clk_divider_ops,
|
||||
&gate->hw, &clk_gate_ops,
|
||||
data->clk_flags |
|
||||
CLK_GET_RATE_NOCACHE);
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(gate);
|
||||
kfree(div);
|
||||
kfree(mux);
|
||||
goto err;
|
||||
}
|
||||
|
||||
pr_debug("%s: parent %s rate %u\n",
|
||||
__clk_get_name(clk),
|
||||
__clk_get_name(clk_get_parent(clk)),
|
||||
(unsigned int)clk_get_rate(clk));
|
||||
|
||||
clk_data->clks[i] = clk;
|
||||
}
|
||||
|
||||
kfree(parents);
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
|
||||
return;
|
||||
|
||||
err:
|
||||
for (i = 0; i < clk_data->clk_num; i++) {
|
||||
struct clk_composite *composite;
|
||||
|
||||
if (!clk_data->clks[i])
|
||||
continue;
|
||||
|
||||
composite = to_clk_composite(__clk_get_hw(clk_data->clks[i]));
|
||||
kfree(to_clk_gate(composite->gate_hw));
|
||||
kfree(to_clk_divider(composite->rate_hw));
|
||||
kfree(to_clk_mux(composite->mux_hw));
|
||||
}
|
||||
|
||||
kfree(clk_data->clks);
|
||||
err_alloc_clks:
|
||||
kfree(clk_data);
|
||||
err_alloc:
|
||||
kfree(parents);
|
||||
err_parents:
|
||||
iounmap(reg);
|
||||
}
|
||||
CLK_OF_DECLARE(clkgen_vcc, "st,clkgen-vcc", st_of_clkgen_vcc_setup);
|
||||
|
||||
Reference in New Issue
Block a user