Merge git://www.linux-watchdog.org/linux-watchdog

Pull watchdog updates from Wim Van Sebroeck:
 "This contains following changes:

   - Octeon: convert to watchdog-API and apply some fixes
   - Cadence wdt: remove dependency on ARCH
   - add DT bindings for qcom + msm
   - bcm281xx: Remove use of seq_printf return value
   - stmp3xxx_rtc_wdt + pnx4008_wdt: fix broken email addresses"

* git://www.linux-watchdog.org/linux-watchdog:
  watchdog: stmp3xxx_rtc_wdt: fix broken email address
  watchdog: pnx4008_wdt: fix broken email address
  watchdog: octeon: use fixed length string for register names
  watchdog: octeon: fix some trivial coding style issues
  watchdog: octeon: convert to WATCHDOG_CORE API
  watchdog: cadence: Remove Kconfig dependency on ARCH
  ARM: msm: add watchdog entries to DT timer binding doc
  ARM: qcom: add description of KPSS WDT for IPQ8064
  watchdog: qcom: use timer devicetree binding
  watchdog: bcm281xx: Remove use of seq_printf return value

Documentation/devicetree/bindings/arm/msm/timer.txt

@@ -9,11 +9,17 @@ Properties:
                "qcom,scss-timer" - scorpion subsystem
 
 - interrupts : Interrupts for the debug timer, the first general purpose
-               timer, and optionally a second general purpose timer in that
-               order.
+               timer, and optionally a second general purpose timer, and
+               optionally as well, 2 watchdog interrupts, in that order.
 
 - reg : Specifies the base address of the timer registers.
 
+- clocks: Reference to the parent clocks, one per output clock. The parents
+          must appear in the same order as the clock names.
+
+- clock-names: The name of the clocks as free-form strings. They should be in
+               the same order as the clocks.
+
 - clock-frequency : The frequency of the debug timer and the general purpose
                     timer(s) in Hz in that order.
 
@@ -29,9 +35,13 @@ Example:
                compatible = "qcom,scss-timer", "qcom,msm-timer";
                interrupts = <1 1 0x301>,
                             <1 2 0x301>,
-                            <1 3 0x301>;
+                            <1 3 0x301>,
+                            <1 4 0x301>,
+                            <1 5 0x301>;
                reg = <0x0200a000 0x100>;
                clock-frequency = <19200000>,
                                  <32768>;
+               clocks = <&sleep_clk>;
+               clock-names = "sleep";
                cpu-offset = <0x40000>;
        };