Merge branch 'pci/aw-reset-v5' into next
* pci/aw-reset-v5: PCI: Add pci_probe_reset_slot() and pci_probe_reset_bus() PCI: Remove aer_do_secondary_bus_reset() PCI: Tune secondary bus reset timing PCI: Wake-up devices before saving config space for reset PCI: Add pci_reset_slot() and pci_reset_bus() PCI: Split out pci_dev lock/unlock and save/restore PCI: Add slot reset option to pci_dev_reset() PCI: pciehp: Add reset_slot() method PCI: Add hotplug_slot_ops.reset_slot() PCI: Add pci_reset_bridge_secondary_bus()
This commit is contained in:
Bjorn Helgaas
@@ -22,6 +22,7 @@
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/pm_runtime.h>
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#include <linux/pci_hotplug.h>
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#include <asm-generic/pci-bridge.h>
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#include <asm/setup.h>
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#include "pci.h"
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@@ -3288,9 +3289,42 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
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return 0;
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}
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static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
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/**
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* pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
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* @dev: Bridge device
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*
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* Use the bridge control register to assert reset on the secondary bus.
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* Devices on the secondary bus are left in power-on state.
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*/
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void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
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{
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u16 ctrl;
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
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ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
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/*
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* PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
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* this to 2ms to ensure that we meet the minium requirement.
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*/
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msleep(2);
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ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
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/*
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* Trhfa for conventional PCI is 2^25 clock cycles.
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* Assuming a minimum 33MHz clock this results in a 1s
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* delay before we can consider subordinate devices to
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* be re-initialized. PCIe has some ways to shorten this,
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* but we don't make use of them yet.
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*/
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ssleep(1);
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}
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EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
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static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
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{
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struct pci_dev *pdev;
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if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
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@@ -3303,18 +3337,40 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
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if (probe)
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return 0;
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pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
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ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
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msleep(100);
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ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
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msleep(100);
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pci_reset_bridge_secondary_bus(dev->bus->self);
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return 0;
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}
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static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
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{
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int rc = -ENOTTY;
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if (!hotplug || !try_module_get(hotplug->ops->owner))
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return rc;
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if (hotplug->ops->reset_slot)
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rc = hotplug->ops->reset_slot(hotplug, probe);
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module_put(hotplug->ops->owner);
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return rc;
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}
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static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
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{
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struct pci_dev *pdev;
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if (dev->subordinate || !dev->slot)
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return -ENOTTY;
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list_for_each_entry(pdev, &dev->bus->devices, bus_list)
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if (pdev != dev && pdev->slot == dev->slot)
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return -ENOTTY;
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return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
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}
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static int __pci_dev_reset(struct pci_dev *dev, int probe)
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{
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int rc;
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@@ -3337,27 +3393,65 @@ static int __pci_dev_reset(struct pci_dev *dev, int probe)
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if (rc != -ENOTTY)
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goto done;
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rc = pci_dev_reset_slot_function(dev, probe);
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if (rc != -ENOTTY)
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goto done;
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rc = pci_parent_bus_reset(dev, probe);
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done:
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return rc;
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}
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static void pci_dev_lock(struct pci_dev *dev)
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{
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pci_cfg_access_lock(dev);
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/* block PM suspend, driver probe, etc. */
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device_lock(&dev->dev);
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}
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static void pci_dev_unlock(struct pci_dev *dev)
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{
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device_unlock(&dev->dev);
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pci_cfg_access_unlock(dev);
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}
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static void pci_dev_save_and_disable(struct pci_dev *dev)
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{
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/*
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* Wake-up device prior to save. PM registers default to D0 after
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* reset and a simple register restore doesn't reliably return
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* to a non-D0 state anyway.
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*/
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pci_set_power_state(dev, PCI_D0);
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pci_save_state(dev);
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/*
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* Disable the device by clearing the Command register, except for
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* INTx-disable which is set. This not only disables MMIO and I/O port
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* BARs, but also prevents the device from being Bus Master, preventing
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* DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
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* compliant devices, INTx-disable prevents legacy interrupts.
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*/
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pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
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}
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static void pci_dev_restore(struct pci_dev *dev)
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{
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pci_restore_state(dev);
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}
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static int pci_dev_reset(struct pci_dev *dev, int probe)
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{
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int rc;
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if (!probe) {
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pci_cfg_access_lock(dev);
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/* block PM suspend, driver probe, etc. */
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device_lock(&dev->dev);
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}
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if (!probe)
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pci_dev_lock(dev);
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rc = __pci_dev_reset(dev, probe);
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if (!probe) {
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device_unlock(&dev->dev);
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pci_cfg_access_unlock(dev);
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}
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if (!probe)
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pci_dev_unlock(dev);
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return rc;
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}
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/**
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@@ -3448,22 +3542,249 @@ int pci_reset_function(struct pci_dev *dev)
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if (rc)
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return rc;
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pci_save_state(dev);
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/*
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* both INTx and MSI are disabled after the Interrupt Disable bit
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* is set and the Bus Master bit is cleared.
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*/
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pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
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pci_dev_save_and_disable(dev);
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rc = pci_dev_reset(dev, 0);
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pci_restore_state(dev);
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pci_dev_restore(dev);
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return rc;
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}
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EXPORT_SYMBOL_GPL(pci_reset_function);
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/* Lock devices from the top of the tree down */
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static void pci_bus_lock(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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pci_dev_lock(dev);
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if (dev->subordinate)
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pci_bus_lock(dev->subordinate);
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}
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}
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/* Unlock devices from the bottom of the tree up */
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static void pci_bus_unlock(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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if (dev->subordinate)
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pci_bus_unlock(dev->subordinate);
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pci_dev_unlock(dev);
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}
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}
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/* Lock devices from the top of the tree down */
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static void pci_slot_lock(struct pci_slot *slot)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &slot->bus->devices, bus_list) {
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if (!dev->slot || dev->slot != slot)
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continue;
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pci_dev_lock(dev);
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if (dev->subordinate)
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pci_bus_lock(dev->subordinate);
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}
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}
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/* Unlock devices from the bottom of the tree up */
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static void pci_slot_unlock(struct pci_slot *slot)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &slot->bus->devices, bus_list) {
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if (!dev->slot || dev->slot != slot)
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continue;
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if (dev->subordinate)
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pci_bus_unlock(dev->subordinate);
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pci_dev_unlock(dev);
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}
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}
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/* Save and disable devices from the top of the tree down */
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static void pci_bus_save_and_disable(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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pci_dev_save_and_disable(dev);
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if (dev->subordinate)
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pci_bus_save_and_disable(dev->subordinate);
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}
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}
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/*
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* Restore devices from top of the tree down - parent bridges need to be
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* restored before we can get to subordinate devices.
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*/
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static void pci_bus_restore(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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pci_dev_restore(dev);
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if (dev->subordinate)
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pci_bus_restore(dev->subordinate);
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}
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}
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/* Save and disable devices from the top of the tree down */
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static void pci_slot_save_and_disable(struct pci_slot *slot)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &slot->bus->devices, bus_list) {
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if (!dev->slot || dev->slot != slot)
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continue;
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pci_dev_save_and_disable(dev);
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if (dev->subordinate)
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pci_bus_save_and_disable(dev->subordinate);
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}
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}
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/*
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* Restore devices from top of the tree down - parent bridges need to be
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* restored before we can get to subordinate devices.
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*/
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static void pci_slot_restore(struct pci_slot *slot)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &slot->bus->devices, bus_list) {
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if (!dev->slot || dev->slot != slot)
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continue;
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pci_dev_restore(dev);
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if (dev->subordinate)
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pci_bus_restore(dev->subordinate);
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}
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}
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static int pci_slot_reset(struct pci_slot *slot, int probe)
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{
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int rc;
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if (!slot)
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return -ENOTTY;
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if (!probe)
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pci_slot_lock(slot);
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might_sleep();
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rc = pci_reset_hotplug_slot(slot->hotplug, probe);
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if (!probe)
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pci_slot_unlock(slot);
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return rc;
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}
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/**
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* pci_probe_reset_slot - probe whether a PCI slot can be reset
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* @slot: PCI slot to probe
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*
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* Return 0 if slot can be reset, negative if a slot reset is not supported.
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*/
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int pci_probe_reset_slot(struct pci_slot *slot)
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{
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return pci_slot_reset(slot, 1);
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}
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EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
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/**
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* pci_reset_slot - reset a PCI slot
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* @slot: PCI slot to reset
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*
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* A PCI bus may host multiple slots, each slot may support a reset mechanism
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* independent of other slots. For instance, some slots may support slot power
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* control. In the case of a 1:1 bus to slot architecture, this function may
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* wrap the bus reset to avoid spurious slot related events such as hotplug.
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* Generally a slot reset should be attempted before a bus reset. All of the
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* function of the slot and any subordinate buses behind the slot are reset
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* through this function. PCI config space of all devices in the slot and
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* behind the slot is saved before and restored after reset.
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*
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* Return 0 on success, non-zero on error.
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*/
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int pci_reset_slot(struct pci_slot *slot)
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{
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int rc;
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rc = pci_slot_reset(slot, 1);
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if (rc)
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return rc;
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pci_slot_save_and_disable(slot);
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rc = pci_slot_reset(slot, 0);
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pci_slot_restore(slot);
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return rc;
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}
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EXPORT_SYMBOL_GPL(pci_reset_slot);
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static int pci_bus_reset(struct pci_bus *bus, int probe)
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{
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if (!bus->self)
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return -ENOTTY;
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if (probe)
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return 0;
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pci_bus_lock(bus);
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might_sleep();
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pci_reset_bridge_secondary_bus(bus->self);
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pci_bus_unlock(bus);
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return 0;
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}
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/**
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* pci_probe_reset_bus - probe whether a PCI bus can be reset
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* @bus: PCI bus to probe
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*
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* Return 0 if bus can be reset, negative if a bus reset is not supported.
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*/
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int pci_probe_reset_bus(struct pci_bus *bus)
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{
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return pci_bus_reset(bus, 1);
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}
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EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
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/**
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* pci_reset_bus - reset a PCI bus
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* @bus: top level PCI bus to reset
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*
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* Do a bus reset on the given bus and any subordinate buses, saving
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* and restoring state of all devices.
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*
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* Return 0 on success, non-zero on error.
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*/
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int pci_reset_bus(struct pci_bus *bus)
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{
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int rc;
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rc = pci_bus_reset(bus, 1);
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if (rc)
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return rc;
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pci_bus_save_and_disable(bus);
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rc = pci_bus_reset(bus, 0);
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pci_bus_restore(bus);
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return rc;
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}
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EXPORT_SYMBOL_GPL(pci_reset_bus);
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/**
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* pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
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* @dev: PCI device to query
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Reference in New Issue
Block a user