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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

Browse Source 
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (127 commits)
  sh: update defconfigs.
  sh: Fix up the NUMA build for recent LMB changes.
  sh64: provide a stub per_cpu_trap_init() definition.
  sh: fix up CONFIG_KEXEC=n build.
  sh: fixup the docbook paths for clock framework shuffling.
  driver core: Early dev_name() depends on slab_is_available().
  sh: simplify WARN usage in SH clock driver
  sh: Check return value of clk_get on ms7724
  sh: Check return value of clk_get on ecovec24
  sh: move sh clock-cpg.c contents to drivers/sh/clk-cpg.c
  sh: move sh clock.c contents to drivers/sh/clk.
  sh: move sh asm/clock.h contents to linux/sh_clk.h V2
  sh: remove unused clock lookup
  sh: switch boards to clkdev
  sh: switch sh4-202 to clkdev
  sh: switch shx3 to clkdev
  sh: switch sh7757 to clkdev
  sh: switch sh7763 to clkdev
  sh: switch sh7780 to clkdev
  sh: switch sh7786 to clkdev
  ...
This commit is contained in:
Linus Torvalds
2010-05-19 11:36:03 -07:00
parent ba0234ec35 4d0956b8f5
commit 7c7cbaf5b8
172 changed files with 6097 additions and 3733 deletions
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2
arch/sh/kernel/Makefile
View File

@@ -11,7 +11,7 @@ endif
CFLAGS_REMOVE_return_address.o = -pg
obj-y := debugtraps.o dma-nommu.o dumpstack.o \
obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \
idle.o io.o io_generic.o irq.o \
irq_$(BITS).o machvec.o nmi_debug.o process.o \
process_$(BITS).o ptrace_$(BITS).o \

169
arch/sh/kernel/clkdev.c Normal file
View File

@@ -0,0 +1,169 @@
/*
* arch/sh/kernel/clkdev.c
*
* Cloned from arch/arm/common/clkdev.c:
*
* Copyright (C) 2008 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Helper for the clk API to assist looking up a struct clk.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/mutex.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/bootmem.h>
#include <linux/mm.h>
#include <asm/clock.h>
#include <asm/clkdev.h>
static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex);
/*
* Find the correct struct clk for the device and connection ID.
* We do slightly fuzzy matching here:
* An entry with a NULL ID is assumed to be a wildcard.
* If an entry has a device ID, it must match
* If an entry has a connection ID, it must match
* Then we take the most specific entry - with the following
* order of precidence: dev+con > dev only > con only.
*/
static struct clk *clk_find(const char *dev_id, const char *con_id)
{
struct clk_lookup *p;
struct clk *clk = NULL;
int match, best = 0;
list_for_each_entry(p, &clocks, node) {
match = 0;
if (p->dev_id) {
if (!dev_id || strcmp(p->dev_id, dev_id))
continue;
match += 2;
}
if (p->con_id) {
if (!con_id || strcmp(p->con_id, con_id))
continue;
match += 1;
}
if (match == 0)
continue;
if (match > best) {
clk = p->clk;
best = match;
}
}
return clk;
}
struct clk *clk_get_sys(const char *dev_id, const char *con_id)
{
struct clk *clk;
mutex_lock(&clocks_mutex);
clk = clk_find(dev_id, con_id);
mutex_unlock(&clocks_mutex);
return clk ? clk : ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get_sys);
void clkdev_add(struct clk_lookup *cl)
{
mutex_lock(&clocks_mutex);
list_add_tail(&cl->node, &clocks);
mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL(clkdev_add);
void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
{
mutex_lock(&clocks_mutex);
while (num--) {
list_add_tail(&cl->node, &clocks);
cl++;
}
mutex_unlock(&clocks_mutex);
}
#define MAX_DEV_ID 20
#define MAX_CON_ID 16
struct clk_lookup_alloc {
struct clk_lookup cl;
char dev_id[MAX_DEV_ID];
char con_id[MAX_CON_ID];
};
struct clk_lookup * __init_refok
clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
{
struct clk_lookup_alloc *cla;
if (!slab_is_available())
cla = alloc_bootmem_low_pages(sizeof(*cla));
else
cla = kzalloc(sizeof(*cla), GFP_KERNEL);
if (!cla)
return NULL;
cla->cl.clk = clk;
if (con_id) {
strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
cla->cl.con_id = cla->con_id;
}
if (dev_fmt) {
va_list ap;
va_start(ap, dev_fmt);
vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
cla->cl.dev_id = cla->dev_id;
va_end(ap);
}
return &cla->cl;
}
EXPORT_SYMBOL(clkdev_alloc);
int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
struct device *dev)
{
struct clk *r = clk_get(dev, id);
struct clk_lookup *l;
if (IS_ERR(r))
return PTR_ERR(r);
l = clkdev_alloc(r, alias, alias_dev_name);
clk_put(r);
if (!l)
return -ENODEV;
clkdev_add(l);
return 0;
}
EXPORT_SYMBOL(clk_add_alias);
/*
* clkdev_drop - remove a clock dynamically allocated
*/
void clkdev_drop(struct clk_lookup *cl)
{
mutex_lock(&clocks_mutex);
list_del(&cl->node);
mutex_unlock(&clocks_mutex);
kfree(cl);
}
EXPORT_SYMBOL(clkdev_drop);

2
arch/sh/kernel/cpu/Makefile
View File

@@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
# Common interfaces.
obj-$(CONFIG_SH_ADC) += adc.o
obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o
obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
obj-$(CONFIG_SH_FPU) += fpu.o
obj-$(CONFIG_SH_FPU_EMU) += fpu.o

312
arch/sh/kernel/cpu/clock-cpg.c
View File

@@ -2,317 +2,25 @@
#include <linux/compiler.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
static int sh_clk_mstp32_enable(struct clk *clk)
{
__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
clk->enable_reg);
return 0;
}
static void sh_clk_mstp32_disable(struct clk *clk)
{
__raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
clk->enable_reg);
}
static struct clk_ops sh_clk_mstp32_clk_ops = {
.enable = sh_clk_mstp32_enable,
.disable = sh_clk_mstp32_disable,
.recalc = followparent_recalc,
};
int __init sh_clk_mstp32_register(struct clk *clks, int nr)
{
struct clk *clkp;
int ret = 0;
int k;
for (k = 0; !ret && (k < nr); k++) {
clkp = clks + k;
clkp->ops = &sh_clk_mstp32_clk_ops;
ret |= clk_register(clkp);
}
return ret;
}
static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
{
return clk_rate_table_round(clk, clk->freq_table, rate);
}
static int sh_clk_div6_divisors[64] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
};
static struct clk_div_mult_table sh_clk_div6_table = {
.divisors = sh_clk_div6_divisors,
.nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
};
static unsigned long sh_clk_div6_recalc(struct clk *clk)
{
struct clk_div_mult_table *table = &sh_clk_div6_table;
unsigned int idx;
clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
table, NULL);
idx = __raw_readl(clk->enable_reg) & 0x003f;
return clk->freq_table[idx].frequency;
}
static int sh_clk_div6_set_rate(struct clk *clk,
unsigned long rate, int algo_id)
{
unsigned long value;
int idx;
idx = clk_rate_table_find(clk, clk->freq_table, rate);
if (idx < 0)
return idx;
value = __raw_readl(clk->enable_reg);
value &= ~0x3f;
value |= idx;
__raw_writel(value, clk->enable_reg);
return 0;
}
static int sh_clk_div6_enable(struct clk *clk)
{
unsigned long value;
int ret;
ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
if (ret == 0) {
value = __raw_readl(clk->enable_reg);
value &= ~0x100; /* clear stop bit to enable clock */
__raw_writel(value, clk->enable_reg);
}
return ret;
}
static void sh_clk_div6_disable(struct clk *clk)
{
unsigned long value;
value = __raw_readl(clk->enable_reg);
value |= 0x100; /* stop clock */
value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
__raw_writel(value, clk->enable_reg);
}
static struct clk_ops sh_clk_div6_clk_ops = {
.recalc = sh_clk_div6_recalc,
.round_rate = sh_clk_div_round_rate,
.set_rate = sh_clk_div6_set_rate,
.enable = sh_clk_div6_enable,
.disable = sh_clk_div6_disable,
};
int __init sh_clk_div6_register(struct clk *clks, int nr)
{
struct clk *clkp;
void *freq_table;
int nr_divs = sh_clk_div6_table.nr_divisors;
int freq_table_size = sizeof(struct cpufreq_frequency_table);
int ret = 0;
int k;
freq_table_size *= (nr_divs + 1);
freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
if (!freq_table) {
pr_err("sh_clk_div6_register: unable to alloc memory\n");
return -ENOMEM;
}
for (k = 0; !ret && (k < nr); k++) {
clkp = clks + k;
clkp->ops = &sh_clk_div6_clk_ops;
clkp->id = -1;
clkp->freq_table = freq_table + (k * freq_table_size);
clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
ret = clk_register(clkp);
}
return ret;
}
static unsigned long sh_clk_div4_recalc(struct clk *clk)
{
struct clk_div4_table *d4t = clk->priv;
struct clk_div_mult_table *table = d4t->div_mult_table;
unsigned int idx;
clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
table, &clk->arch_flags);
idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
return clk->freq_table[idx].frequency;
}
static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
{
struct clk_div4_table *d4t = clk->priv;
struct clk_div_mult_table *table = d4t->div_mult_table;
u32 value;
int ret;
if (!strcmp("pll_clk", parent->name))
value = __raw_readl(clk->enable_reg) & ~(1 << 7);
else
value = __raw_readl(clk->enable_reg) | (1 << 7);
ret = clk_reparent(clk, parent);
if (ret < 0)
return ret;
__raw_writel(value, clk->enable_reg);
/* Rebiuld the frequency table */
clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
table, &clk->arch_flags);
return 0;
}
static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
{
struct clk_div4_table *d4t = clk->priv;
unsigned long value;
int idx = clk_rate_table_find(clk, clk->freq_table, rate);
if (idx < 0)
return idx;
value = __raw_readl(clk->enable_reg);
value &= ~(0xf << clk->enable_bit);
value |= (idx << clk->enable_bit);
__raw_writel(value, clk->enable_reg);
if (d4t->kick)
d4t->kick(clk);
return 0;
}
static int sh_clk_div4_enable(struct clk *clk)
{
__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
return 0;
}
static void sh_clk_div4_disable(struct clk *clk)
{
__raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
}
static struct clk_ops sh_clk_div4_clk_ops = {
.recalc = sh_clk_div4_recalc,
.set_rate = sh_clk_div4_set_rate,
.round_rate = sh_clk_div_round_rate,
};
static struct clk_ops sh_clk_div4_enable_clk_ops = {
.recalc = sh_clk_div4_recalc,
.set_rate = sh_clk_div4_set_rate,
.round_rate = sh_clk_div_round_rate,
.enable = sh_clk_div4_enable,
.disable = sh_clk_div4_disable,
};
static struct clk_ops sh_clk_div4_reparent_clk_ops = {
.recalc = sh_clk_div4_recalc,
.set_rate = sh_clk_div4_set_rate,
.round_rate = sh_clk_div_round_rate,
.enable = sh_clk_div4_enable,
.disable = sh_clk_div4_disable,
.set_parent = sh_clk_div4_set_parent,
};
static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
struct clk_div4_table *table, struct clk_ops *ops)
{
struct clk *clkp;
void *freq_table;
int nr_divs = table->div_mult_table->nr_divisors;
int freq_table_size = sizeof(struct cpufreq_frequency_table);
int ret = 0;
int k;
freq_table_size *= (nr_divs + 1);
freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
if (!freq_table) {
pr_err("sh_clk_div4_register: unable to alloc memory\n");
return -ENOMEM;
}
for (k = 0; !ret && (k < nr); k++) {
clkp = clks + k;
clkp->ops = ops;
clkp->id = -1;
clkp->priv = table;
clkp->freq_table = freq_table + (k * freq_table_size);
clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
ret = clk_register(clkp);
}
return ret;
}
int __init sh_clk_div4_register(struct clk *clks, int nr,
struct clk_div4_table *table)
{
return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
}
int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
struct clk_div4_table *table)
{
return sh_clk_div4_register_ops(clks, nr, table,
&sh_clk_div4_enable_clk_ops);
}
int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
struct clk_div4_table *table)
{
return sh_clk_div4_register_ops(clks, nr, table,
&sh_clk_div4_reparent_clk_ops);
}
#ifdef CONFIG_SH_CLK_CPG_LEGACY
static struct clk master_clk = {
.name = "master_clk",
.flags = CLK_ENABLE_ON_INIT,
.rate = CONFIG_SH_PCLK_FREQ,
};
static struct clk peripheral_clk = {
.name = "peripheral_clk",
.parent = &master_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static struct clk bus_clk = {
.name = "bus_clk",
.parent = &master_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static struct clk cpu_clk = {
.name = "cpu_clk",
.parent = &master_clk,
.flags = CLK_ENABLE_ON_INIT,
};
@@ -327,6 +35,16 @@ static struct clk *onchip_clocks[] = {
&cpu_clk,
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("master_clk", &master_clk),
CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
CLKDEV_CON_ID("bus_clk", &bus_clk),
CLKDEV_CON_ID("cpu_clk", &cpu_clk),
};
int __init __deprecated cpg_clk_init(void)
{
int i, ret = 0;
@@ -338,6 +56,13 @@ int __init __deprecated cpg_clk_init(void)
ret |= clk_register(clk);
}
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
return ret;
}
@@ -349,4 +74,3 @@ int __init __weak arch_clk_init(void)
{
return cpg_clk_init();
}
#endif /* CONFIG_SH_CPG_CLK_LEGACY */

630
arch/sh/kernel/cpu/clock.c
View File

@@ -10,558 +10,16 @@
*
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
*
* With clkdev bits:
*
* Copyright (C) 2008 Russell King.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/list.h>
#include <linux/kobject.h>
#include <linux/sysdev.h>
#include <linux/seq_file.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/debugfs.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <asm/clock.h>
#include <asm/machvec.h>
static LIST_HEAD(clock_list);
static DEFINE_SPINLOCK(clock_lock);
static DEFINE_MUTEX(clock_list_sem);
void clk_rate_table_build(struct clk *clk,
struct cpufreq_frequency_table *freq_table,
int nr_freqs,
struct clk_div_mult_table *src_table,
unsigned long *bitmap)
{
unsigned long mult, div;
unsigned long freq;
int i;
for (i = 0; i < nr_freqs; i++) {
div = 1;
mult = 1;
if (src_table->divisors && i < src_table->nr_divisors)
div = src_table->divisors[i];
if (src_table->multipliers && i < src_table->nr_multipliers)
mult = src_table->multipliers[i];
if (!div || !mult || (bitmap && !test_bit(i, bitmap)))
freq = CPUFREQ_ENTRY_INVALID;
else
freq = clk->parent->rate * mult / div;
freq_table[i].index = i;
freq_table[i].frequency = freq;
}
/* Termination entry */
freq_table[i].index = i;
freq_table[i].frequency = CPUFREQ_TABLE_END;
}
long clk_rate_table_round(struct clk *clk,
struct cpufreq_frequency_table *freq_table,
unsigned long rate)
{
unsigned long rate_error, rate_error_prev = ~0UL;
unsigned long rate_best_fit = rate;
unsigned long highest, lowest;
int i;
highest = lowest = 0;
for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
unsigned long freq = freq_table[i].frequency;
if (freq == CPUFREQ_ENTRY_INVALID)
continue;
if (freq > highest)
highest = freq;
if (freq < lowest)
lowest = freq;
rate_error = abs(freq - rate);
if (rate_error < rate_error_prev) {
rate_best_fit = freq;
rate_error_prev = rate_error;
}
if (rate_error == 0)
break;
}
if (rate >= highest)
rate_best_fit = highest;
if (rate <= lowest)
rate_best_fit = lowest;
return rate_best_fit;
}
int clk_rate_table_find(struct clk *clk,
struct cpufreq_frequency_table *freq_table,
unsigned long rate)
{
int i;
for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
unsigned long freq = freq_table[i].frequency;
if (freq == CPUFREQ_ENTRY_INVALID)
continue;
if (freq == rate)
return i;
}
return -ENOENT;
}
/* Used for clocks that always have same value as the parent clock */
unsigned long followparent_recalc(struct clk *clk)
{
return clk->parent ? clk->parent->rate : 0;
}
int clk_reparent(struct clk *child, struct clk *parent)
{
list_del_init(&child->sibling);
if (parent)
list_add(&child->sibling, &parent->children);
child->parent = parent;
/* now do the debugfs renaming to reattach the child
to the proper parent */
return 0;
}
/* Propagate rate to children */
void propagate_rate(struct clk *tclk)
{
struct clk *clkp;
list_for_each_entry(clkp, &tclk->children, sibling) {
if (clkp->ops && clkp->ops->recalc)
clkp->rate = clkp->ops->recalc(clkp);
propagate_rate(clkp);
}
}
static void __clk_disable(struct clk *clk)
{
if (clk->usecount == 0) {
printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
clk->name);
WARN_ON(1);
return;
}
if (!(--clk->usecount)) {
if (likely(clk->ops && clk->ops->disable))
clk->ops->disable(clk);
if (likely(clk->parent))
__clk_disable(clk->parent);
}
}
void clk_disable(struct clk *clk)
{
unsigned long flags;
if (!clk)
return;
spin_lock_irqsave(&clock_lock, flags);
__clk_disable(clk);
spin_unlock_irqrestore(&clock_lock, flags);
}
EXPORT_SYMBOL_GPL(clk_disable);
static int __clk_enable(struct clk *clk)
{
int ret = 0;
if (clk->usecount++ == 0) {
if (clk->parent) {
ret = __clk_enable(clk->parent);
if (unlikely(ret))
goto err;
}
if (clk->ops && clk->ops->enable) {
ret = clk->ops->enable(clk);
if (ret) {
if (clk->parent)
__clk_disable(clk->parent);
goto err;
}
}
}
return ret;
err:
clk->usecount--;
return ret;
}
int clk_enable(struct clk *clk)
{
unsigned long flags;
int ret;
if (!clk)
return -EINVAL;
spin_lock_irqsave(&clock_lock, flags);
ret = __clk_enable(clk);
spin_unlock_irqrestore(&clock_lock, flags);
return ret;
}
EXPORT_SYMBOL_GPL(clk_enable);
static LIST_HEAD(root_clks);
/**
* recalculate_root_clocks - recalculate and propagate all root clocks
*
* Recalculates all root clocks (clocks with no parent), which if the
* clock's .recalc is set correctly, should also propagate their rates.
* Called at init.
*/
void recalculate_root_clocks(void)
{
struct clk *clkp;
list_for_each_entry(clkp, &root_clks, sibling) {
if (clkp->ops && clkp->ops->recalc)
clkp->rate = clkp->ops->recalc(clkp);
propagate_rate(clkp);
}
}
int clk_register(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
/*
* trap out already registered clocks
*/
if (clk->node.next || clk->node.prev)
return 0;
mutex_lock(&clock_list_sem);
INIT_LIST_HEAD(&clk->children);
clk->usecount = 0;
if (clk->parent)
list_add(&clk->sibling, &clk->parent->children);
else
list_add(&clk->sibling, &root_clks);
list_add(&clk->node, &clock_list);
if (clk->ops && clk->ops->init)
clk->ops->init(clk);
mutex_unlock(&clock_list_sem);
return 0;
}
EXPORT_SYMBOL_GPL(clk_register);
void clk_unregister(struct clk *clk)
{
mutex_lock(&clock_list_sem);
list_del(&clk->sibling);
list_del(&clk->node);
mutex_unlock(&clock_list_sem);
}
EXPORT_SYMBOL_GPL(clk_unregister);
static void clk_enable_init_clocks(void)
{
struct clk *clkp;
list_for_each_entry(clkp, &clock_list, node)
if (clkp->flags & CLK_ENABLE_ON_INIT)
clk_enable(clkp);
}
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL_GPL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return clk_set_rate_ex(clk, rate, 0);
}
EXPORT_SYMBOL_GPL(clk_set_rate);
int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
{
int ret = -EOPNOTSUPP;
unsigned long flags;
spin_lock_irqsave(&clock_lock, flags);
if (likely(clk->ops && clk->ops->set_rate)) {
ret = clk->ops->set_rate(clk, rate, algo_id);
if (ret != 0)
goto out_unlock;
} else {
clk->rate = rate;
ret = 0;
}
if (clk->ops && clk->ops->recalc)
clk->rate = clk->ops->recalc(clk);
propagate_rate(clk);
out_unlock:
spin_unlock_irqrestore(&clock_lock, flags);
return ret;
}
EXPORT_SYMBOL_GPL(clk_set_rate_ex);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
unsigned long flags;
int ret = -EINVAL;
if (!parent || !clk)
return ret;
if (clk->parent == parent)
return 0;
spin_lock_irqsave(&clock_lock, flags);
if (clk->usecount == 0) {
if (clk->ops->set_parent)
ret = clk->ops->set_parent(clk, parent);
else
ret = clk_reparent(clk, parent);
if (ret == 0) {
pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
clk->name, clk->parent->name, clk->rate);
if (clk->ops->recalc)
clk->rate = clk->ops->recalc(clk);
propagate_rate(clk);
}
} else
ret = -EBUSY;
spin_unlock_irqrestore(&clock_lock, flags);
return ret;
}
EXPORT_SYMBOL_GPL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
return clk->parent;
}
EXPORT_SYMBOL_GPL(clk_get_parent);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (likely(clk->ops && clk->ops->round_rate)) {
unsigned long flags, rounded;
spin_lock_irqsave(&clock_lock, flags);
rounded = clk->ops->round_rate(clk, rate);
spin_unlock_irqrestore(&clock_lock, flags);
return rounded;
}
return clk_get_rate(clk);
}
EXPORT_SYMBOL_GPL(clk_round_rate);
/*
* Find the correct struct clk for the device and connection ID.
* We do slightly fuzzy matching here:
* An entry with a NULL ID is assumed to be a wildcard.
* If an entry has a device ID, it must match
* If an entry has a connection ID, it must match
* Then we take the most specific entry - with the following
* order of precedence: dev+con > dev only > con only.
*/
static struct clk *clk_find(const char *dev_id, const char *con_id)
{
struct clk_lookup *p;
struct clk *clk = NULL;
int match, best = 0;
list_for_each_entry(p, &clock_list, node) {
match = 0;
if (p->dev_id) {
if (!dev_id || strcmp(p->dev_id, dev_id))
continue;
match += 2;
}
if (p->con_id) {
if (!con_id || strcmp(p->con_id, con_id))
continue;
match += 1;
}
if (match == 0)
continue;
if (match > best) {
clk = p->clk;
best = match;
}
}
return clk;
}
struct clk *clk_get_sys(const char *dev_id, const char *con_id)
{
struct clk *clk;
mutex_lock(&clock_list_sem);
clk = clk_find(dev_id, con_id);
mutex_unlock(&clock_list_sem);
return clk ? clk : ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL_GPL(clk_get_sys);
/*
* Returns a clock. Note that we first try to use device id on the bus
* and clock name. If this fails, we try to use clock name only.
*/
struct clk *clk_get(struct device *dev, const char *id)
{
const char *dev_id = dev ? dev_name(dev) : NULL;
struct clk *p, *clk = ERR_PTR(-ENOENT);
int idno;
clk = clk_get_sys(dev_id, id);
if (clk && !IS_ERR(clk))
return clk;
if (dev == NULL || dev->bus != &platform_bus_type)
idno = -1;
else
idno = to_platform_device(dev)->id;
mutex_lock(&clock_list_sem);
list_for_each_entry(p, &clock_list, node) {
if (p->id == idno &&
strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
clk = p;
goto found;
}
}
list_for_each_entry(p, &clock_list, node) {
if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
clk = p;
break;
}
}
found:
mutex_unlock(&clock_list_sem);
return clk;
}
EXPORT_SYMBOL_GPL(clk_get);
void clk_put(struct clk *clk)
{
if (clk && !IS_ERR(clk))
module_put(clk->owner);
}
EXPORT_SYMBOL_GPL(clk_put);
#ifdef CONFIG_PM
static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
{
static pm_message_t prev_state;
struct clk *clkp;
switch (state.event) {
case PM_EVENT_ON:
/* Resumeing from hibernation */
if (prev_state.event != PM_EVENT_FREEZE)
break;
list_for_each_entry(clkp, &clock_list, node) {
if (likely(clkp->ops)) {
unsigned long rate = clkp->rate;
if (likely(clkp->ops->set_parent))
clkp->ops->set_parent(clkp,
clkp->parent);
if (likely(clkp->ops->set_rate))
clkp->ops->set_rate(clkp,
rate, NO_CHANGE);
else if (likely(clkp->ops->recalc))
clkp->rate = clkp->ops->recalc(clkp);
}
}
break;
case PM_EVENT_FREEZE:
break;
case PM_EVENT_SUSPEND:
break;
}
prev_state = state;
return 0;
}
static int clks_sysdev_resume(struct sys_device *dev)
{
return clks_sysdev_suspend(dev, PMSG_ON);
}
static struct sysdev_class clks_sysdev_class = {
.name = "clks",
};
static struct sysdev_driver clks_sysdev_driver = {
.suspend = clks_sysdev_suspend,
.resume = clks_sysdev_resume,
};
static struct sys_device clks_sysdev_dev = {
.cls = &clks_sysdev_class,
};
static int __init clk_sysdev_init(void)
{
sysdev_class_register(&clks_sysdev_class);
sysdev_driver_register(&clks_sysdev_class, &clks_sysdev_driver);
sysdev_register(&clks_sysdev_dev);
return 0;
}
subsys_initcall(clk_sysdev_init);
#endif
int __init clk_init(void)
{
int ret;
@@ -591,89 +49,19 @@ int __init clk_init(void)
}
/*
* debugfs support to trace clock tree hierarchy and attributes
* Returns a clock. Note that we first try to use device id on the bus
* and clock name. If this fails, we try to use clock name only.
*/
static struct dentry *clk_debugfs_root;
static int clk_debugfs_register_one(struct clk *c)
struct clk *clk_get(struct device *dev, const char *con_id)
{
int err;
struct dentry *d, *child, *child_tmp;
struct clk *pa = c->parent;
char s[255];
char *p = s;
const char *dev_id = dev ? dev_name(dev) : NULL;
p += sprintf(p, "%s", c->name);
if (c->id >= 0)
sprintf(p, ":%d", c->id);
d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root);
if (!d)
return -ENOMEM;
c->dentry = d;
d = debugfs_create_u8("usecount", S_IRUGO, c->dentry, (u8 *)&c->usecount);
if (!d) {
err = -ENOMEM;
goto err_out;
}
d = debugfs_create_u32("rate", S_IRUGO, c->dentry, (u32 *)&c->rate);
if (!d) {
err = -ENOMEM;
goto err_out;
}
d = debugfs_create_x32("flags", S_IRUGO, c->dentry, (u32 *)&c->flags);
if (!d) {
err = -ENOMEM;
goto err_out;
}
return 0;
err_out:
d = c->dentry;
list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
debugfs_remove(child);
debugfs_remove(c->dentry);
return err;
return clk_get_sys(dev_id, con_id);
}
EXPORT_SYMBOL_GPL(clk_get);
static int clk_debugfs_register(struct clk *c)
void clk_put(struct clk *clk)
{
int err;
struct clk *pa = c->parent;
if (pa && !pa->dentry) {
err = clk_debugfs_register(pa);
if (err)
return err;
}
if (!c->dentry) {
err = clk_debugfs_register_one(c);
if (err)
return err;
}
return 0;
}
EXPORT_SYMBOL_GPL(clk_put);
static int __init clk_debugfs_init(void)
{
struct clk *c;
struct dentry *d;
int err;
d = debugfs_create_dir("clock", NULL);
if (!d)
return -ENOMEM;
clk_debugfs_root = d;
list_for_each_entry(c, &clock_list, node) {
err = clk_debugfs_register(c);
if (err)
goto err_out;
}
return 0;
err_out:
debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
return err;
}
late_initcall(clk_debugfs_init);

5
arch/sh/kernel/cpu/hwblk.c
View File

@@ -146,6 +146,11 @@ int __init sh_hwblk_clk_register(struct clk *clks, int nr)
for (k = 0; !ret && (k < nr); k++) {
clkp = clks + k;
/* skip over clocks using hwblk 0 (HWBLK_UNKNOWN) */
if (!clkp->arch_flags)
continue;
clkp->ops = &sh_hwblk_clk_ops;
ret |= clk_register(clkp);
}

24
arch/sh/kernel/cpu/init.c
View File

@@ -43,9 +43,9 @@
* peripherals (nofpu, nodsp, and so forth).
*/
#define onchip_setup(x) \
static int x##_disabled __initdata = !cpu_has_##x; \
static int x##_disabled __cpuinitdata = !cpu_has_##x; \
\
static int __init x##_setup(char *opts) \
static int __cpuinit x##_setup(char *opts) \
{ \
x##_disabled = 1; \
return 1; \
@@ -59,7 +59,7 @@ onchip_setup(dsp);
#define CPUOPM 0xff2f0000
#define CPUOPM_RABD (1 << 5)
static void __init speculative_execution_init(void)
static void __cpuinit speculative_execution_init(void)
{
/* Clear RABD */
__raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
@@ -78,7 +78,7 @@ static void __init speculative_execution_init(void)
#define EXPMASK_BRDSSLP (1 << 1)
#define EXPMASK_MMCAW (1 << 4)
static void __init expmask_init(void)
static void __cpuinit expmask_init(void)
{
unsigned long expmask = __raw_readl(EXPMASK);
@@ -217,7 +217,7 @@ static void detect_cache_shape(void)
l2_cache_shape = -1; /* No S-cache */
}
static void __init fpu_init(void)
static void __cpuinit fpu_init(void)
{
/* Disable the FPU */
if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) {
@@ -230,7 +230,7 @@ static void __init fpu_init(void)
}
#ifdef CONFIG_SH_DSP
static void __init release_dsp(void)
static void __cpuinit release_dsp(void)
{
unsigned long sr;
@@ -244,7 +244,7 @@ static void __init release_dsp(void)
);
}
static void __init dsp_init(void)
static void __cpuinit dsp_init(void)
{
unsigned long sr;
@@ -276,11 +276,11 @@ static void __init dsp_init(void)
release_dsp();
}
#else
static inline void __init dsp_init(void) { }
static inline void __cpuinit dsp_init(void) { }
#endif /* CONFIG_SH_DSP */
/**
* sh_cpu_init
* cpu_init
*
* This is our initial entry point for each CPU, and is invoked on the
* boot CPU prior to calling start_kernel(). For SMP, a combination of
@@ -293,14 +293,14 @@ static inline void __init dsp_init(void) { }
* subtype and initial configuration will all be done.
*
* Each processor family is still responsible for doing its own probing
* and cache configuration in detect_cpu_and_cache_system().
* and cache configuration in cpu_probe().
*/
asmlinkage void __init sh_cpu_init(void)
asmlinkage void __cpuinit cpu_init(void)
{
current_thread_info()->cpu = hard_smp_processor_id();
/* First, probe the CPU */
detect_cpu_and_cache_system();
cpu_probe();
if (current_cpu_data.type == CPU_SH_NONE)
panic("Unknown CPU");

5
arch/sh/kernel/cpu/sh2/probe.c
View File

@@ -13,7 +13,7 @@
#include <asm/processor.h>
#include <asm/cache.h>
int __init detect_cpu_and_cache_system(void)
void __cpuinit cpu_probe(void)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
boot_cpu_data.type = CPU_SH7619;
@@ -30,7 +30,4 @@ int __init detect_cpu_and_cache_system(void)
boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
boot_cpu_data.icache = boot_cpu_data.dcache;
boot_cpu_data.family = CPU_FAMILY_SH2;
return 0;
}

6
arch/sh/kernel/cpu/sh2/setup-sh7619.c
View File

@@ -128,17 +128,14 @@ static struct platform_device eth_device = {
};
static struct sh_timer_config cmt0_platform_data = {
.name = "CMT0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
static struct resource cmt0_resources[] = {
[0] = {
.name = "CMT0",
.start = 0xf84a0072,
.end = 0xf84a0077,
.flags = IORESOURCE_MEM,
@@ -160,17 +157,14 @@ static struct platform_device cmt0_device = {
};
static struct sh_timer_config cmt1_platform_data = {
.name = "CMT1",
.channel_offset = 0x08,
.timer_bit = 1,
.clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
static struct resource cmt1_resources[] = {
[0] = {
.name = "CMT1",
.start = 0xf84a0078,
.end = 0xf84a007d,
.flags = IORESOURCE_MEM,

4
arch/sh/kernel/cpu/sh2a/probe.c
View File

@@ -13,7 +13,7 @@
#include <asm/processor.h>
#include <asm/cache.h>
int __init detect_cpu_and_cache_system(void)
void __cpuinit cpu_probe(void)
{
boot_cpu_data.family = CPU_FAMILY_SH2A;
@@ -51,6 +51,4 @@ int __init detect_cpu_and_cache_system(void)
* on the cache info.
*/
boot_cpu_data.icache = boot_cpu_data.dcache;
return 0;
}

9
arch/sh/kernel/cpu/sh2a/setup-mxg.c
View File

@@ -115,16 +115,13 @@ static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
mask_registers, prio_registers, NULL);
static struct sh_timer_config mtu2_0_platform_data = {
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_0_resources[] = {
[0] = {
.name = "MTU2_0",
.start = 0xff801300,
.end = 0xff801326,
.flags = IORESOURCE_MEM,
@@ -146,16 +143,13 @@ static struct platform_device mtu2_0_device = {
};
static struct sh_timer_config mtu2_1_platform_data = {
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_1_resources[] = {
[0] = {
.name = "MTU2_1",
.start = 0xff801380,
.end = 0xff801390,
.flags = IORESOURCE_MEM,
@@ -177,16 +171,13 @@ static struct platform_device mtu2_1_device = {
};
static struct sh_timer_config mtu2_2_platform_data = {
.name = "MTU2_2",
.channel_offset = 0x80,
.timer_bit = 2,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_2_resources[] = {
[0] = {
.name = "MTU2_2",
.start = 0xff801000,
.end = 0xff80100a,
.flags = IORESOURCE_MEM,

9
arch/sh/kernel/cpu/sh2a/setup-sh7201.c
View File

@@ -318,16 +318,13 @@ static struct platform_device rtc_device = {
};
static struct sh_timer_config mtu2_0_platform_data = {
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_0_resources[] = {
[0] = {
.name = "MTU2_0",
.start = 0xfffe4300,
.end = 0xfffe4326,
.flags = IORESOURCE_MEM,
@@ -349,16 +346,13 @@ static struct platform_device mtu2_0_device = {
};
static struct sh_timer_config mtu2_1_platform_data = {
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_1_resources[] = {
[0] = {
.name = "MTU2_1",
.start = 0xfffe4380,
.end = 0xfffe4390,
.flags = IORESOURCE_MEM,
@@ -380,16 +374,13 @@ static struct platform_device mtu2_1_device = {
};
static struct sh_timer_config mtu2_2_platform_data = {
.name = "MTU2_2",
.channel_offset = 0x80,
.timer_bit = 2,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_2_resources[] = {
[0] = {
.name = "MTU2_2",
.start = 0xfffe4000,
.end = 0xfffe400a,
.flags = IORESOURCE_MEM,

12
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
View File

@@ -234,17 +234,14 @@ static struct platform_device scif3_device = {
};
static struct sh_timer_config cmt0_platform_data = {
.name = "CMT0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
static struct resource cmt0_resources[] = {
[0] = {
.name = "CMT0",
.start = 0xfffec002,
.end = 0xfffec007,
.flags = IORESOURCE_MEM,
@@ -266,17 +263,14 @@ static struct platform_device cmt0_device = {
};
static struct sh_timer_config cmt1_platform_data = {
.name = "CMT1",
.channel_offset = 0x08,
.timer_bit = 1,
.clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
static struct resource cmt1_resources[] = {
[0] = {
.name = "CMT1",
.start = 0xfffec008,
.end = 0xfffec00d,
.flags = IORESOURCE_MEM,
@@ -298,16 +292,13 @@ static struct platform_device cmt1_device = {
};
static struct sh_timer_config mtu2_0_platform_data = {
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_0_resources[] = {
[0] = {
.name = "MTU2_0",
.start = 0xfffe4300,
.end = 0xfffe4326,
.flags = IORESOURCE_MEM,
@@ -329,16 +320,13 @@ static struct platform_device mtu2_0_device = {
};
static struct sh_timer_config mtu2_1_platform_data = {
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_1_resources[] = {
[0] = {
.name = "MTU2_1",
.start = 0xfffe4380,
.end = 0xfffe4390,
.flags = IORESOURCE_MEM,

15
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
View File

@@ -194,17 +194,14 @@ static struct platform_device scif3_device = {
};
static struct sh_timer_config cmt0_platform_data = {
.name = "CMT0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
static struct resource cmt0_resources[] = {
[0] = {
.name = "CMT0",
.start = 0xfffec002,
.end = 0xfffec007,
.flags = IORESOURCE_MEM,
@@ -226,17 +223,14 @@ static struct platform_device cmt0_device = {
};
static struct sh_timer_config cmt1_platform_data = {
.name = "CMT1",
.channel_offset = 0x08,
.timer_bit = 1,
.clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
static struct resource cmt1_resources[] = {
[0] = {
.name = "CMT1",
.start = 0xfffec008,
.end = 0xfffec00d,
.flags = IORESOURCE_MEM,
@@ -258,16 +252,13 @@ static struct platform_device cmt1_device = {
};
static struct sh_timer_config mtu2_0_platform_data = {
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_0_resources[] = {
[0] = {
.name = "MTU2_0",
.start = 0xfffe4300,
.end = 0xfffe4326,
.flags = IORESOURCE_MEM,
@@ -289,16 +280,13 @@ static struct platform_device mtu2_0_device = {
};
static struct sh_timer_config mtu2_1_platform_data = {
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_1_resources[] = {
[0] = {
.name = "MTU2_1",
.start = 0xfffe4380,
.end = 0xfffe4390,
.flags = IORESOURCE_MEM,
@@ -320,16 +308,13 @@ static struct platform_device mtu2_1_device = {
};
static struct sh_timer_config mtu2_2_platform_data = {
.name = "MTU2_2",
.channel_offset = 0x80,
.timer_bit = 2,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource mtu2_2_resources[] = {
[0] = {
.name = "MTU2_2",
.start = 0xfffe4000,
.end = 0xfffe400a,
.flags = IORESOURCE_MEM,

4
arch/sh/kernel/cpu/sh3/probe.c
View File

@@ -16,7 +16,7 @@
#include <asm/cache.h>
#include <asm/io.h>
int detect_cpu_and_cache_system(void)
void __cpuinit cpu_probe(void)
{
unsigned long addr0, addr1, data0, data1, data2, data3;
@@ -108,6 +108,4 @@ int detect_cpu_and_cache_system(void)
boot_cpu_data.icache = boot_cpu_data.dcache;
boot_cpu_data.family = CPU_FAMILY_SH3;
return 0;
}

9
arch/sh/kernel/cpu/sh3/setup-sh7705.c
View File

@@ -124,16 +124,13 @@ static struct platform_device rtc_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xfffffe94,
.end = 0xfffffe9f,
.flags = IORESOURCE_MEM,
@@ -155,16 +152,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xfffffea0,
.end = 0xfffffeab,
.flags = IORESOURCE_MEM,
@@ -186,15 +180,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xfffffeac,
.end = 0xfffffebb,
.flags = IORESOURCE_MEM,

9
arch/sh/kernel/cpu/sh3/setup-sh770x.c
View File

@@ -157,16 +157,13 @@ static struct platform_device scif2_device = {
#endif
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xfffffe94,
.end = 0xfffffe9f,
.flags = IORESOURCE_MEM,
@@ -188,16 +185,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xfffffea0,
.end = 0xfffffeab,
.flags = IORESOURCE_MEM,
@@ -219,15 +213,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xfffffeac,
.end = 0xfffffebb,
.flags = IORESOURCE_MEM,

9
arch/sh/kernel/cpu/sh3/setup-sh7710.c
View File

@@ -127,16 +127,13 @@ static struct platform_device scif1_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xa412fe94,
.end = 0xa412fe9f,
.flags = IORESOURCE_MEM,
@@ -158,16 +155,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xa412fea0,
.end = 0xa412feab,
.flags = IORESOURCE_MEM,
@@ -189,15 +183,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xa412feac,
.end = 0xa412feb5,
.flags = IORESOURCE_MEM,

24
arch/sh/kernel/cpu/sh3/setup-sh7720.c
View File

@@ -130,17 +130,14 @@ static struct platform_device usbf_device = {
};
static struct sh_timer_config cmt0_platform_data = {
.name = "CMT0",
.channel_offset = 0x10,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 125,
};
static struct resource cmt0_resources[] = {
[0] = {
.name = "CMT0",
.start = 0x044a0010,
.end = 0x044a001b,
.flags = IORESOURCE_MEM,
@@ -162,15 +159,12 @@ static struct platform_device cmt0_device = {
};
static struct sh_timer_config cmt1_platform_data = {
.name = "CMT1",
.channel_offset = 0x20,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource cmt1_resources[] = {
[0] = {
.name = "CMT1",
.start = 0x044a0020,
.end = 0x044a002b,
.flags = IORESOURCE_MEM,
@@ -192,15 +186,12 @@ static struct platform_device cmt1_device = {
};
static struct sh_timer_config cmt2_platform_data = {
.name = "CMT2",
.channel_offset = 0x30,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource cmt2_resources[] = {
[0] = {
.name = "CMT2",
.start = 0x044a0030,
.end = 0x044a003b,
.flags = IORESOURCE_MEM,
@@ -222,15 +213,12 @@ static struct platform_device cmt2_device = {
};
static struct sh_timer_config cmt3_platform_data = {
.name = "CMT3",
.channel_offset = 0x40,
.timer_bit = 3,
.clk = "peripheral_clk",
};
static struct resource cmt3_resources[] = {
[0] = {
.name = "CMT3",
.start = 0x044a0040,
.end = 0x044a004b,
.flags = IORESOURCE_MEM,
@@ -252,15 +240,12 @@ static struct platform_device cmt3_device = {
};
static struct sh_timer_config cmt4_platform_data = {
.name = "CMT4",
.channel_offset = 0x50,
.timer_bit = 4,
.clk = "peripheral_clk",
};
static struct resource cmt4_resources[] = {
[0] = {
.name = "CMT4",
.start = 0x044a0050,
.end = 0x044a005b,
.flags = IORESOURCE_MEM,
@@ -282,16 +267,13 @@ static struct platform_device cmt4_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xa412fe94,
.end = 0xa412fe9f,
.flags = IORESOURCE_MEM,
@@ -313,16 +295,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xa412fea0,
.end = 0xa412feab,
.flags = IORESOURCE_MEM,
@@ -344,15 +323,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xa412feac,
.end = 0xa412feb5,
.flags = IORESOURCE_MEM,

17
arch/sh/kernel/cpu/sh4/clock-sh4-202.c
View File

@@ -12,9 +12,10 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <asm/io.h>
#define CPG2_FRQCR3 0xfe0a0018
@@ -45,7 +46,6 @@ static struct clk_ops sh4202_emi_clk_ops = {
};
static struct clk sh4202_emi_clk = {
.name = "emi_clk",
.flags = CLK_ENABLE_ON_INIT,
.ops = &sh4202_emi_clk_ops,
};
@@ -61,7 +61,6 @@ static struct clk_ops sh4202_femi_clk_ops = {
};
static struct clk sh4202_femi_clk = {
.name = "femi_clk",
.flags = CLK_ENABLE_ON_INIT,
.ops = &sh4202_femi_clk_ops,
};
@@ -139,7 +138,6 @@ static struct clk_ops sh4202_shoc_clk_ops = {
};
static struct clk sh4202_shoc_clk = {
.name = "shoc_clk",
.flags = CLK_ENABLE_ON_INIT,
.ops = &sh4202_shoc_clk_ops,
};
@@ -150,6 +148,15 @@ static struct clk *sh4202_onchip_clocks[] = {
&sh4202_shoc_clk,
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk),
CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk),
CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk),
};
int __init arch_clk_init(void)
{
struct clk *clk;
@@ -167,5 +174,7 @@ int __init arch_clk_init(void)
clk_put(clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return ret;
}

4
arch/sh/kernel/cpu/sh4/probe.c
View File

@@ -15,7 +15,7 @@
#include <asm/processor.h>
#include <asm/cache.h>
int __init detect_cpu_and_cache_system(void)
void __cpuinit cpu_probe(void)
{
unsigned long pvr, prr, cvr;
unsigned long size;
@@ -251,6 +251,4 @@ int __init detect_cpu_and_cache_system(void)
boot_cpu_data.scache.linesz);
}
}
return 0;
}

9
arch/sh/kernel/cpu/sh4/setup-sh4-202.c
View File

@@ -31,16 +31,13 @@ static struct platform_device scif0_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -62,16 +59,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -93,15 +87,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002f,
.flags = IORESOURCE_MEM,

15
arch/sh/kernel/cpu/sh4/setup-sh7750.c
View File

@@ -66,16 +66,13 @@ static struct platform_device scif1_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -97,16 +94,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -128,15 +122,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002f,
.flags = IORESOURCE_MEM,
@@ -163,15 +154,12 @@ static struct platform_device tmu2_device = {
defined(CONFIG_CPU_SUBTYPE_SH7751R)
static struct sh_timer_config tmu3_platform_data = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
[0] = {
.name = "TMU3",
.start = 0xfe100008,
.end = 0xfe100013,
.flags = IORESOURCE_MEM,
@@ -193,15 +181,12 @@ static struct platform_device tmu3_device = {
};
static struct sh_timer_config tmu4_platform_data = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
[0] = {
.name = "TMU4",
.start = 0xfe100014,
.end = 0xfe10001f,
.flags = IORESOURCE_MEM,

9
arch/sh/kernel/cpu/sh4/setup-sh7760.c
View File

@@ -187,16 +187,13 @@ static struct platform_device scif3_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -218,16 +215,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -249,15 +243,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002f,
.flags = IORESOURCE_MEM,

225
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
View File

@@ -21,6 +21,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
/* SH7343 registers */
@@ -36,8 +37,6 @@
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
.name = "rclk",
.id = -1,
.rate = 32768,
};
@@ -46,8 +45,6 @@ static struct clk r_clk = {
* from the platform code.
*/
struct clk extal_clk = {
.name = "extal",
.id = -1,
.rate = 33333333,
};
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
};
static struct clk dll_clk = {
.name = "dll_clk",
.id = -1,
.ops = &dll_clk_ops,
.parent = &r_clk,
.flags = CLK_ENABLE_ON_INIT,
@@ -91,8 +86,6 @@ static struct clk_ops pll_clk_ops = {
};
static struct clk pll_clk = {
.name = "pll_clk",
.id = -1,
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
};
@@ -121,72 +114,168 @@ static struct clk_div4_table div4_table = {
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
DIV4_SIUA, DIV4_SIUB, DIV4_NR };
#define DIV4(_str, _reg, _bit, _mask, _flags) \
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
};
struct clk div6_clks[] = {
SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
enum { DIV6_V, DIV6_NR };
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};
#define MSTP(_str, _parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
#define MSTP(_parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
static struct clk mstp_clks[] = {
MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0),
MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
MSTP109, MSTP108, MSTP100,
MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP_NR };
MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0),
static struct clk mstp_clks[MSTP_NR] = {
[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
[MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
[MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
[MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0),
MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0),
MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0),
MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0),
MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
[MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
[MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
[MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
[MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
[MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
[MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
[MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
[MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("rclk", &r_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("dll_clk", &dll_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
/* DIV6 clocks */
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
/* MSTP32 clocks */
CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
{
/* SCIF0 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP007],
}, {
/* SCIF1 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP006],
}, {
/* SCIF2 */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP005],
}, {
/* SCIF3 */
.dev_id = "sh-sci.3",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP004],
},
CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
};
int __init arch_clk_init(void)
@@ -202,14 +291,16 @@ int __init arch_clk_init(void)
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
return ret;
}

206
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
View File

@@ -21,6 +21,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
/* SH7366 registers */
@@ -36,8 +37,6 @@
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
.name = "rclk",
.id = -1,
.rate = 32768,
};
@@ -46,8 +45,6 @@ static struct clk r_clk = {
* from the platform code.
*/
struct clk extal_clk = {
.name = "extal",
.id = -1,
.rate = 33333333,
};
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
};
static struct clk dll_clk = {
.name = "dll_clk",
.id = -1,
.ops = &dll_clk_ops,
.parent = &r_clk,
.flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
};
static struct clk pll_clk = {
.name = "pll_clk",
.id = -1,
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
};
@@ -124,69 +117,154 @@ static struct clk_div4_table div4_table = {
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
DIV4_SIUA, DIV4_SIUB, DIV4_NR };
#define DIV4(_str, _reg, _bit, _mask, _flags) \
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
};
struct clk div6_clks[] = {
SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
enum { DIV6_V, DIV6_NR };
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};
#define MSTP(_str, _parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
#define MSTP(_parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
static struct clk mstp_clks[] = {
enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
MSTP109, MSTP100,
MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0),
MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0),
MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0),
MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0),
MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
[MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
[MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
[MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
[MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
[MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("rclk", &r_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("dll_clk", &dll_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
/* DIV6 clocks */
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
/* MSTP32 clocks */
CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
{
/* SCIF0 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP007],
}, {
/* SCIF1 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP006],
}, {
/* SCIF2 */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP005],
},
CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
};
int __init arch_clk_init(void)
@@ -202,14 +280,16 @@ int __init arch_clk_init(void)
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
return ret;
}

171
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
View File

@@ -21,6 +21,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/hwblk.h>
#include <cpu/sh7722.h>
@@ -36,8 +37,6 @@
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
.name = "rclk",
.id = -1,
.rate = 32768,
};
@@ -46,8 +45,6 @@ static struct clk r_clk = {
* from the platform code.
*/
struct clk extal_clk = {
.name = "extal",
.id = -1,
.rate = 33333333,
};
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
};
static struct clk dll_clk = {
.name = "dll_clk",
.id = -1,
.ops = &dll_clk_ops,
.parent = &r_clk,
.flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
};
static struct clk pll_clk = {
.name = "pll_clk",
.id = -1,
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
};
@@ -121,68 +114,142 @@ static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
};
#define DIV4(_str, _reg, _bit, _mask, _flags) \
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
};
enum { DIV4_IRDA, DIV4_ENABLE_NR };
struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
};
enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
};
struct clk div6_clks[] = {
SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
enum { DIV6_V, DIV6_NR };
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};
#define R_CLK &r_clk
#define P_CLK &div4_clks[DIV4_P]
#define B_CLK &div4_clks[DIV4_B]
#define U_CLK &div4_clks[DIV4_U]
static struct clk mstp_clks[HWBLK_NR] = {
SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
static struct clk mstp_clks[] = {
SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0),
SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
};
SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0),
SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0),
SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0),
SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0),
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("rclk", &r_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("dll_clk", &dll_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
/* DIV6 clocks */
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
/* MSTP clocks */
CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
{
/* TMU0 */
.dev_id = "sh_tmu.0",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU],
}, {
/* TMU1 */
.dev_id = "sh_tmu.1",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU],
}, {
/* TMU2 */
.dev_id = "sh_tmu.2",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU],
},
CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
{
/* SCIF0 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF0],
}, {
/* SCIF1 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF1],
}, {
/* SCIF2 */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF2],
},
CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
};
int __init arch_clk_init(void)
@@ -198,6 +265,8 @@ int __init arch_clk_init(void)
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
@@ -210,10 +279,10 @@ int __init arch_clk_init(void)
DIV4_REPARENT_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
return ret;
}

275
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
View File

@@ -21,6 +21,8 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/hwblk.h>
#include <cpu/sh7723.h>
@@ -36,8 +38,6 @@
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
.name = "rclk",
.id = -1,
.rate = 32768,
};
@@ -46,8 +46,6 @@ static struct clk r_clk = {
* from the platform code.
*/
struct clk extal_clk = {
.name = "extal",
.id = -1,
.rate = 33333333,
};
@@ -69,8 +67,6 @@ static struct clk_ops dll_clk_ops = {
};
static struct clk dll_clk = {
.name = "dll_clk",
.id = -1,
.ops = &dll_clk_ops,
.parent = &r_clk,
.flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +90,6 @@ static struct clk_ops pll_clk_ops = {
};
static struct clk pll_clk = {
.name = "pll_clk",
.id = -1,
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
};
@@ -123,92 +117,215 @@ static struct clk_div4_table div4_table = {
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
#define DIV4(_str, _reg, _bit, _mask, _flags) \
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
[DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
[DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
};
enum { DIV4_IRDA, DIV4_ENABLE_NR };
struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
};
enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
};
struct clk div6_clks[] = {
SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
};
enum { DIV6_V, DIV6_NR };
#define R_CLK (&r_clk)
#define P_CLK (&div4_clks[DIV4_P])
#define B_CLK (&div4_clks[DIV4_B])
#define U_CLK (&div4_clks[DIV4_U])
#define I_CLK (&div4_clks[DIV4_I])
#define SH_CLK (&div4_clks[DIV4_SH])
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};
static struct clk mstp_clks[] = {
/* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("intc0", -1, I_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0),
SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0),
SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0),
SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0),
SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0),
SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0),
SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),
SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
SH_HWBLK_CLK("atapi0", -1, SH_CLK, HWBLK_ATAPI, 0),
SH_HWBLK_CLK("adc0", -1, P_CLK, HWBLK_ADC, 0),
SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0),
SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0),
SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0),
SH_HWBLK_CLK("icb0", -1, B_CLK, HWBLK_ICB, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0),
SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0),
SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0),
SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("rclk", &r_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("dll_clk", &dll_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
/* DIV6 clocks */
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
/* MSTP clocks */
CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
{
/* TMU0 */
.dev_id = "sh_tmu.0",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU0],
}, {
/* TMU1 */
.dev_id = "sh_tmu.1",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU0],
}, {
/* TMU2 */
.dev_id = "sh_tmu.2",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU0],
},
CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
{
/* TMU3 */
.dev_id = "sh_tmu.3",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU1],
}, {
/* TMU4 */
.dev_id = "sh_tmu.4",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU1],
}, {
/* TMU5 */
.dev_id = "sh_tmu.5",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU1],
},
CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
{
/* SCIF0 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF0],
}, {
/* SCIF1 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF1],
}, {
/* SCIF2 */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF2],
}, {
/* SCIF3 */
.dev_id = "sh-sci.3",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF3],
}, {
/* SCIF4 */
.dev_id = "sh-sci.4",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF4],
}, {
/* SCIF5 */
.dev_id = "sh-sci.5",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF5],
},
CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
};
int __init arch_clk_init(void)
@@ -222,7 +339,9 @@ int __init arch_clk_init(void)
pll_clk.parent = &extal_clk;
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
ret |= clk_register(main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
@@ -236,10 +355,10 @@ int __init arch_clk_init(void)
DIV4_REPARENT_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
return ret;
}

289
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
View File

@@ -21,6 +21,8 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/hwblk.h>
#include <cpu/sh7724.h>
@@ -39,8 +41,6 @@
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
.name = "rclk",
.id = -1,
.rate = 32768,
};
@@ -49,8 +49,6 @@ static struct clk r_clk = {
* from the platform code.
*/
struct clk extal_clk = {
.name = "extal",
.id = -1,
.rate = 33333333,
};
@@ -74,8 +72,6 @@ static struct clk_ops fll_clk_ops = {
};
static struct clk fll_clk = {
.name = "fll_clk",
.id = -1,
.ops = &fll_clk_ops,
.parent = &r_clk,
.flags = CLK_ENABLE_ON_INIT,
@@ -96,8 +92,6 @@ static struct clk_ops pll_clk_ops = {
};
static struct clk pll_clk = {
.name = "pll_clk",
.id = -1,
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
};
@@ -113,8 +107,6 @@ static struct clk_ops div3_clk_ops = {
};
static struct clk div3_clk = {
.name = "div3_clk",
.id = -1,
.ops = &div3_clk_ops,
.parent = &pll_clk,
};
@@ -151,86 +143,215 @@ static struct clk_div4_table div4_table = {
enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
#define DIV4(_str, _reg, _bit, _mask, _flags) \
SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
[DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
[DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
};
struct clk div6_clks[] = {
SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
[DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
[DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
[DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
[DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
};
#define R_CLK (&r_clk)
#define P_CLK (&div4_clks[DIV4_P])
#define B_CLK (&div4_clks[DIV4_B])
#define I_CLK (&div4_clks[DIV4_I])
#define SH_CLK (&div4_clks[DIV4_SH])
static struct clk mstp_clks[HWBLK_NR] = {
SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
static struct clk mstp_clks[] = {
SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("rs0", -1, B_CLK, HWBLK_RSMEM, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("intc0", -1, P_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0),
SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0),
SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0),
SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0),
SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0),
SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC0, 0),
SH_HWBLK_CLK("i2c1", -1, P_CLK, HWBLK_IIC1, 0),
SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
};
SH_HWBLK_CLK("mmc0", -1, B_CLK, HWBLK_MMC, 0),
SH_HWBLK_CLK("eth0", -1, B_CLK, HWBLK_ETHER, 0),
SH_HWBLK_CLK("atapi0", -1, B_CLK, HWBLK_ATAPI, 0),
SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0),
SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0),
SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0),
SH_HWBLK_CLK("usb1", -1, B_CLK, HWBLK_USB1, 0),
SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB0, 0),
SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0),
SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0),
SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0),
SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0),
SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0),
SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0),
SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0),
SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0),
SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("rclk", &r_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("fll_clk", &fll_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
CLKDEV_CON_ID("div3_clk", &div3_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
/* DIV6 clocks */
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
/* MSTP clocks */
CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
{
/* TMU0 */
.dev_id = "sh_tmu.0",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU0],
}, {
/* TMU1 */
.dev_id = "sh_tmu.1",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU0],
}, {
/* TMU2 */
.dev_id = "sh_tmu.2",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU0],
}, {
/* TMU3 */
.dev_id = "sh_tmu.3",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU1],
},
CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
{
/* TMU4 */
.dev_id = "sh_tmu.4",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU1],
}, {
/* TMU5 */
.dev_id = "sh_tmu.5",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU1],
}, {
/* SCIF0 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF0],
}, {
/* SCIF1 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF1],
}, {
/* SCIF2 */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF2],
}, {
/* SCIF3 */
.dev_id = "sh-sci.3",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF3],
}, {
/* SCIF4 */
.dev_id = "sh-sci.4",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF4],
}, {
/* SCIF5 */
.dev_id = "sh-sci.5",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF5],
},
CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]),
CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]),
CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
};
int __init arch_clk_init(void)
@@ -246,14 +367,16 @@ int __init arch_clk_init(void)
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
return ret;
}

11
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
View File

@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/freq.h>
@@ -87,7 +88,6 @@ static struct clk_ops sh7757_shyway_clk_ops = {
};
static struct clk sh7757_shyway_clk = {
.name = "shyway_clk",
.flags = CLK_ENABLE_ON_INIT,
.ops = &sh7757_shyway_clk_ops,
};
@@ -100,6 +100,13 @@ static struct clk *sh7757_onchip_clocks[] = {
&sh7757_shyway_clk,
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk),
};
static int __init sh7757_clk_init(void)
{
struct clk *clk = clk_get(NULL, "master_clk");
@@ -123,6 +130,8 @@ static int __init sh7757_clk_init(void)
clk_put(clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return 0;
}

12
arch/sh/kernel/cpu/sh4a/clock-sh7763.c
View File

@@ -12,6 +12,8 @@
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <asm/io.h>
@@ -77,7 +79,6 @@ static struct clk_ops sh7763_shyway_clk_ops = {
};
static struct clk sh7763_shyway_clk = {
.name = "shyway_clk",
.flags = CLK_ENABLE_ON_INIT,
.ops = &sh7763_shyway_clk_ops,
};
@@ -90,6 +91,13 @@ static struct clk *sh7763_onchip_clocks[] = {
&sh7763_shyway_clk,
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
};
int __init arch_clk_init(void)
{
struct clk *clk;
@@ -107,5 +115,7 @@ int __init arch_clk_init(void)
clk_put(clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return ret;
}

12
arch/sh/kernel/cpu/sh4a/clock-sh7780.c
View File

@@ -11,6 +11,8 @@
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <asm/io.h>
@@ -83,7 +85,6 @@ static struct clk_ops sh7780_shyway_clk_ops = {
};
static struct clk sh7780_shyway_clk = {
.name = "shyway_clk",
.flags = CLK_ENABLE_ON_INIT,
.ops = &sh7780_shyway_clk_ops,
};
@@ -96,6 +97,13 @@ static struct clk *sh7780_onchip_clocks[] = {
&sh7780_shyway_clk,
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk),
};
int __init arch_clk_init(void)
{
struct clk *clk;
@@ -113,5 +121,7 @@ int __init arch_clk_init(void)
clk_put(clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return ret;
}

176
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
View File

@@ -3,7 +3,7 @@
*
* SH7785 support for the clock framework
*
* Copyright (C) 2007 - 2009 Paul Mundt
* Copyright (C) 2007 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@@ -14,6 +14,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/cpufreq.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <cpu/sh7785.h>
@@ -23,8 +24,6 @@
* from the platform code.
*/
static struct clk extal_clk = {
.name = "extal",
.id = -1,
.rate = 33333333,
};
@@ -42,8 +41,6 @@ static struct clk_ops pll_clk_ops = {
};
static struct clk pll_clk = {
.name = "pll_clk",
.id = -1,
.ops = &pll_clk_ops,
.parent = &extal_clk,
.flags = CLK_ENABLE_ON_INIT,
@@ -69,48 +66,149 @@ static struct clk_div4_table div4_table = {
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
DIV4_DU, DIV4_P, DIV4_NR };
#define DIV4(_str, _bit, _mask, _flags) \
SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
#define DIV4(_bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
struct clk div4_clks[DIV4_NR] = {
[DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0),
[DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0),
[DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0),
[DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT),
[DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4(0, 0x0f80, 0),
[DIV4_DU] = DIV4(4, 0x0ff0, 0),
[DIV4_GA] = DIV4(8, 0x0030, 0),
[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
[DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
};
#define MSTPCR0 0xffc80030
#define MSTPCR1 0xffc80034
static struct clk mstp_clks[] = {
enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
MSTP021, MSTP020, MSTP017, MSTP016,
MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
/* MSTPCR0 */
SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0),
SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0),
SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0),
SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
[MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
/* MSTPCR1 */
SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
[MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
[MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
/* MSTP32 clocks */
{
/* SCIF5 */
.dev_id = "sh-sci.5",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP029],
}, {
/* SCIF4 */
.dev_id = "sh-sci.4",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP028],
}, {
/* SCIF3 */
.dev_id = "sh-sci.3",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP027],
}, {
/* SCIF2 */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP026],
}, {
/* SCIF1 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP025],
}, {
/* SCIF0 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP024],
},
CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
{
/* TMU0 */
.dev_id = "sh_tmu.0",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP008],
}, {
/* TMU1 */
.dev_id = "sh_tmu.1",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP008],
}, {
/* TMU2 */
.dev_id = "sh_tmu.2",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP008],
}, {
/* TMU3 */
.dev_id = "sh_tmu.3",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP009],
}, {
/* TMU4 */
.dev_id = "sh_tmu.4",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP009],
}, {
/* TMU5 */
.dev_id = "sh_tmu.5",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP009],
},
CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
};
int __init arch_clk_init(void)
@@ -119,12 +217,14 @@ int __init arch_clk_init(void)
for (i = 0; i < ARRAY_SIZE(clks); i++)
ret |= clk_register(clks[i]);
for (i = 0; i < ARRAY_SIZE(lookups); i++)
clkdev_add(&lookups[i]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
&div4_table);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
return ret;
}

223
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
View File

@@ -13,6 +13,8 @@
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/freq.h>
@@ -21,8 +23,6 @@
* from the platform code.
*/
static struct clk extal_clk = {
.name = "extal",
.id = -1,
.rate = 33333333,
};
@@ -44,8 +44,6 @@ static struct clk_ops pll_clk_ops = {
};
static struct clk pll_clk = {
.name = "pll_clk",
.id = -1,
.ops = &pll_clk_ops,
.parent = &extal_clk,
.flags = CLK_ENABLE_ON_INIT,
@@ -70,54 +68,191 @@ static struct clk_div4_table div4_table = {
enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
#define DIV4(_str, _bit, _mask, _flags) \
SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
#define DIV4(_bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
struct clk div4_clks[DIV4_NR] = {
[DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
[DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
[DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
[DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
[DIV4_P] = DIV4(0, 0x0b40, 0),
[DIV4_DU] = DIV4(4, 0x0010, 0),
[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
};
#define MSTPCR0 0xffc40030
#define MSTPCR1 0xffc40034
static struct clk mstp_clks[] = {
enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
MSTP005, MSTP004, MSTP002,
MSTP112, MSTP110, MSTP109, MSTP108,
MSTP105, MSTP104, MSTP103, MSTP102,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
/* MSTPCR0 */
SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
[MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
/* MSTPCR1 */
SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
[MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
[MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
[MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
[MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
[MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
[MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
/* MSTP32 clocks */
{
/* SCIF5 */
.dev_id = "sh-sci.5",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP029],
}, {
/* SCIF4 */
.dev_id = "sh-sci.4",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP028],
}, {
/* SCIF3 */
.dev_id = "sh-sci.3",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP027],
}, {
/* SCIF2 */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP026],
}, {
/* SCIF1 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP025],
}, {
/* SCIF0 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP024],
},
CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
{
/* TMU0 */
.dev_id = "sh_tmu.0",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP008],
}, {
/* TMU1 */
.dev_id = "sh_tmu.1",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP008],
}, {
/* TMU2 */
.dev_id = "sh_tmu.2",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP008],
}, {
/* TMU3 */
.dev_id = "sh_tmu.3",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP009],
}, {
/* TMU4 */
.dev_id = "sh_tmu.4",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP009],
}, {
/* TMU5 */
.dev_id = "sh_tmu.5",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP009],
}, {
/* TMU6 */
.dev_id = "sh_tmu.6",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP010],
}, {
/* TMU7 */
.dev_id = "sh_tmu.7",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP010],
}, {
/* TMU8 */
.dev_id = "sh_tmu.8",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP010],
}, {
/* TMU9 */
.dev_id = "sh_tmu.9",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP011],
}, {
/* TMU10 */
.dev_id = "sh_tmu.10",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP011],
}, {
/* TMU11 */
.dev_id = "sh_tmu.11",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP011],
},
CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
};
int __init arch_clk_init(void)
@@ -126,12 +261,14 @@ int __init arch_clk_init(void)
for (i = 0; i < ARRAY_SIZE(clks); i++)
ret |= clk_register(clks[i]);
for (i = 0; i < ARRAY_SIZE(lookups); i++)
clkdev_add(&lookups[i]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
&div4_table);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
return ret;
}

13
arch/sh/kernel/cpu/sh4a/clock-shx3.c
View File

@@ -13,9 +13,10 @@
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <asm/io.h>
static int ifc_divisors[] = { 1, 2, 4 ,6 };
static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
@@ -94,7 +95,6 @@ static struct clk_ops shx3_shyway_clk_ops = {
};
static struct clk shx3_shyway_clk = {
.name = "shyway_clk",
.flags = CLK_ENABLE_ON_INIT,
.ops = &shx3_shyway_clk_ops,
};
@@ -107,6 +107,13 @@ static struct clk *shx3_onchip_clocks[] = {
&shx3_shyway_clk,
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),
};
int __init arch_clk_init(void)
{
struct clk *clk;
@@ -124,5 +131,7 @@ int __init arch_clk_init(void)
clk_put(clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return ret;
}

16
arch/sh/kernel/cpu/sh4a/setup-sh7343.c
View File

@@ -21,7 +21,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 },
.clk = "scif0",
};
static struct platform_device scif0_device = {
@@ -37,7 +36,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 },
.clk = "scif1",
};
static struct platform_device scif1_device = {
@@ -53,7 +51,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 },
.clk = "scif2",
};
static struct platform_device scif2_device = {
@@ -69,7 +66,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 83, 83, 83, 83 },
.clk = "scif3",
};
static struct platform_device scif3_device = {
@@ -207,17 +203,14 @@ static struct platform_device jpu_device = {
};
static struct sh_timer_config cmt_platform_data = {
.name = "CMT",
.channel_offset = 0x60,
.timer_bit = 5,
.clk = "cmt0",
.clockevent_rating = 125,
.clocksource_rating = 200,
};
static struct resource cmt_resources[] = {
[0] = {
.name = "CMT",
.start = 0x044a0060,
.end = 0x044a006b,
.flags = IORESOURCE_MEM,
@@ -239,16 +232,13 @@ static struct platform_device cmt_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "tmu0",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -270,16 +260,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "tmu0",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -301,15 +288,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "tmu0",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002b,
.flags = IORESOURCE_MEM,

13
arch/sh/kernel/cpu/sh4a/setup-sh7366.c
View File

@@ -23,7 +23,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 },
.clk = "scif0",
};
static struct platform_device scif0_device = {
@@ -169,17 +168,14 @@ static struct platform_device veu1_device = {
};
static struct sh_timer_config cmt_platform_data = {
.name = "CMT",
.channel_offset = 0x60,
.timer_bit = 5,
.clk = "cmt0",
.clockevent_rating = 125,
.clocksource_rating = 200,
};
static struct resource cmt_resources[] = {
[0] = {
.name = "CMT",
.start = 0x044a0060,
.end = 0x044a006b,
.flags = IORESOURCE_MEM,
@@ -201,16 +197,13 @@ static struct platform_device cmt_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "tmu0",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -232,16 +225,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "tmu0",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -263,15 +253,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "tmu0",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002b,
.flags = IORESOURCE_MEM,

21
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
View File

@@ -24,7 +24,7 @@
#include <cpu/dma-register.h>
#include <cpu/sh7722.h>
static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
{
.slave_id = SHDMA_SLAVE_SCIF0_TX,
.addr = 0xffe0000c,
@@ -78,7 +78,7 @@ static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
},
};
static struct sh_dmae_channel sh7722_dmae_channels[] = {
static const struct sh_dmae_channel sh7722_dmae_channels[] = {
{
.offset = 0,
.dmars = 0,
@@ -106,7 +106,7 @@ static struct sh_dmae_channel sh7722_dmae_channels[] = {
}
};
static unsigned int ts_shift[] = TS_SHIFT;
static const unsigned int ts_shift[] = TS_SHIFT;
static struct sh_dmae_pdata dma_platform_data = {
.slave = sh7722_dmae_slaves,
@@ -174,7 +174,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 },
.clk = "scif0",
};
static struct platform_device scif0_device = {
@@ -190,7 +189,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 },
.clk = "scif1",
};
static struct platform_device scif1_device = {
@@ -206,7 +204,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 },
.clk = "scif2",
};
static struct platform_device scif2_device = {
@@ -401,17 +398,14 @@ static struct platform_device jpu_device = {
};
static struct sh_timer_config cmt_platform_data = {
.name = "CMT",
.channel_offset = 0x60,
.timer_bit = 5,
.clk = "cmt0",
.clockevent_rating = 125,
.clocksource_rating = 125,
};
static struct resource cmt_resources[] = {
[0] = {
.name = "CMT",
.start = 0x044a0060,
.end = 0x044a006b,
.flags = IORESOURCE_MEM,
@@ -436,16 +430,13 @@ static struct platform_device cmt_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "tmu0",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -470,16 +461,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "tmu0",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -504,15 +492,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "tmu0",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002b,
.flags = IORESOURCE_MEM,

27
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
View File

@@ -26,7 +26,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 },
.clk = "scif0",
};
static struct platform_device scif0_device = {
@@ -42,7 +41,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 },
.clk = "scif1",
};
static struct platform_device scif1_device = {
@@ -58,7 +56,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 },
.clk = "scif2",
};
static struct platform_device scif2_device = {
@@ -74,7 +71,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA,
.irqs = { 56, 56, 56, 56 },
.clk = "scif3",
};
static struct platform_device scif3_device = {
@@ -90,7 +86,6 @@ static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA,
.irqs = { 88, 88, 88, 88 },
.clk = "scif4",
};
static struct platform_device scif4_device = {
@@ -106,7 +101,6 @@ static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA,
.irqs = { 109, 109, 109, 109 },
.clk = "scif5",
};
static struct platform_device scif5_device = {
@@ -211,17 +205,14 @@ static struct platform_device veu1_device = {
};
static struct sh_timer_config cmt_platform_data = {
.name = "CMT",
.channel_offset = 0x60,
.timer_bit = 5,
.clk = "cmt0",
.clockevent_rating = 125,
.clocksource_rating = 125,
};
static struct resource cmt_resources[] = {
[0] = {
.name = "CMT",
.start = 0x044a0060,
.end = 0x044a006b,
.flags = IORESOURCE_MEM,
@@ -246,16 +237,13 @@ static struct platform_device cmt_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "tmu0",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -280,16 +268,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "tmu0",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -314,15 +299,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "tmu0",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002b,
.flags = IORESOURCE_MEM,
@@ -347,15 +329,12 @@ static struct platform_device tmu2_device = {
};
static struct sh_timer_config tmu3_platform_data = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "tmu1",
};
static struct resource tmu3_resources[] = {
[0] = {
.name = "TMU3",
.start = 0xffd90008,
.end = 0xffd90013,
.flags = IORESOURCE_MEM,
@@ -380,15 +359,12 @@ static struct platform_device tmu3_device = {
};
static struct sh_timer_config tmu4_platform_data = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "tmu1",
};
static struct resource tmu4_resources[] = {
[0] = {
.name = "TMU4",
.start = 0xffd90014,
.end = 0xffd9001f,
.flags = IORESOURCE_MEM,
@@ -413,15 +389,12 @@ static struct platform_device tmu4_device = {
};
static struct sh_timer_config tmu5_platform_data = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "tmu1",
};
static struct resource tmu5_resources[] = {
[0] = {
.name = "TMU5",
.start = 0xffd90020,
.end = 0xffd9002b,
.flags = IORESOURCE_MEM,

81
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
View File

@@ -31,7 +31,7 @@
#include <cpu/sh7724.h>
/* DMA */
static struct sh_dmae_channel sh7724_dmae0_channels[] = {
static const struct sh_dmae_channel sh7724_dmae_channels[] = {
{
.offset = 0,
.dmars = 0,
@@ -59,51 +59,11 @@ static struct sh_dmae_channel sh7724_dmae0_channels[] = {
}
};
static struct sh_dmae_channel sh7724_dmae1_channels[] = {
{
.offset = 0,
.dmars = 0,
.dmars_bit = 0,
}, {
.offset = 0x10,
.dmars = 0,
.dmars_bit = 8,
}, {
.offset = 0x20,
.dmars = 4,
.dmars_bit = 0,
}, {
.offset = 0x30,
.dmars = 4,
.dmars_bit = 8,
}, {
.offset = 0x50,
.dmars = 8,
.dmars_bit = 0,
}, {
.offset = 0x60,
.dmars = 8,
.dmars_bit = 8,
}
};
static const unsigned int ts_shift[] = TS_SHIFT;
static unsigned int ts_shift[] = TS_SHIFT;
static struct sh_dmae_pdata dma0_platform_data = {
.channel = sh7724_dmae0_channels,
.channel_num = ARRAY_SIZE(sh7724_dmae0_channels),
.ts_low_shift = CHCR_TS_LOW_SHIFT,
.ts_low_mask = CHCR_TS_LOW_MASK,
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
.ts_high_mask = CHCR_TS_HIGH_MASK,
.ts_shift = ts_shift,
.ts_shift_num = ARRAY_SIZE(ts_shift),
.dmaor_init = DMAOR_INIT,
};
static struct sh_dmae_pdata dma1_platform_data = {
.channel = sh7724_dmae1_channels,
.channel_num = ARRAY_SIZE(sh7724_dmae1_channels),
static struct sh_dmae_pdata dma_platform_data = {
.channel = sh7724_dmae_channels,
.channel_num = ARRAY_SIZE(sh7724_dmae_channels),
.ts_low_shift = CHCR_TS_LOW_SHIFT,
.ts_low_mask = CHCR_TS_LOW_MASK,
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
@@ -187,7 +147,7 @@ static struct platform_device dma0_device = {
.resource = sh7724_dmae0_resources,
.num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
.dev = {
.platform_data = &dma0_platform_data,
.platform_data = &dma_platform_data,
},
.archdata = {
.hwblk_id = HWBLK_DMAC0,
@@ -200,7 +160,7 @@ static struct platform_device dma1_device = {
.resource = sh7724_dmae1_resources,
.num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
.dev = {
.platform_data = &dma1_platform_data,
.platform_data = &dma_platform_data,
},
.archdata = {
.hwblk_id = HWBLK_DMAC1,
@@ -213,7 +173,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 },
.clk = "scif0",
};
static struct platform_device scif0_device = {
@@ -229,7 +188,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 },
.clk = "scif1",
};
static struct platform_device scif1_device = {
@@ -245,7 +203,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 },
.clk = "scif2",
};
static struct platform_device scif2_device = {
@@ -261,7 +218,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA,
.irqs = { 56, 56, 56, 56 },
.clk = "scif3",
};
static struct platform_device scif3_device = {
@@ -277,7 +233,6 @@ static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA,
.irqs = { 88, 88, 88, 88 },
.clk = "scif4",
};
static struct platform_device scif4_device = {
@@ -293,7 +248,6 @@ static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA,
.irqs = { 109, 109, 109, 109 },
.clk = "scif5",
};
static struct platform_device scif5_device = {
@@ -485,17 +439,14 @@ static struct platform_device veu1_device = {
};
static struct sh_timer_config cmt_platform_data = {
.name = "CMT",
.channel_offset = 0x60,
.timer_bit = 5,
.clk = "cmt0",
.clockevent_rating = 125,
.clocksource_rating = 200,
};
static struct resource cmt_resources[] = {
[0] = {
.name = "CMT",
.start = 0x044a0060,
.end = 0x044a006b,
.flags = IORESOURCE_MEM,
@@ -520,16 +471,13 @@ static struct platform_device cmt_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "tmu0",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -554,16 +502,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "tmu0",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -588,15 +533,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "tmu0",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002b,
.flags = IORESOURCE_MEM,
@@ -622,15 +564,12 @@ static struct platform_device tmu2_device = {
static struct sh_timer_config tmu3_platform_data = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "tmu1",
};
static struct resource tmu3_resources[] = {
[0] = {
.name = "TMU3",
.start = 0xffd90008,
.end = 0xffd90013,
.flags = IORESOURCE_MEM,
@@ -655,15 +594,12 @@ static struct platform_device tmu3_device = {
};
static struct sh_timer_config tmu4_platform_data = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "tmu1",
};
static struct resource tmu4_resources[] = {
[0] = {
.name = "TMU4",
.start = 0xffd90014,
.end = 0xffd9001f,
.flags = IORESOURCE_MEM,
@@ -688,15 +624,12 @@ static struct platform_device tmu4_device = {
};
static struct sh_timer_config tmu5_platform_data = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "tmu1",
};
static struct resource tmu5_resources[] = {
[0] = {
.name = "TMU5",
.start = 0xffd90020,
.end = 0xffd9002b,
.flags = IORESOURCE_MEM,

6
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
View File

@@ -63,16 +63,13 @@ static struct platform_device scif4_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xfe430008,
.end = 0xfe430013,
.flags = IORESOURCE_MEM,
@@ -94,16 +91,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xfe430014,
.end = 0xfe43001f,
.flags = IORESOURCE_MEM,

18
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
View File

@@ -131,16 +131,13 @@ static struct platform_device usbf_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -162,16 +159,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -193,15 +187,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002f,
.flags = IORESOURCE_MEM,
@@ -223,15 +214,12 @@ static struct platform_device tmu2_device = {
};
static struct sh_timer_config tmu3_platform_data = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
[0] = {
.name = "TMU3",
.start = 0xffd88008,
.end = 0xffd88013,
.flags = IORESOURCE_MEM,
@@ -253,15 +241,12 @@ static struct platform_device tmu3_device = {
};
static struct sh_timer_config tmu4_platform_data = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
[0] = {
.name = "TMU4",
.start = 0xffd88014,
.end = 0xffd8801f,
.flags = IORESOURCE_MEM,
@@ -283,15 +268,12 @@ static struct platform_device tmu4_device = {
};
static struct sh_timer_config tmu5_platform_data = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
[0] = {
.name = "TMU5",
.start = 0xffd88020,
.end = 0xffd8802b,
.flags = IORESOURCE_MEM,

27
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
View File

@@ -165,16 +165,13 @@ static struct platform_device scif9_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -196,16 +193,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -227,15 +221,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002f,
.flags = IORESOURCE_MEM,
@@ -257,15 +248,12 @@ static struct platform_device tmu2_device = {
};
static struct sh_timer_config tmu3_platform_data = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
[0] = {
.name = "TMU3",
.start = 0xffd81008,
.end = 0xffd81013,
.flags = IORESOURCE_MEM,
@@ -287,15 +275,12 @@ static struct platform_device tmu3_device = {
};
static struct sh_timer_config tmu4_platform_data = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
[0] = {
.name = "TMU4",
.start = 0xffd81014,
.end = 0xffd8101f,
.flags = IORESOURCE_MEM,
@@ -317,15 +302,12 @@ static struct platform_device tmu4_device = {
};
static struct sh_timer_config tmu5_platform_data = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
[0] = {
.name = "TMU5",
.start = 0xffd81020,
.end = 0xffd8102f,
.flags = IORESOURCE_MEM,
@@ -347,15 +329,12 @@ static struct platform_device tmu5_device = {
};
static struct sh_timer_config tmu6_platform_data = {
.name = "TMU6",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
};
static struct resource tmu6_resources[] = {
[0] = {
.name = "TMU6",
.start = 0xffd82008,
.end = 0xffd82013,
.flags = IORESOURCE_MEM,
@@ -377,15 +356,12 @@ static struct platform_device tmu6_device = {
};
static struct sh_timer_config tmu7_platform_data = {
.name = "TMU7",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource tmu7_resources[] = {
[0] = {
.name = "TMU7",
.start = 0xffd82014,
.end = 0xffd8201f,
.flags = IORESOURCE_MEM,
@@ -407,15 +383,12 @@ static struct platform_device tmu7_device = {
};
static struct sh_timer_config tmu8_platform_data = {
.name = "TMU8",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu8_resources[] = {
[0] = {
.name = "TMU8",
.start = 0xffd82020,
.end = 0xffd8202b,
.flags = IORESOURCE_MEM,

24
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
View File

@@ -49,16 +49,13 @@ static struct platform_device scif1_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -80,16 +77,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -111,15 +105,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002f,
.flags = IORESOURCE_MEM,
@@ -141,15 +132,12 @@ static struct platform_device tmu2_device = {
};
static struct sh_timer_config tmu3_platform_data = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
[0] = {
.name = "TMU3",
.start = 0xffdc0008,
.end = 0xffdc0013,
.flags = IORESOURCE_MEM,
@@ -171,15 +159,12 @@ static struct platform_device tmu3_device = {
};
static struct sh_timer_config tmu4_platform_data = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
[0] = {
.name = "TMU4",
.start = 0xffdc0014,
.end = 0xffdc001f,
.flags = IORESOURCE_MEM,
@@ -201,15 +186,12 @@ static struct platform_device tmu4_device = {
};
static struct sh_timer_config tmu5_platform_data = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
[0] = {
.name = "TMU5",
.start = 0xffdc0020,
.end = 0xffdc002b,
.flags = IORESOURCE_MEM,
@@ -251,7 +233,7 @@ static struct platform_device rtc_device = {
};
/* DMA */
static struct sh_dmae_channel sh7780_dmae0_channels[] = {
static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
{
.offset = 0,
.dmars = 0,
@@ -279,7 +261,7 @@ static struct sh_dmae_channel sh7780_dmae0_channels[] = {
}
};
static struct sh_dmae_channel sh7780_dmae1_channels[] = {
static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
{
.offset = 0,
}, {
@@ -295,7 +277,7 @@ static struct sh_dmae_channel sh7780_dmae1_channels[] = {
}
};
static unsigned int ts_shift[] = TS_SHIFT;
static const unsigned int ts_shift[] = TS_SHIFT;
static struct sh_dmae_pdata dma0_platform_data = {
.channel = sh7780_dmae0_channels,

30
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
View File

@@ -25,7 +25,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 40, 40, 40, 40 },
.clk = "scif_fck",
};
static struct platform_device scif0_device = {
@@ -41,7 +40,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 44, 44, 44, 44 },
.clk = "scif_fck",
};
static struct platform_device scif1_device = {
@@ -57,7 +55,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 60, 60, 60, 60 },
.clk = "scif_fck",
};
static struct platform_device scif2_device = {
@@ -73,7 +70,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 61, 61, 61, 61 },
.clk = "scif_fck",
};
static struct platform_device scif3_device = {
@@ -89,7 +85,6 @@ static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 62, 62, 62, 62 },
.clk = "scif_fck",
};
static struct platform_device scif4_device = {
@@ -105,7 +100,6 @@ static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 63, 63, 63, 63 },
.clk = "scif_fck",
};
static struct platform_device scif5_device = {
@@ -117,16 +111,13 @@ static struct platform_device scif5_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "tmu012_fck",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -148,16 +139,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "tmu012_fck",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -179,15 +167,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "tmu012_fck",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002f,
.flags = IORESOURCE_MEM,
@@ -209,15 +194,12 @@ static struct platform_device tmu2_device = {
};
static struct sh_timer_config tmu3_platform_data = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "tmu345_fck",
};
static struct resource tmu3_resources[] = {
[0] = {
.name = "TMU3",
.start = 0xffdc0008,
.end = 0xffdc0013,
.flags = IORESOURCE_MEM,
@@ -239,15 +221,12 @@ static struct platform_device tmu3_device = {
};
static struct sh_timer_config tmu4_platform_data = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "tmu345_fck",
};
static struct resource tmu4_resources[] = {
[0] = {
.name = "TMU4",
.start = 0xffdc0014,
.end = 0xffdc001f,
.flags = IORESOURCE_MEM,
@@ -269,15 +248,12 @@ static struct platform_device tmu4_device = {
};
static struct sh_timer_config tmu5_platform_data = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "tmu345_fck",
};
static struct resource tmu5_resources[] = {
[0] = {
.name = "TMU5",
.start = 0xffdc0020,
.end = 0xffdc002b,
.flags = IORESOURCE_MEM,
@@ -299,7 +275,7 @@ static struct platform_device tmu5_device = {
};
/* DMA */
static struct sh_dmae_channel sh7785_dmae0_channels[] = {
static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
{
.offset = 0,
.dmars = 0,
@@ -327,7 +303,7 @@ static struct sh_dmae_channel sh7785_dmae0_channels[] = {
}
};
static struct sh_dmae_channel sh7785_dmae1_channels[] = {
static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
{
.offset = 0,
}, {
@@ -343,7 +319,7 @@ static struct sh_dmae_channel sh7785_dmae1_channels[] = {
}
};
static unsigned int ts_shift[] = TS_SHIFT;
static const unsigned int ts_shift[] = TS_SHIFT;
static struct sh_dmae_pdata dma0_platform_data = {
.channel = sh7785_dmae0_channels,

157
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
View File

@@ -1,7 +1,7 @@
/*
* SH7786 Setup
*
* Copyright (C) 2009 Renesas Solutions Corp.
* Copyright (C) 2009 - 2010 Renesas Solutions Corp.
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
* Paul Mundt <paul.mundt@renesas.com>
*
@@ -21,7 +21,10 @@
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/sh_timer.h>
#include <linux/sh_intc.h>
#include <cpu/dma-register.h>
#include <asm/mmzone.h>
#include <asm/dmaengine.h>
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xffea0000,
@@ -117,16 +120,13 @@ static struct platform_device scif5_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffd80008,
.end = 0xffd80013,
.flags = IORESOURCE_MEM,
@@ -148,16 +148,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffd80014,
.end = 0xffd8001f,
.flags = IORESOURCE_MEM,
@@ -179,15 +176,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffd80020,
.end = 0xffd8002f,
.flags = IORESOURCE_MEM,
@@ -209,15 +203,12 @@ static struct platform_device tmu2_device = {
};
static struct sh_timer_config tmu3_platform_data = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
[0] = {
.name = "TMU3",
.start = 0xffda0008,
.end = 0xffda0013,
.flags = IORESOURCE_MEM,
@@ -239,15 +230,12 @@ static struct platform_device tmu3_device = {
};
static struct sh_timer_config tmu4_platform_data = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
[0] = {
.name = "TMU4",
.start = 0xffda0014,
.end = 0xffda001f,
.flags = IORESOURCE_MEM,
@@ -269,15 +257,12 @@ static struct platform_device tmu4_device = {
};
static struct sh_timer_config tmu5_platform_data = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
[0] = {
.name = "TMU5",
.start = 0xffda0020,
.end = 0xffda002b,
.flags = IORESOURCE_MEM,
@@ -299,15 +284,12 @@ static struct platform_device tmu5_device = {
};
static struct sh_timer_config tmu6_platform_data = {
.name = "TMU6",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
};
static struct resource tmu6_resources[] = {
[0] = {
.name = "TMU6",
.start = 0xffdc0008,
.end = 0xffdc0013,
.flags = IORESOURCE_MEM,
@@ -329,15 +311,12 @@ static struct platform_device tmu6_device = {
};
static struct sh_timer_config tmu7_platform_data = {
.name = "TMU7",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource tmu7_resources[] = {
[0] = {
.name = "TMU7",
.start = 0xffdc0014,
.end = 0xffdc001f,
.flags = IORESOURCE_MEM,
@@ -359,15 +338,12 @@ static struct platform_device tmu7_device = {
};
static struct sh_timer_config tmu8_platform_data = {
.name = "TMU8",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu8_resources[] = {
[0] = {
.name = "TMU8",
.start = 0xffdc0020,
.end = 0xffdc002b,
.flags = IORESOURCE_MEM,
@@ -389,15 +365,12 @@ static struct platform_device tmu8_device = {
};
static struct sh_timer_config tmu9_platform_data = {
.name = "TMU9",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
};
static struct resource tmu9_resources[] = {
[0] = {
.name = "TMU9",
.start = 0xffde0008,
.end = 0xffde0013,
.flags = IORESOURCE_MEM,
@@ -419,15 +392,12 @@ static struct platform_device tmu9_device = {
};
static struct sh_timer_config tmu10_platform_data = {
.name = "TMU10",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource tmu10_resources[] = {
[0] = {
.name = "TMU10",
.start = 0xffde0014,
.end = 0xffde001f,
.flags = IORESOURCE_MEM,
@@ -449,15 +419,12 @@ static struct platform_device tmu10_device = {
};
static struct sh_timer_config tmu11_platform_data = {
.name = "TMU11",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu11_resources[] = {
[0] = {
.name = "TMU11",
.start = 0xffde0020,
.end = 0xffde002b,
.flags = IORESOURCE_MEM,
@@ -478,6 +445,83 @@ static struct platform_device tmu11_device = {
.num_resources = ARRAY_SIZE(tmu11_resources),
};
static const struct sh_dmae_channel dmac0_channels[] = {
{
.offset = 0,
.dmars = 0,
.dmars_bit = 0,
}, {
.offset = 0x10,
.dmars = 0,
.dmars_bit = 8,
}, {
.offset = 0x20,
.dmars = 4,
.dmars_bit = 0,
}, {
.offset = 0x30,
.dmars = 4,
.dmars_bit = 8,
}, {
.offset = 0x50,
.dmars = 8,
.dmars_bit = 0,
}, {
.offset = 0x60,
.dmars = 8,
.dmars_bit = 8,
}
};
static const unsigned int ts_shift[] = TS_SHIFT;
static struct sh_dmae_pdata dma0_platform_data = {
.channel = dmac0_channels,
.channel_num = ARRAY_SIZE(dmac0_channels),
.ts_low_shift = CHCR_TS_LOW_SHIFT,
.ts_low_mask = CHCR_TS_LOW_MASK,
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
.ts_high_mask = CHCR_TS_HIGH_MASK,
.ts_shift = ts_shift,
.ts_shift_num = ARRAY_SIZE(ts_shift),
.dmaor_init = DMAOR_INIT,
};
/* Resource order important! */
static struct resource dmac0_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe008020,
.end = 0xfe00808f,
.flags = IORESOURCE_MEM,
}, {
/* DMARSx */
.start = 0xfe009000,
.end = 0xfe00900b,
.flags = IORESOURCE_MEM,
}, {
/* DMA error IRQ */
.start = evt2irq(0x5c0),
.end = evt2irq(0x5c0),
.flags = IORESOURCE_IRQ,
}, {
/* IRQ for channels 0-5 */
.start = evt2irq(0x500),
.end = evt2irq(0x5a0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dma0_device = {
.name = "sh-dma-engine",
.id = 0,
.resource = dmac0_resources,
.num_resources = ARRAY_SIZE(dmac0_resources),
.dev = {
.platform_data = &dma0_platform_data,
},
};
static struct resource usb_ohci_resources[] = {
[0] = {
.start = 0xffe70400,
@@ -525,10 +569,10 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
};
static struct platform_device *sh7786_devices[] __initdata = {
&dma0_device,
&usb_ohci_device,
};
/*
* Please call this function if your platform board
* use external clock for USB
@@ -536,6 +580,7 @@ static struct platform_device *sh7786_devices[] __initdata = {
#define USBCTL0 0xffe70858
#define CLOCK_MODE_MASK 0xffffff7f
#define EXT_CLOCK_MODE 0x00000080
void __init sh7786_usb_use_exclock(void)
{
u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
@@ -553,6 +598,7 @@ void __init sh7786_usb_use_exclock(void)
#define PLL_ENB 0x00000002
#define PHY_RST 0x00000004
#define ACT_PLL_STATUS 0xc0000000
static void __init sh7786_usb_setup(void)
{
int i = 1000000;
@@ -708,9 +754,19 @@ static struct intc_vect vectors[] __initdata = {
#define INTMSK2 0xfe410068
#define INTMSKCLR2 0xfe41006c
#define INTDISTCR0 0xfe4100b0
#define INTDISTCR1 0xfe4100b4
#define INTACK 0xfe4100b8
#define INTACKCLR 0xfe4100bc
#define INT2DISTCR0 0xfe410900
#define INT2DISTCR1 0xfe410904
#define INT2DISTCR2 0xfe410908
#define INT2DISTCR3 0xfe41090c
static struct intc_mask_reg mask_registers[] __initdata = {
{ CnINTMSK0, CnINTMSKCLR0, 32,
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
INTC_SMP_BALANCING(INTDISTCR0) },
{ INTMSK2, INTMSKCLR2, 32,
{ IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
@@ -722,7 +778,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
{ CnINT2MSKR0, CnINT2MSKCR0 , 32,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
INTC_SMP_BALANCING(INT2DISTCR0) },
{ CnINT2MSKR1, CnINT2MSKCR1, 32,
{ TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
@@ -731,14 +788,14 @@ static struct intc_mask_reg mask_registers[] __initdata = {
HPB_0, HPB_1, HPB_2,
SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
SCIF1,
TMU2, TMU3, 0, } },
TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
{ CnINT2MSKR2, CnINT2MSKCR2, 32,
{ 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
Eth_0, Eth_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PCIeC0_0, PCIeC0_1, PCIeC0_2,
PCIeC1_0, PCIeC1_1, PCIeC1_2,
USB, 0, 0 } },
USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
{ CnINT2MSKR3, CnINT2MSKCR3, 32,
{ 0, 0, 0, 0, 0, 0,
I2C0, I2C1,
@@ -747,7 +804,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
HAC0, HAC1,
FLCTL, 0,
HSPI, GPIO0, GPIO1, Thermal,
0, 0, 0, 0, 0, 0, 0, 0 } },
0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
};
static struct intc_prio_reg prio_registers[] __initdata = {
@@ -863,6 +920,19 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
#define INTC_INTMSK2 INTMSK2
#define INTC_INTMSKCLR1 CnINTMSKCLR1
#define INTC_INTMSKCLR2 INTMSKCLR2
#define INTC_USERIMASK 0xfe411000
#ifdef CONFIG_INTC_BALANCING
unsigned int irq_lookup(unsigned int irq)
{
return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
}
void irq_finish(unsigned int irq)
{
__raw_writel(irq2evt(irq), INTACKCLR);
}
#endif
void __init plat_irq_setup(void)
{
@@ -877,6 +947,7 @@ void __init plat_irq_setup(void)
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
register_intc_controller(&intc_desc);
register_intc_userimask(INTC_USERIMASK);
}
void __init plat_irq_setup_pins(int mode)

18
arch/sh/kernel/cpu/sh4a/setup-shx3.c
View File

@@ -70,16 +70,13 @@ static struct platform_device scif2_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xffc10008,
.end = 0xffc10013,
.flags = IORESOURCE_MEM,
@@ -101,16 +98,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xffc10014,
.end = 0xffc1001f,
.flags = IORESOURCE_MEM,
@@ -132,15 +126,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xffc10020,
.end = 0xffc1002f,
.flags = IORESOURCE_MEM,
@@ -162,15 +153,12 @@ static struct platform_device tmu2_device = {
};
static struct sh_timer_config tmu3_platform_data = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
[0] = {
.name = "TMU3",
.start = 0xffc20008,
.end = 0xffc20013,
.flags = IORESOURCE_MEM,
@@ -192,15 +180,12 @@ static struct platform_device tmu3_device = {
};
static struct sh_timer_config tmu4_platform_data = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
[0] = {
.name = "TMU4",
.start = 0xffc20014,
.end = 0xffc2001f,
.flags = IORESOURCE_MEM,
@@ -222,15 +207,12 @@ static struct platform_device tmu4_device = {
};
static struct sh_timer_config tmu5_platform_data = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
[0] = {
.name = "TMU5",
.start = 0xffc20020,
.end = 0xffc2002b,
.flags = IORESOURCE_MEM,

74
arch/sh/kernel/cpu/sh4a/smp-shx3.c
View File

@@ -1,7 +1,7 @@
/*
* SH-X3 SMP
*
* Copyright (C) 2007 - 2008 Paul Mundt
* Copyright (C) 2007 - 2010 Paul Mundt
* Copyright (C) 2007 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
@@ -9,16 +9,22 @@
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/cpumask.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/cpu.h>
#include <asm/sections.h>
#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
#define STBCR_MSTP 0x00000001
#define STBCR_RESET 0x00000002
#define STBCR_SLEEP 0x00000004
#define STBCR_LTSLP 0x80000000
static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
@@ -37,7 +43,7 @@ static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
return IRQ_HANDLED;
}
void __init plat_smp_setup(void)
static void shx3_smp_setup(void)
{
unsigned int cpu = 0;
int i, num;
@@ -63,7 +69,7 @@ void __init plat_smp_setup(void)
printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
}
void __init plat_prepare_cpus(unsigned int max_cpus)
static void shx3_prepare_cpus(unsigned int max_cpus)
{
int i;
@@ -72,11 +78,14 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
BUILD_BUG_ON(SMP_MSG_NR >= 8);
for (i = 0; i < SMP_MSG_NR; i++)
request_irq(104 + i, ipi_interrupt_handler, IRQF_DISABLED,
"IPI", (void *)(long)i);
request_irq(104 + i, ipi_interrupt_handler,
IRQF_DISABLED | IRQF_PERCPU, "IPI", (void *)(long)i);
for (i = 0; i < max_cpus; i++)
set_cpu_present(i, true);
}
void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
static void shx3_start_cpu(unsigned int cpu, unsigned long entry_point)
{
if (__in_29bit_mode())
__raw_writel(entry_point, RESET_REG(cpu));
@@ -93,12 +102,12 @@ void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
__raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
}
int plat_smp_processor_id(void)
static unsigned int shx3_smp_processor_id(void)
{
return __raw_readl(0xff000048); /* CPIDR */
}
void plat_send_ipi(unsigned int cpu, unsigned int message)
static void shx3_send_ipi(unsigned int cpu, unsigned int message)
{
unsigned long addr = 0xfe410070 + (cpu * 4);
@@ -106,3 +115,52 @@ void plat_send_ipi(unsigned int cpu, unsigned int message)
__raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
}
static void shx3_update_boot_vector(unsigned int cpu)
{
__raw_writel(STBCR_MSTP, STBCR_REG(cpu));
while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
cpu_relax();
__raw_writel(STBCR_RESET, STBCR_REG(cpu));
}
static int __cpuinit
shx3_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned int)hcpu;
switch (action) {
case CPU_UP_PREPARE:
shx3_update_boot_vector(cpu);
break;
case CPU_ONLINE:
pr_info("CPU %u is now online\n", cpu);
break;
case CPU_DEAD:
break;
}
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata shx3_cpu_notifier = {
.notifier_call = shx3_cpu_callback,
};
static int __cpuinit register_shx3_cpu_notifier(void)
{
register_hotcpu_notifier(&shx3_cpu_notifier);
return 0;
}
late_initcall(register_shx3_cpu_notifier);
struct plat_smp_ops shx3_smp_ops = {
.smp_setup = shx3_smp_setup,
.prepare_cpus = shx3_prepare_cpus,
.start_cpu = shx3_start_cpu,
.smp_processor_id = shx3_smp_processor_id,
.send_ipi = shx3_send_ipi,
.cpu_die = native_cpu_die,
.cpu_disable = native_cpu_disable,
.play_dead = native_play_dead,
};

4
arch/sh/kernel/cpu/sh5/probe.c
View File

@@ -17,7 +17,7 @@
#include <asm/cache.h>
#include <asm/tlb.h>
int __init detect_cpu_and_cache_system(void)
void __cpuinit cpu_probe(void)
{
unsigned long long cir;
@@ -72,6 +72,4 @@ int __init detect_cpu_and_cache_system(void)
/* Setup some I/D TLB defaults */
sh64_tlb_init();
return 0;
}

9
arch/sh/kernel/cpu/sh5/setup-sh5.c
View File

@@ -68,16 +68,13 @@ static struct platform_device rtc_device = {
#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = TMU0_BASE,
.end = TMU0_BASE + 0xc - 1,
.flags = IORESOURCE_MEM,
@@ -99,16 +96,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = TMU1_BASE,
.end = TMU1_BASE + 0xc - 1,
.flags = IORESOURCE_MEM,
@@ -130,15 +124,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = TMU2_BASE,
.end = TMU2_BASE + 0xc - 1,
.flags = IORESOURCE_MEM,

20
arch/sh/kernel/crash_dump.c
View File

@@ -4,7 +4,6 @@
* Created by: Hariprasad Nellitheertha (hari@in.ibm.com)
* Copyright (C) IBM Corporation, 2004. All rights reserved
*/
#include <linux/errno.h>
#include <linux/crash_dump.h>
#include <linux/io.h>
@@ -13,6 +12,25 @@
/* Stores the physical address of elf header of crash image. */
unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
/*
* Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
* is_kdump_kernel() to determine if we are booting after a panic. Hence
* ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
*
* elfcorehdr= specifies the location of elf core header
* stored by the crashed kernel.
*/
static int __init parse_elfcorehdr(char *arg)
{
if (!arg)
return -EINVAL;
elfcorehdr_addr = memparse(arg, &arg);
return 0;
}
early_param("elfcorehdr", parse_elfcorehdr);
/**
* copy_oldmem_page - copy one page from "oldmem"
* @pfn: page frame number to be copied

1
arch/sh/kernel/dwarf.c
View File

@@ -22,6 +22,7 @@
#include <linux/mm.h>
#include <linux/elf.h>
#include <linux/ftrace.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <asm/dwarf.h>
#include <asm/unwinder.h>

7
arch/sh/kernel/head_32.S
View File

@@ -131,6 +131,7 @@ ENTRY(_stext)
* r8 = scratch register
* r9 = scratch register
* r10 = number of PMB entries we've setup
* r11 = scratch register
*/
mov.l .LMMUCR, r1 /* Flush the TLB */
@@ -167,8 +168,9 @@ ENTRY(_stext)
.Lvalidate_existing_mappings:
mov.l .LPMB_DATA_MASK, r11
mov.l @r7, r8
and r0, r8
and r11, r8
cmp/eq r0, r8 /* Check for valid __MEMORY_START mappings */
bt .Lpmb_done
@@ -335,12 +337,13 @@ ENTRY(stack_start)
3: .long __bss_start
4: .long _end
5: .long start_kernel
6: .long sh_cpu_init
6: .long cpu_init
7: .long init_thread_union
#ifdef CONFIG_PMB
.LPMB_ADDR: .long PMB_ADDR
.LPMB_DATA: .long PMB_DATA
.LPMB_DATA_MASK: .long PMB_PFN_MASK | PMB_V
.LFIRST_ADDR_ENTRY: .long PAGE_OFFSET | PMB_V
.LFIRST_DATA_ENTRY: .long __MEMORY_START | PMB_V
.LMMUCR: .long MMUCR

5
arch/sh/kernel/hw_breakpoint.c
View File

@@ -405,11 +405,6 @@ void hw_breakpoint_pmu_read(struct perf_event *bp)
/* TODO */
}
void hw_breakpoint_pmu_unthrottle(struct perf_event *bp)
{
/* TODO */
}
int register_sh_ubc(struct sh_ubc *ubc)
{
/* Bail if it's already assigned */

8
arch/sh/kernel/idle.c
View File

@@ -19,6 +19,7 @@
#include <asm/pgalloc.h>
#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/smp.h>
void (*pm_idle)(void) = NULL;
@@ -89,10 +90,13 @@ void cpu_idle(void)
while (1) {
tick_nohz_stop_sched_tick(1);
while (!need_resched() && cpu_online(cpu)) {
while (!need_resched()) {
check_pgt_cache();
rmb();
if (cpu_is_offline(cpu))
play_dead();
local_irq_disable();
/* Don't trace irqs off for idle */
stop_critical_timings();
@@ -133,7 +137,7 @@ static void do_nothing(void *unused)
void stop_this_cpu(void *unused)
{
local_irq_disable();
cpu_clear(smp_processor_id(), cpu_online_map);
set_cpu_online(smp_processor_id(), false);
for (;;)
cpu_sleep();

91
arch/sh/kernel/irq.c
View File

@@ -12,6 +12,7 @@
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/ftrace.h>
#include <linux/delay.h>
#include <asm/processor.h>
#include <asm/machvec.h>
#include <asm/uaccess.h>
@@ -113,19 +114,14 @@ union irq_ctx {
static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
#endif
asmlinkage __irq_entry int do_IRQ(unsigned int irq, struct pt_regs *regs)
static char softirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;
static char hardirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;
static inline void handle_one_irq(unsigned int irq)
{
struct pt_regs *old_regs = set_irq_regs(regs);
#ifdef CONFIG_IRQSTACKS
union irq_ctx *curctx, *irqctx;
#endif
irq_enter();
irq = irq_demux(irq);
#ifdef CONFIG_IRQSTACKS
curctx = (union irq_ctx *)current_thread_info();
irqctx = hardirq_ctx[smp_processor_id()];
@@ -164,20 +160,9 @@ asmlinkage __irq_entry int do_IRQ(unsigned int irq, struct pt_regs *regs)
"r5", "r6", "r7", "r8", "t", "pr"
);
} else
#endif
generic_handle_irq(irq);
irq_exit();
set_irq_regs(old_regs);
return 1;
}
#ifdef CONFIG_IRQSTACKS
static char softirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;
static char hardirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;
/*
* allocate per-cpu stacks for hardirq and for softirq processing
*/
@@ -257,8 +242,33 @@ asmlinkage void do_softirq(void)
local_irq_restore(flags);
}
#else
static inline void handle_one_irq(unsigned int irq)
{
generic_handle_irq(irq);
}
#endif
asmlinkage __irq_entry int do_IRQ(unsigned int irq, struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
irq_enter();
irq = irq_demux(irq_lookup(irq));
if (irq != NO_IRQ_IGNORE) {
handle_one_irq(irq);
irq_finish(irq);
}
irq_exit();
set_irq_regs(old_regs);
return IRQ_HANDLED;
}
void __init init_IRQ(void)
{
plat_irq_setup();
@@ -283,3 +293,44 @@ int __init arch_probe_nr_irqs(void)
return 0;
}
#endif
#ifdef CONFIG_HOTPLUG_CPU
static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
{
printk(KERN_INFO "IRQ%u: moving from cpu%u to cpu%u\n",
irq, desc->node, cpu);
raw_spin_lock_irq(&desc->lock);
desc->chip->set_affinity(irq, cpumask_of(cpu));
raw_spin_unlock_irq(&desc->lock);
}
/*
* The CPU has been marked offline. Migrate IRQs off this CPU. If
* the affinity settings do not allow other CPUs, force them onto any
* available CPU.
*/
void migrate_irqs(void)
{
struct irq_desc *desc;
unsigned int irq, cpu = smp_processor_id();
for_each_irq_desc(irq, desc) {
if (desc->node == cpu) {
unsigned int newcpu = cpumask_any_and(desc->affinity,
cpu_online_mask);
if (newcpu >= nr_cpu_ids) {
if (printk_ratelimit())
printk(KERN_INFO "IRQ%u no longer affine to CPU%u\n",
irq, cpu);
cpumask_setall(desc->affinity);
newcpu = cpumask_any_and(desc->affinity,
cpu_online_mask);
}
route_irq(desc, irq, newcpu);
}
}
}
#endif

6
arch/sh/kernel/localtimer.c
View File

@@ -44,7 +44,7 @@ static void dummy_timer_set_mode(enum clock_event_mode mode,
{
}
void __cpuinit local_timer_setup(unsigned int cpu)
void local_timer_setup(unsigned int cpu)
{
struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
@@ -60,3 +60,7 @@ void __cpuinit local_timer_setup(unsigned int cpu)
clockevents_register_device(clk);
}
void local_timer_stop(unsigned int cpu)
{
}

62
arch/sh/kernel/machine_kexec.c
View File

@@ -8,7 +8,6 @@
* This source code is licensed under the GNU General Public License,
* Version 2. See the file COPYING for more details.
*/
#include <linux/mm.h>
#include <linux/kexec.h>
#include <linux/delay.h>
@@ -16,6 +15,7 @@
#include <linux/numa.h>
#include <linux/ftrace.h>
#include <linux/suspend.h>
#include <linux/lmb.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/mmu_context.h>
@@ -147,4 +147,64 @@ void arch_crash_save_vmcoreinfo(void)
VMCOREINFO_SYMBOL(node_data);
VMCOREINFO_LENGTH(node_data, MAX_NUMNODES);
#endif
#ifdef CONFIG_X2TLB
VMCOREINFO_CONFIG(X2TLB);
#endif
}
void __init reserve_crashkernel(void)
{
unsigned long long crash_size, crash_base;
int ret;
/* this is necessary because of lmb_phys_mem_size() */
lmb_analyze();
ret = parse_crashkernel(boot_command_line, lmb_phys_mem_size(),
&crash_size, &crash_base);
if (ret == 0 && crash_size > 0) {
crashk_res.start = crash_base;
crashk_res.end = crash_base + crash_size - 1;
}
if (crashk_res.end == crashk_res.start)
goto disable;
crash_size = PAGE_ALIGN(crashk_res.end - crashk_res.start + 1);
if (!crashk_res.start) {
unsigned long max = lmb_end_of_DRAM() - memory_limit;
crashk_res.start = __lmb_alloc_base(crash_size, PAGE_SIZE, max);
if (!crashk_res.start) {
pr_err("crashkernel allocation failed\n");
goto disable;
}
} else {
ret = lmb_reserve(crashk_res.start, crash_size);
if (unlikely(ret < 0)) {
pr_err("crashkernel reservation failed - "
"memory is in use\n");
goto disable;
}
}
crashk_res.end = crashk_res.start + crash_size - 1;
/*
* Crash kernel trumps memory limit
*/
if ((lmb_end_of_DRAM() - memory_limit) <= crashk_res.end) {
memory_limit = 0;
pr_info("Disabled memory limit for crashkernel\n");
}
pr_info("Reserving %ldMB of memory at 0x%08lx "
"for crashkernel (System RAM: %ldMB)\n",
(unsigned long)(crash_size >> 20),
(unsigned long)(crashk_res.start),
(unsigned long)(lmb_phys_mem_size() >> 20));
return;
disable:
crashk_res.start = crashk_res.end = 0;
}

1
arch/sh/kernel/machvec.c
View File

@@ -131,6 +131,7 @@ void __init sh_mv_setup(void)
mv_set(ioport_unmap);
mv_set(irq_demux);
mv_set(mode_pins);
mv_set(mem_init);
if (!sh_mv.mv_nr_irqs)
sh_mv.mv_nr_irqs = NR_IRQS;

2
arch/sh/kernel/process.c
View File

@@ -90,7 +90,7 @@ void arch_task_cache_init(void)
# define HAVE_SOFTFP 0
#endif
void init_thread_xstate(void)
void __cpuinit init_thread_xstate(void)
{
if (boot_cpu_data.flags & CPU_HAS_FPU)
xstate_size = sizeof(struct sh_fpu_hard_struct);

308
arch/sh/kernel/setup.c
View File

@@ -4,7 +4,7 @@
* This file handles the architecture-dependent parts of initialization
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2002 - 2007 Paul Mundt
* Copyright (C) 2002 - 2010 Paul Mundt
*/
#include <linux/screen_info.h>
#include <linux/ioport.h>
@@ -39,7 +39,9 @@
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/clock.h>
#include <asm/smp.h>
#include <asm/mmu_context.h>
#include <asm/mmzone.h>
/*
* Initialize loops_per_jiffy as 10000000 (1000MIPS).
@@ -93,6 +95,7 @@ unsigned long memory_start;
EXPORT_SYMBOL(memory_start);
unsigned long memory_end = 0;
EXPORT_SYMBOL(memory_end);
unsigned long memory_limit = 0;
static struct resource mem_resources[MAX_NUMNODES];
@@ -100,92 +103,73 @@ int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
static int __init early_parse_mem(char *p)
{
unsigned long size;
if (!p)
return 1;
memory_start = (unsigned long)__va(__MEMORY_START);
size = memparse(p, &p);
memory_limit = PAGE_ALIGN(memparse(p, &p));
if (size > __MEMORY_SIZE) {
printk(KERN_ERR
"Using mem= to increase the size of kernel memory "
"is not allowed.\n"
" Recompile the kernel with the correct value for "
"CONFIG_MEMORY_SIZE.\n");
return 0;
}
memory_end = memory_start + size;
pr_notice("Memory limited to %ldMB\n", memory_limit >> 20);
return 0;
}
early_param("mem", early_parse_mem);
/*
* Register fully available low RAM pages with the bootmem allocator.
*/
static void __init register_bootmem_low_pages(void)
void __init check_for_initrd(void)
{
unsigned long curr_pfn, last_pfn, pages;
#ifdef CONFIG_BLK_DEV_INITRD
unsigned long start, end;
/*
* We are rounding up the start address of usable memory:
* Check for the rare cases where boot loaders adhere to the boot
* ABI.
*/
curr_pfn = PFN_UP(__MEMORY_START);
if (!LOADER_TYPE || !INITRD_START || !INITRD_SIZE)
goto disable;
/*
* ... and at the end of the usable range downwards:
*/
last_pfn = PFN_DOWN(__pa(memory_end));
start = INITRD_START + __MEMORY_START;
end = start + INITRD_SIZE;
if (last_pfn > max_low_pfn)
last_pfn = max_low_pfn;
pages = last_pfn - curr_pfn;
free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(pages));
}
#ifdef CONFIG_KEXEC
static void __init reserve_crashkernel(void)
{
unsigned long long free_mem;
unsigned long long crash_size, crash_base;
void *vp;
int ret;
free_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
ret = parse_crashkernel(boot_command_line, free_mem,
&crash_size, &crash_base);
if (ret == 0 && crash_size) {
if (crash_base <= 0) {
vp = alloc_bootmem_nopanic(crash_size);
if (!vp) {
printk(KERN_INFO "crashkernel allocation "
"failed\n");
return;
}
crash_base = __pa(vp);
} else if (reserve_bootmem(crash_base, crash_size,
BOOTMEM_EXCLUSIVE) < 0) {
printk(KERN_INFO "crashkernel reservation failed - "
"memory is in use\n");
return;
}
printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
"for crashkernel (System RAM: %ldMB)\n",
(unsigned long)(crash_size >> 20),
(unsigned long)(crash_base >> 20),
(unsigned long)(free_mem >> 20));
crashk_res.start = crash_base;
crashk_res.end = crash_base + crash_size - 1;
insert_resource(&iomem_resource, &crashk_res);
if (unlikely(end <= start))
goto disable;
if (unlikely(start & ~PAGE_MASK)) {
pr_err("initrd must be page aligned\n");
goto disable;
}
}
#else
static inline void __init reserve_crashkernel(void)
{}
if (unlikely(start < PAGE_OFFSET)) {
pr_err("initrd start < PAGE_OFFSET\n");
goto disable;
}
if (unlikely(end > lmb_end_of_DRAM())) {
pr_err("initrd extends beyond end of memory "
"(0x%08lx > 0x%08lx)\ndisabling initrd\n",
end, (unsigned long)lmb_end_of_DRAM());
goto disable;
}
/*
* If we got this far inspite of the boot loader's best efforts
* to the contrary, assume we actually have a valid initrd and
* fix up the root dev.
*/
ROOT_DEV = Root_RAM0;
/*
* Address sanitization
*/
initrd_start = (unsigned long)__va(__pa(start));
initrd_end = initrd_start + INITRD_SIZE;
lmb_reserve(__pa(initrd_start), INITRD_SIZE);
return;
disable:
pr_info("initrd disabled\n");
initrd_start = initrd_end = 0;
#endif
}
void __cpuinit calibrate_delay(void)
{
@@ -207,13 +191,18 @@ void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
unsigned long end_pfn)
{
struct resource *res = &mem_resources[nid];
unsigned long start, end;
WARN_ON(res->name); /* max one active range per node for now */
start = start_pfn << PAGE_SHIFT;
end = end_pfn << PAGE_SHIFT;
res->name = "System RAM";
res->start = start_pfn << PAGE_SHIFT;
res->end = (end_pfn << PAGE_SHIFT) - 1;
res->start = start;
res->end = end - 1;
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
if (request_resource(&iomem_resource, res)) {
pr_err("unable to request memory_resource 0x%lx 0x%lx\n",
start_pfn, end_pfn);
@@ -229,138 +218,18 @@ void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
request_resource(res, &data_resource);
request_resource(res, &bss_resource);
/*
* Also make sure that there is a PMB mapping that covers this
* range before we attempt to activate it, to avoid reset by MMU.
* We can hit this path with NUMA or memory hot-add.
*/
pmb_bolt_mapping((unsigned long)__va(start), start, end - start,
PAGE_KERNEL);
add_active_range(nid, start_pfn, end_pfn);
}
void __init setup_bootmem_allocator(unsigned long free_pfn)
{
unsigned long bootmap_size;
unsigned long bootmap_pages, bootmem_paddr;
u64 total_pages = (lmb_end_of_DRAM() - __MEMORY_START) >> PAGE_SHIFT;
int i;
bootmap_pages = bootmem_bootmap_pages(total_pages);
bootmem_paddr = lmb_alloc(bootmap_pages << PAGE_SHIFT, PAGE_SIZE);
/*
* Find a proper area for the bootmem bitmap. After this
* bootstrap step all allocations (until the page allocator
* is intact) must be done via bootmem_alloc().
*/
bootmap_size = init_bootmem_node(NODE_DATA(0),
bootmem_paddr >> PAGE_SHIFT,
min_low_pfn, max_low_pfn);
/* Add active regions with valid PFNs. */
for (i = 0; i < lmb.memory.cnt; i++) {
unsigned long start_pfn, end_pfn;
start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
__add_active_range(0, start_pfn, end_pfn);
}
/*
* Add all physical memory to the bootmem map and mark each
* area as present.
*/
register_bootmem_low_pages();
/* Reserve the sections we're already using. */
for (i = 0; i < lmb.reserved.cnt; i++)
reserve_bootmem(lmb.reserved.region[i].base,
lmb_size_bytes(&lmb.reserved, i),
BOOTMEM_DEFAULT);
node_set_online(0);
sparse_memory_present_with_active_regions(0);
#ifdef CONFIG_BLK_DEV_INITRD
ROOT_DEV = Root_RAM0;
if (LOADER_TYPE && INITRD_START) {
unsigned long initrd_start_phys = INITRD_START + __MEMORY_START;
if (initrd_start_phys + INITRD_SIZE <= PFN_PHYS(max_low_pfn)) {
reserve_bootmem(initrd_start_phys, INITRD_SIZE,
BOOTMEM_DEFAULT);
initrd_start = (unsigned long)__va(initrd_start_phys);
initrd_end = initrd_start + INITRD_SIZE;
} else {
printk("initrd extends beyond end of memory "
"(0x%08lx > 0x%08lx)\ndisabling initrd\n",
initrd_start_phys + INITRD_SIZE,
(unsigned long)PFN_PHYS(max_low_pfn));
initrd_start = 0;
}
}
#endif
reserve_crashkernel();
}
#ifndef CONFIG_NEED_MULTIPLE_NODES
static void __init setup_memory(void)
{
unsigned long start_pfn;
u64 base = min_low_pfn << PAGE_SHIFT;
u64 size = (max_low_pfn << PAGE_SHIFT) - base;
/*
* Partially used pages are not usable - thus
* we are rounding upwards:
*/
start_pfn = PFN_UP(__pa(_end));
lmb_add(base, size);
/*
* Reserve the kernel text and
* Reserve the bootmem bitmap. We do this in two steps (first step
* was init_bootmem()), because this catches the (definitely buggy)
* case of us accidentally initializing the bootmem allocator with
* an invalid RAM area.
*/
lmb_reserve(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET,
(PFN_PHYS(start_pfn) + PAGE_SIZE - 1) -
(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET));
/*
* Reserve physical pages below CONFIG_ZERO_PAGE_OFFSET.
*/
if (CONFIG_ZERO_PAGE_OFFSET != 0)
lmb_reserve(__MEMORY_START, CONFIG_ZERO_PAGE_OFFSET);
lmb_analyze();
lmb_dump_all();
setup_bootmem_allocator(start_pfn);
}
#else
extern void __init setup_memory(void);
#endif
/*
* Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
* is_kdump_kernel() to determine if we are booting after a panic. Hence
* ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
*/
#ifdef CONFIG_CRASH_DUMP
/* elfcorehdr= specifies the location of elf core header
* stored by the crashed kernel.
*/
static int __init parse_elfcorehdr(char *arg)
{
if (!arg)
return -EINVAL;
elfcorehdr_addr = memparse(arg, &arg);
return 0;
}
early_param("elfcorehdr", parse_elfcorehdr);
#endif
void __init __attribute__ ((weak)) plat_early_device_setup(void)
void __init __weak plat_early_device_setup(void)
{
}
@@ -401,10 +270,6 @@ void __init setup_arch(char **cmdline_p)
bss_resource.start = virt_to_phys(__bss_start);
bss_resource.end = virt_to_phys(_ebss)-1;
memory_start = (unsigned long)__va(__MEMORY_START);
if (!memory_end)
memory_end = memory_start + __MEMORY_SIZE;
#ifdef CONFIG_CMDLINE_OVERWRITE
strlcpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
#else
@@ -421,47 +286,24 @@ void __init setup_arch(char **cmdline_p)
parse_early_param();
uncached_init();
plat_early_device_setup();
sh_mv_setup();
/* Let earlyprintk output early console messages */
early_platform_driver_probe("earlyprintk", 1, 1);
sh_mv_setup();
/*
* Find the highest page frame number we have available
*/
max_pfn = PFN_DOWN(__pa(memory_end));
/*
* Determine low and high memory ranges:
*/
max_low_pfn = max_pfn;
min_low_pfn = __MEMORY_START >> PAGE_SHIFT;
nodes_clear(node_online_map);
pmb_init();
lmb_init();
setup_memory();
sparse_init();
paging_init();
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
paging_init();
ioremap_fixed_init();
/* Perform the machine specific initialisation */
if (likely(sh_mv.mv_setup))
sh_mv.mv_setup(cmdline_p);
#ifdef CONFIG_SMP
plat_smp_setup();
#endif
}
/* processor boot mode configuration */

160
arch/sh/kernel/smp.c
View File

@@ -3,7 +3,7 @@
*
* SMP support for the SuperH processors.
*
* Copyright (C) 2002 - 2008 Paul Mundt
* Copyright (C) 2002 - 2010 Paul Mundt
* Copyright (C) 2006 - 2007 Akio Idehara
*
* This file is subject to the terms and conditions of the GNU General Public
@@ -31,7 +31,20 @@
int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
static inline void __init smp_store_cpu_info(unsigned int cpu)
struct plat_smp_ops *mp_ops = NULL;
/* State of each CPU */
DEFINE_PER_CPU(int, cpu_state) = { 0 };
void __cpuinit register_smp_ops(struct plat_smp_ops *ops)
{
if (mp_ops)
printk(KERN_WARNING "Overriding previously set SMP ops\n");
mp_ops = ops;
}
static inline void __cpuinit smp_store_cpu_info(unsigned int cpu)
{
struct sh_cpuinfo *c = cpu_data + cpu;
@@ -46,14 +59,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
init_new_context(current, &init_mm);
current_thread_info()->cpu = cpu;
plat_prepare_cpus(max_cpus);
mp_ops->prepare_cpus(max_cpus);
#ifndef CONFIG_HOTPLUG_CPU
init_cpu_present(&cpu_possible_map);
#endif
}
void __devinit smp_prepare_boot_cpu(void)
void __init smp_prepare_boot_cpu(void)
{
unsigned int cpu = smp_processor_id();
@@ -62,37 +75,137 @@ void __devinit smp_prepare_boot_cpu(void)
set_cpu_online(cpu, true);
set_cpu_possible(cpu, true);
per_cpu(cpu_state, cpu) = CPU_ONLINE;
}
#ifdef CONFIG_HOTPLUG_CPU
void native_cpu_die(unsigned int cpu)
{
unsigned int i;
for (i = 0; i < 10; i++) {
smp_rmb();
if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
if (system_state == SYSTEM_RUNNING)
pr_info("CPU %u is now offline\n", cpu);
return;
}
msleep(100);
}
pr_err("CPU %u didn't die...\n", cpu);
}
int native_cpu_disable(unsigned int cpu)
{
return cpu == 0 ? -EPERM : 0;
}
void play_dead_common(void)
{
idle_task_exit();
irq_ctx_exit(raw_smp_processor_id());
mb();
__get_cpu_var(cpu_state) = CPU_DEAD;
local_irq_disable();
}
void native_play_dead(void)
{
play_dead_common();
}
int __cpu_disable(void)
{
unsigned int cpu = smp_processor_id();
struct task_struct *p;
int ret;
ret = mp_ops->cpu_disable(cpu);
if (ret)
return ret;
/*
* Take this CPU offline. Once we clear this, we can't return,
* and we must not schedule until we're ready to give up the cpu.
*/
set_cpu_online(cpu, false);
/*
* OK - migrate IRQs away from this CPU
*/
migrate_irqs();
/*
* Stop the local timer for this CPU.
*/
local_timer_stop(cpu);
/*
* Flush user cache and TLB mappings, and then remove this CPU
* from the vm mask set of all processes.
*/
flush_cache_all();
local_flush_tlb_all();
read_lock(&tasklist_lock);
for_each_process(p)
if (p->mm)
cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
read_unlock(&tasklist_lock);
return 0;
}
#else /* ... !CONFIG_HOTPLUG_CPU */
int native_cpu_disable(unsigned int cpu)
{
return -ENOSYS;
}
void native_cpu_die(unsigned int cpu)
{
/* We said "no" in __cpu_disable */
BUG();
}
void native_play_dead(void)
{
BUG();
}
#endif
asmlinkage void __cpuinit start_secondary(void)
{
unsigned int cpu;
unsigned int cpu = smp_processor_id();
struct mm_struct *mm = &init_mm;
enable_mmu();
atomic_inc(&mm->mm_count);
atomic_inc(&mm->mm_users);
current->active_mm = mm;
BUG_ON(current->mm);
enter_lazy_tlb(mm, current);
local_flush_tlb_all();
per_cpu_trap_init();
preempt_disable();
notify_cpu_starting(smp_processor_id());
notify_cpu_starting(cpu);
local_irq_enable();
cpu = smp_processor_id();
/* Enable local timers */
local_timer_setup(cpu);
calibrate_delay();
smp_store_cpu_info(cpu);
cpu_set(cpu, cpu_online_map);
set_cpu_online(cpu, true);
per_cpu(cpu_state, cpu) = CPU_ONLINE;
cpu_idle();
}
@@ -111,12 +224,19 @@ int __cpuinit __cpu_up(unsigned int cpu)
struct task_struct *tsk;
unsigned long timeout;
tsk = fork_idle(cpu);
if (IS_ERR(tsk)) {
printk(KERN_ERR "Failed forking idle task for cpu %d\n", cpu);
return PTR_ERR(tsk);
tsk = cpu_data[cpu].idle;
if (!tsk) {
tsk = fork_idle(cpu);
if (IS_ERR(tsk)) {
pr_err("Failed forking idle task for cpu %d\n", cpu);
return PTR_ERR(tsk);
}
cpu_data[cpu].idle = tsk;
}
per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
/* Fill in data in head.S for secondary cpus */
stack_start.sp = tsk->thread.sp;
stack_start.thread_info = tsk->stack;
@@ -127,7 +247,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
(unsigned long)&stack_start + sizeof(stack_start));
wmb();
plat_start_cpu(cpu, (unsigned long)_stext);
mp_ops->start_cpu(cpu, (unsigned long)_stext);
timeout = jiffies + HZ;
while (time_before(jiffies, timeout)) {
@@ -135,6 +255,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
break;
udelay(10);
barrier();
}
if (cpu_online(cpu))
@@ -159,7 +280,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
void smp_send_reschedule(int cpu)
{
plat_send_ipi(cpu, SMP_MSG_RESCHEDULE);
mp_ops->send_ipi(cpu, SMP_MSG_RESCHEDULE);
}
void smp_send_stop(void)
@@ -172,12 +293,12 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask)
int cpu;
for_each_cpu(cpu, mask)
plat_send_ipi(cpu, SMP_MSG_FUNCTION);
mp_ops->send_ipi(cpu, SMP_MSG_FUNCTION);
}
void arch_send_call_function_single_ipi(int cpu)
{
plat_send_ipi(cpu, SMP_MSG_FUNCTION_SINGLE);
mp_ops->send_ipi(cpu, SMP_MSG_FUNCTION_SINGLE);
}
void smp_timer_broadcast(const struct cpumask *mask)
@@ -185,7 +306,7 @@ void smp_timer_broadcast(const struct cpumask *mask)
int cpu;
for_each_cpu(cpu, mask)
plat_send_ipi(cpu, SMP_MSG_TIMER);
mp_ops->send_ipi(cpu, SMP_MSG_TIMER);
}
static void ipi_timer(void)
@@ -249,7 +370,6 @@ static void flush_tlb_mm_ipi(void *mm)
* behalf of debugees, kswapd stealing pages from another process etc).
* Kanoj 07/00.
*/
void flush_tlb_mm(struct mm_struct *mm)
{
preempt_disable();

6
arch/sh/kernel/topology.c
View File

@@ -52,7 +52,11 @@ static int __init topology_init(void)
#endif
for_each_present_cpu(i) {
ret = register_cpu(&per_cpu(cpu_devices, i), i);
struct cpu *c = &per_cpu(cpu_devices, i);
c->hotpluggable = 1;
ret = register_cpu(c, i);
if (unlikely(ret))
printk(KERN_WARNING "%s: register_cpu %d failed (%d)\n",
__func__, i, ret);

5
arch/sh/kernel/traps_64.c
View File

@@ -944,3 +944,8 @@ asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
/* Clear all DEBUGINT causes */
poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
}
void __cpuinit per_cpu_trap_init(void)
{
/* Nothing to do for now, VBR initialization later. */
}