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Merge tag 'iio-for-4.21a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-testing

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Jonathan writes:

First set of new device support, features and cleanups for IIO in the 4.21 cycle

Along with the headline feature of 5 new drivers, we have the
substantial addition of auxilliary sensor support on the lsm6sdx
parts for ST.  There has also been a good set of staging cleanup
in this period with more underway.

An ever increasing number of devices supported with just a new
ID which is a good sign that at least some manufacturers are
continuing to stabilise their interfaces.

New device support,
* ad7124
  - New driver supporting Analog Devices' ad7124-4 and ad7124-8 parts
    with the inevitable DT binding.
* ad7949
  - New driver supporting Analog Devices' ad7949, AD7682 and AD7689 ADCs.
* rm3100
  - New driver supporting PNIs RM3100 magnometer with bindings and
    vendor prefix.
* ti-dac7311
  - New driver supporting DAC7311, DAC6311 and DAC5311 TI DACs, with
    DT bindings.
* vcnl5035
  - New driver supporting the light sensor part of the VCNL4035, with
    DT bindings

Features,
* bindings
  - Add a generic ADC channel binding as we keep reinventing this
    wheel.
* adc128s052
  - Add IDs for additional pin compatible parts.
  - Add APCI ID seen on E3940 UP squared boards.
* ad_sigma_delta
  - Allow for custom data register overiding default.
* kxcjk1013
  - Add KIOX0009 ACPI ID as seen on the Acer One 10.
* lsm6dsx
  - Rework leading to...
  - External sensor support using the built in I2C master.
  - Initial support for a slave lis2mdl magnetometer.
* meson-saradc
  - Add temperature sensor support and bindings.
* st_magn
  - New ID for lsm9dsl_magn with bindings
  - New ID for lis3de accelerometer
* tpl0102
  - Add supprot for IIO_AVAIL_RANGE to report the range available
    from this device to userspace and in kernel users.

Cleanups and minor fixes
* tools
  - Allow outside specification of CFLAGS
* ad2s90
  - Handle and spi_read error.
  - Handle spi_setup failure
  - Drop a pointless assignment.
  - Prevent a potentail race by moving device registration to after
    all other setup.
  - Add missing scale attribute.
  - Add a sanity check on channel type before trying to read it.
* ad2s1210
  - Move to modern gpio descriptors.
  - Drop a gpioin flag which made no sense as far as we can tell.
  - Add dt table (bindings doc to follow when this is ready for
    moving out of staging).
* ad5933
  - Drop camel-case naming of ext_clk_hz.
  - White space fixes.
* ad7150
  - Local variable to shorten overly long line.
  - Alignment and line break fixes.
* ad7280a
  - Handle an error path that was previously ignored.
  - Use crc8.h to build the crc table replacing custom code.
  - Avoid unecessary cast.
  - Power down the device if an error happens in probe
  - Use devm routines to simplify probe and remove.
* ad7606
  - Alignment fixes.
* ad7780
  - This worked as long as by coincidence an uninitialized value
    was 0.  Lets not rely on that.
  - Ensure gain update is only used with the ad778x chips that
    actually support it.
  - Tidy up pattern mask generation.
  - Read regulator when scale is requested (which should be infrequent)
    as it might have changed from initialization.
* ad7816
  - Move to modern gpio descriptors
  - Don't use a busy_pin for ad7818 as there isn't one.
  - Ensure RD/WR and CONVST pins are outputs (previously they
    were brought up as inputs which doesn't seem to make any sense)
  - DT id table.
* adc128s052
  - SPDX
* adt7316
  - Alignment fix.
  - Fix data reading.  When using I2C the driver never actually
    used the value read.  This has been broken a very long time
    hence no rush to fix it now + the driver is undergoing a lot
    of cleanup.
  - Sanity check that the i2c read didn't fail to actually read
    anything.
* dpot-dac
  - Mark a switch full through with slightly different text so that
    gcc doesn't warn on it.
* gyro-adc
  - Fix a wrong file in the MAINTAINERS entry and add binding doc to the
    listed files.
* ina2xx
  - Add some early returns to clarify error paths in switch.
* lsm6dsx
  - MAINTAINERS entry.
* max11100
  - SPDX
* max9611
  - SPDX
* mcp4131
  - use of_device_get_match_data in preference to spi_get_device_id
    approach.
* rcar-adc
  - SPDX
* sc27xx
  - Add ADC conversion timeout support to avoid possible fault.
* ssp_sensors
  - Don't free managed resources manually.
* st-magn
  - Add a comment to avoid future confusion over when to use -magn
    postfix (on multi chip in package parts)
  - Add BDU register for LIS3MDL where it seems to have been missed.
* st-sensors
  - Minor spelling, grammar etc fixes.
* tpl0102
  - Use a pointer rather than an index of an array to improve conciseness.

* tag 'iio-for-4.21a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio: (80 commits)
  Staging: iio: adt7316: Add an extra check for 'ret' equals to 0
  Staging: iio: adt7316: Fix i2c data reading, set the data field
  dt-bindings: iio: adc: Add docs for ad7124
  iio: adc: Add ad7124 support
  dt-bindings: iio: adc: Add common ADCs properties to a separate file
  iio: ad_sigma_delta: Allow to provide custom data register address
  staging: iio: ad7816: Add device tree table.
  iio: imu: st_lsm6dsx: add entry in MAINTAINERS file
  iio: potentiometer: mcp4131: use of_device_get_match_data()
  staging: iio: adc: ad7280a: use devm_* APIs
  staging: iio: adc: ad7280a: power down the device on error in probe
  dt-bindings: iio: imu: st_lsm6dsx: add support to i2c pullup resistors
  iio: imu: st_lsm6dsx: add hw FIFO support to i2c controller
  iio: imu: st_lsm6dsx: add st_lsm6dsx_push_tagged_data routine
  iio: imu: st_lsm6dsx: add i2c embedded controller support
  iio: imu: st_lsm6dsx: introduce st_lsm6dsx_sensor_set_enable routine
  iio: imu: st_lsm6dsx: introduce ST_LSM6DSX_ID_EXT sensor ids
  iio: imu: st_lsm6dsx: remove static from st_lsm6dsx_set_watermark
  iio: imu: st_lsm6dsx: reload trimming parameter at bootstrap
  iio: imu: st_lsm6dsx: introduce locked read/write utility routines
  ...
This commit is contained in:
Greg Kroah-Hartman
2018-11-22 09:39:45 +01:00
父節點 0e2c8fb54d 00426e9978
當前提交 7c0bc65c84
共有 74 個文件被更改，包括 5240 次插入 和 763 次删除
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21
drivers/iio/adc/Kconfig
查看文件

@@ -10,6 +10,17 @@ config AD_SIGMA_DELTA
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
config AD7124
tristate "Analog Devices AD7124 and similar sigma-delta ADCs driver"
depends on SPI_MASTER
select AD_SIGMA_DELTA
help
Say yes here to build support for Analog Devices AD7124-4 and AD7124-8
SPI analog to digital converters (ADC).
To compile this driver as a module, choose M here: the module will be
called ad7124.
config AD7266
tristate "Analog Devices AD7265/AD7266 ADC driver"
depends on SPI_MASTER
@@ -116,6 +127,16 @@ config AD7923
To compile this driver as a module, choose M here: the
module will be called ad7923.
config AD7949
tristate "Analog Devices AD7949 and similar ADCs driver"
depends on SPI
help
Say yes here to build support for Analog Devices
AD7949, AD7682, AD7689 8 Channel ADCs.
To compile this driver as a module, choose M here: the
module will be called ad7949.
config AD799X
tristate "Analog Devices AD799x ADC driver"
depends on I2C

2
drivers/iio/adc/Makefile
查看文件

@@ -5,6 +5,7 @@
# When adding new entries keep the list in alphabetical order
obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o
obj-$(CONFIG_AD7124) += ad7124.o
obj-$(CONFIG_AD7266) += ad7266.o
obj-$(CONFIG_AD7291) += ad7291.o
obj-$(CONFIG_AD7298) += ad7298.o
@@ -14,6 +15,7 @@ obj-$(CONFIG_AD7766) += ad7766.o
obj-$(CONFIG_AD7791) += ad7791.o
obj-$(CONFIG_AD7793) += ad7793.o
obj-$(CONFIG_AD7887) += ad7887.o
obj-$(CONFIG_AD7949) += ad7949.o
obj-$(CONFIG_AD799X) += ad799x.o
obj-$(CONFIG_ASPEED_ADC) += aspeed_adc.o
obj-$(CONFIG_AT91_ADC) += at91_adc.o

684
drivers/iio/adc/ad7124.c Normal file
查看文件

@@ -0,0 +1,684 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* AD7124 SPI ADC driver
*
* Copyright 2018 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include <linux/iio/adc/ad_sigma_delta.h>
#include <linux/iio/sysfs.h>
/* AD7124 registers */
#define AD7124_COMMS 0x00
#define AD7124_STATUS 0x00
#define AD7124_ADC_CONTROL 0x01
#define AD7124_DATA 0x02
#define AD7124_IO_CONTROL_1 0x03
#define AD7124_IO_CONTROL_2 0x04
#define AD7124_ID 0x05
#define AD7124_ERROR 0x06
#define AD7124_ERROR_EN 0x07
#define AD7124_MCLK_COUNT 0x08
#define AD7124_CHANNEL(x) (0x09 + (x))
#define AD7124_CONFIG(x) (0x19 + (x))
#define AD7124_FILTER(x) (0x21 + (x))
#define AD7124_OFFSET(x) (0x29 + (x))
#define AD7124_GAIN(x) (0x31 + (x))
/* AD7124_STATUS */
#define AD7124_STATUS_POR_FLAG_MSK BIT(4)
/* AD7124_ADC_CONTROL */
#define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
#define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
#define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
#define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
/* AD7124_CHANNEL_X */
#define AD7124_CHANNEL_EN_MSK BIT(15)
#define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
#define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
#define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
#define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
#define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
#define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
#define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
/* AD7124_CONFIG_X */
#define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
#define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
#define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
#define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
#define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
#define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
/* AD7124_FILTER_X */
#define AD7124_FILTER_FS_MSK GENMASK(10, 0)
#define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
enum ad7124_ids {
ID_AD7124_4,
ID_AD7124_8,
};
enum ad7124_ref_sel {
AD7124_REFIN1,
AD7124_REFIN2,
AD7124_INT_REF,
AD7124_AVDD_REF,
};
enum ad7124_power_mode {
AD7124_LOW_POWER,
AD7124_MID_POWER,
AD7124_FULL_POWER,
};
static const unsigned int ad7124_gain[8] = {
1, 2, 4, 8, 16, 32, 64, 128
};
static const int ad7124_master_clk_freq_hz[3] = {
[AD7124_LOW_POWER] = 76800,
[AD7124_MID_POWER] = 153600,
[AD7124_FULL_POWER] = 614400,
};
static const char * const ad7124_ref_names[] = {
[AD7124_REFIN1] = "refin1",
[AD7124_REFIN2] = "refin2",
[AD7124_INT_REF] = "int",
[AD7124_AVDD_REF] = "avdd",
};
struct ad7124_chip_info {
unsigned int num_inputs;
};
struct ad7124_channel_config {
enum ad7124_ref_sel refsel;
bool bipolar;
unsigned int ain;
unsigned int vref_mv;
unsigned int pga_bits;
unsigned int odr;
};
struct ad7124_state {
const struct ad7124_chip_info *chip_info;
struct ad_sigma_delta sd;
struct ad7124_channel_config channel_config[4];
struct regulator *vref[4];
struct clk *mclk;
unsigned int adc_control;
unsigned int num_channels;
};
static const struct iio_chan_spec ad7124_channel_template = {
.type = IIO_VOLTAGE,
.indexed = 1,
.differential = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.scan_type = {
.sign = 'u',
.realbits = 24,
.storagebits = 32,
.shift = 8,
.endianness = IIO_BE,
},
};
static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
[ID_AD7124_4] = {
.num_inputs = 8,
},
[ID_AD7124_8] = {
.num_inputs = 16,
},
};
static int ad7124_find_closest_match(const int *array,
unsigned int size, int val)
{
int i, idx;
unsigned int diff_new, diff_old;
diff_old = U32_MAX;
idx = 0;
for (i = 0; i < size; i++) {
diff_new = abs(val - array[i]);
if (diff_new < diff_old) {
diff_old = diff_new;
idx = i;
}
}
return idx;
}
static int ad7124_spi_write_mask(struct ad7124_state *st,
unsigned int addr,
unsigned long mask,
unsigned int val,
unsigned int bytes)
{
unsigned int readval;
int ret;
ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
if (ret < 0)
return ret;
readval &= ~mask;
readval |= val;
return ad_sd_write_reg(&st->sd, addr, bytes, readval);
}
static int ad7124_set_mode(struct ad_sigma_delta *sd,
enum ad_sigma_delta_mode mode)
{
struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
}
static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
{
struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
unsigned int val;
val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
AD7124_CHANNEL_SETUP(channel);
return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
}
static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
.set_channel = ad7124_set_channel,
.set_mode = ad7124_set_mode,
.has_registers = true,
.addr_shift = 0,
.read_mask = BIT(6),
.data_reg = AD7124_DATA,
};
static int ad7124_set_channel_odr(struct ad7124_state *st,
unsigned int channel,
unsigned int odr)
{
unsigned int fclk, odr_sel_bits;
int ret;
fclk = clk_get_rate(st->mclk);
/*
* FS[10:0] = fCLK / (fADC x 32) where:
* fADC is the output data rate
* fCLK is the master clock frequency
* FS[10:0] are the bits in the filter register
* FS[10:0] can have a value from 1 to 2047
*/
odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
if (odr_sel_bits < 1)
odr_sel_bits = 1;
else if (odr_sel_bits > 2047)
odr_sel_bits = 2047;
ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
AD7124_FILTER_FS_MSK,
AD7124_FILTER_FS(odr_sel_bits), 3);
if (ret < 0)
return ret;
/* fADC = fCLK / (FS[10:0] x 32) */
st->channel_config[channel].odr =
DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
return 0;
}
static int ad7124_set_channel_gain(struct ad7124_state *st,
unsigned int channel,
unsigned int gain)
{
unsigned int res;
int ret;
res = ad7124_find_closest_match(ad7124_gain,
ARRAY_SIZE(ad7124_gain), gain);
ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
AD7124_CONFIG_PGA_MSK,
AD7124_CONFIG_PGA(res), 2);
if (ret < 0)
return ret;
st->channel_config[channel].pga_bits = res;
return 0;
}
static int ad7124_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct ad7124_state *st = iio_priv(indio_dev);
int idx, ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
if (ret < 0)
return ret;
/* After the conversion is performed, disable the channel */
ret = ad_sd_write_reg(&st->sd,
AD7124_CHANNEL(chan->address), 2,
st->channel_config[chan->address].ain |
AD7124_CHANNEL_EN(0));
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
idx = st->channel_config[chan->address].pga_bits;
*val = st->channel_config[chan->address].vref_mv;
if (st->channel_config[chan->address].bipolar)
*val2 = chan->scan_type.realbits - 1 + idx;
else
*val2 = chan->scan_type.realbits + idx;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
if (st->channel_config[chan->address].bipolar)
*val = -(1 << (chan->scan_type.realbits - 1));
else
*val = 0;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SAMP_FREQ:
*val = st->channel_config[chan->address].odr;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int ad7124_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long info)
{
struct ad7124_state *st = iio_priv(indio_dev);
unsigned int res, gain, full_scale, vref;
switch (info) {
case IIO_CHAN_INFO_SAMP_FREQ:
if (val2 != 0)
return -EINVAL;
return ad7124_set_channel_odr(st, chan->address, val);
case IIO_CHAN_INFO_SCALE:
if (val != 0)
return -EINVAL;
if (st->channel_config[chan->address].bipolar)
full_scale = 1 << (chan->scan_type.realbits - 1);
else
full_scale = 1 << chan->scan_type.realbits;
vref = st->channel_config[chan->address].vref_mv * 1000000LL;
res = DIV_ROUND_CLOSEST(vref, full_scale);
gain = DIV_ROUND_CLOSEST(res, val2);
return ad7124_set_channel_gain(st, chan->address, gain);
default:
return -EINVAL;
}
}
static IIO_CONST_ATTR(in_voltage_scale_available,
"0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
static struct attribute *ad7124_attributes[] = {
&iio_const_attr_in_voltage_scale_available.dev_attr.attr,
NULL,
};
static const struct attribute_group ad7124_attrs_group = {
.attrs = ad7124_attributes,
};
static const struct iio_info ad7124_info = {
.read_raw = ad7124_read_raw,
.write_raw = ad7124_write_raw,
.validate_trigger = ad_sd_validate_trigger,
.attrs = &ad7124_attrs_group,
};
static int ad7124_soft_reset(struct ad7124_state *st)
{
unsigned int readval, timeout;
int ret;
ret = ad_sd_reset(&st->sd, 64);
if (ret < 0)
return ret;
timeout = 100;
do {
ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
if (ret < 0)
return ret;
if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
return 0;
/* The AD7124 requires typically 2ms to power up and settle */
usleep_range(100, 2000);
} while (--timeout);
dev_err(&st->sd.spi->dev, "Soft reset failed\n");
return -EIO;
}
static int ad7124_init_channel_vref(struct ad7124_state *st,
unsigned int channel_number)
{
unsigned int refsel = st->channel_config[channel_number].refsel;
switch (refsel) {
case AD7124_REFIN1:
case AD7124_REFIN2:
case AD7124_AVDD_REF:
if (IS_ERR(st->vref[refsel])) {
dev_err(&st->sd.spi->dev,
"Error, trying to use external voltage reference without a %s regulator.\n",
ad7124_ref_names[refsel]);
return PTR_ERR(st->vref[refsel]);
}
st->channel_config[channel_number].vref_mv =
regulator_get_voltage(st->vref[refsel]);
/* Conversion from uV to mV */
st->channel_config[channel_number].vref_mv /= 1000;
break;
case AD7124_INT_REF:
st->channel_config[channel_number].vref_mv = 2500;
break;
default:
dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
return -EINVAL;
}
return 0;
}
static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
struct device_node *np)
{
struct ad7124_state *st = iio_priv(indio_dev);
struct device_node *child;
struct iio_chan_spec *chan;
unsigned int ain[2], channel = 0, tmp;
int ret;
st->num_channels = of_get_available_child_count(np);
if (!st->num_channels) {
dev_err(indio_dev->dev.parent, "no channel children\n");
return -ENODEV;
}
chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
sizeof(*chan), GFP_KERNEL);
if (!chan)
return -ENOMEM;
indio_dev->channels = chan;
indio_dev->num_channels = st->num_channels;
for_each_available_child_of_node(np, child) {
ret = of_property_read_u32(child, "reg", &channel);
if (ret)
goto err;
ret = of_property_read_u32_array(child, "diff-channels",
ain, 2);
if (ret)
goto err;
if (ain[0] >= st->chip_info->num_inputs ||
ain[1] >= st->chip_info->num_inputs) {
dev_err(indio_dev->dev.parent,
"Input pin number out of range.\n");
ret = -EINVAL;
goto err;
}
st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
AD7124_CHANNEL_AINM(ain[1]);
st->channel_config[channel].bipolar =
of_property_read_bool(child, "bipolar");
ret = of_property_read_u32(child, "adi,reference-select", &tmp);
if (ret)
st->channel_config[channel].refsel = AD7124_INT_REF;
else
st->channel_config[channel].refsel = tmp;
*chan = ad7124_channel_template;
chan->address = channel;
chan->scan_index = channel;
chan->channel = ain[0];
chan->channel2 = ain[1];
chan++;
}
return 0;
err:
of_node_put(child);
return ret;
}
static int ad7124_setup(struct ad7124_state *st)
{
unsigned int val, fclk, power_mode;
int i, ret;
fclk = clk_get_rate(st->mclk);
if (!fclk)
return -EINVAL;
/* The power mode changes the master clock frequency */
power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
ARRAY_SIZE(ad7124_master_clk_freq_hz),
fclk);
if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
ret = clk_set_rate(st->mclk, fclk);
if (ret)
return ret;
}
/* Set the power mode */
st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
if (ret < 0)
return ret;
for (i = 0; i < st->num_channels; i++) {
val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
if (ret < 0)
return ret;
ret = ad7124_init_channel_vref(st, i);
if (ret < 0)
return ret;
val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel);
ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
if (ret < 0)
return ret;
/*
* 9.38 SPS is the minimum output data rate supported
* regardless of the selected power mode. Round it up to 10 and
* set all the enabled channels to this default value.
*/
ret = ad7124_set_channel_odr(st, i, 10);
}
return ret;
}
static int ad7124_probe(struct spi_device *spi)
{
const struct spi_device_id *id;
struct ad7124_state *st;
struct iio_dev *indio_dev;
int i, ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
id = spi_get_device_id(spi);
st->chip_info = &ad7124_chip_info_tbl[id->driver_data];
ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
spi_set_drvdata(spi, indio_dev);
indio_dev->dev.parent = &spi->dev;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &ad7124_info;
ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
if (ret < 0)
return ret;
for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
if (i == AD7124_INT_REF)
continue;
st->vref[i] = devm_regulator_get_optional(&spi->dev,
ad7124_ref_names[i]);
if (PTR_ERR(st->vref[i]) == -ENODEV)
continue;
else if (IS_ERR(st->vref[i]))
return PTR_ERR(st->vref[i]);
ret = regulator_enable(st->vref[i]);
if (ret)
return ret;
}
st->mclk = devm_clk_get(&spi->dev, "mclk");
if (IS_ERR(st->mclk)) {
ret = PTR_ERR(st->mclk);
goto error_regulator_disable;
}
ret = clk_prepare_enable(st->mclk);
if (ret < 0)
goto error_regulator_disable;
ret = ad7124_soft_reset(st);
if (ret < 0)
goto error_clk_disable_unprepare;
ret = ad7124_setup(st);
if (ret < 0)
goto error_clk_disable_unprepare;
ret = ad_sd_setup_buffer_and_trigger(indio_dev);
if (ret < 0)
goto error_clk_disable_unprepare;
ret = iio_device_register(indio_dev);
if (ret < 0) {
dev_err(&spi->dev, "Failed to register iio device\n");
goto error_remove_trigger;
}
return 0;
error_remove_trigger:
ad_sd_cleanup_buffer_and_trigger(indio_dev);
error_clk_disable_unprepare:
clk_disable_unprepare(st->mclk);
error_regulator_disable:
for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
if (!IS_ERR_OR_NULL(st->vref[i]))
regulator_disable(st->vref[i]);
}
return ret;
}
static int ad7124_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad7124_state *st = iio_priv(indio_dev);
int i;
iio_device_unregister(indio_dev);
ad_sd_cleanup_buffer_and_trigger(indio_dev);
clk_disable_unprepare(st->mclk);
for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
if (!IS_ERR_OR_NULL(st->vref[i]))
regulator_disable(st->vref[i]);
}
return 0;
}
static const struct spi_device_id ad7124_id_table[] = {
{ "ad7124-4", ID_AD7124_4 },
{ "ad7124-8", ID_AD7124_8 },
{}
};
MODULE_DEVICE_TABLE(spi, ad7124_id_table);
static const struct of_device_id ad7124_of_match[] = {
{ .compatible = "adi,ad7124-4" },
{ .compatible = "adi,ad7124-8" },
{ },
};
MODULE_DEVICE_TABLE(of, ad7124_of_match);
static struct spi_driver ad71124_driver = {
.driver = {
.name = "ad7124",
.of_match_table = ad7124_of_match,
},
.probe = ad7124_probe,
.remove = ad7124_remove,
.id_table = ad7124_id_table,
};
module_spi_driver(ad71124_driver);
MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
MODULE_LICENSE("GPL");

347
drivers/iio/adc/ad7949.c Normal file
查看文件

@@ -0,0 +1,347 @@
// SPDX-License-Identifier: GPL-2.0
/* ad7949.c - Analog Devices ADC driver 14/16 bits 4/8 channels
*
* Copyright (C) 2018 CMC NV
*
* http://www.analog.com/media/en/technical-documentation/data-sheets/AD7949.pdf
*/
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#define AD7949_MASK_CHANNEL_SEL GENMASK(9, 7)
#define AD7949_MASK_TOTAL GENMASK(13, 0)
#define AD7949_OFFSET_CHANNEL_SEL 7
#define AD7949_CFG_READ_BACK 0x1
#define AD7949_CFG_REG_SIZE_BITS 14
enum {
ID_AD7949 = 0,
ID_AD7682,
ID_AD7689,
};
struct ad7949_adc_spec {
u8 num_channels;
u8 resolution;
};
static const struct ad7949_adc_spec ad7949_adc_spec[] = {
[ID_AD7949] = { .num_channels = 8, .resolution = 14 },
[ID_AD7682] = { .num_channels = 4, .resolution = 16 },
[ID_AD7689] = { .num_channels = 8, .resolution = 16 },
};
/**
* struct ad7949_adc_chip - AD ADC chip
* @lock: protects write sequences
* @vref: regulator generating Vref
* @iio_dev: reference to iio structure
* @spi: reference to spi structure
* @resolution: resolution of the chip
* @cfg: copy of the configuration register
* @current_channel: current channel in use
* @buffer: buffer to send / receive data to / from device
*/
struct ad7949_adc_chip {
struct mutex lock;
struct regulator *vref;
struct iio_dev *indio_dev;
struct spi_device *spi;
u8 resolution;
u16 cfg;
unsigned int current_channel;
u32 buffer ____cacheline_aligned;
};
static bool ad7949_spi_cfg_is_read_back(struct ad7949_adc_chip *ad7949_adc)
{
if (!(ad7949_adc->cfg & AD7949_CFG_READ_BACK))
return true;
return false;
}
static int ad7949_spi_bits_per_word(struct ad7949_adc_chip *ad7949_adc)
{
int ret = ad7949_adc->resolution;
if (ad7949_spi_cfg_is_read_back(ad7949_adc))
ret += AD7949_CFG_REG_SIZE_BITS;
return ret;
}
static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
u16 mask)
{
int ret;
int bits_per_word = ad7949_spi_bits_per_word(ad7949_adc);
int shift = bits_per_word - AD7949_CFG_REG_SIZE_BITS;
struct spi_message msg;
struct spi_transfer tx[] = {
{
.tx_buf = &ad7949_adc->buffer,
.len = 4,
.bits_per_word = bits_per_word,
},
};
ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask);
ad7949_adc->buffer = ad7949_adc->cfg << shift;
spi_message_init_with_transfers(&msg, tx, 1);
ret = spi_sync(ad7949_adc->spi, &msg);
/*
* This delay is to avoid a new request before the required time to
* send a new command to the device
*/
udelay(2);
return ret;
}
static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
unsigned int channel)
{
int ret;
int bits_per_word = ad7949_spi_bits_per_word(ad7949_adc);
int mask = GENMASK(ad7949_adc->resolution, 0);
struct spi_message msg;
struct spi_transfer tx[] = {
{
.rx_buf = &ad7949_adc->buffer,
.len = 4,
.bits_per_word = bits_per_word,
},
};
ret = ad7949_spi_write_cfg(ad7949_adc,
channel << AD7949_OFFSET_CHANNEL_SEL,
AD7949_MASK_CHANNEL_SEL);
if (ret)
return ret;
ad7949_adc->buffer = 0;
spi_message_init_with_transfers(&msg, tx, 1);
ret = spi_sync(ad7949_adc->spi, &msg);
if (ret)
return ret;
/*
* This delay is to avoid a new request before the required time to
* send a new command to the device
*/
udelay(2);
ad7949_adc->current_channel = channel;
if (ad7949_spi_cfg_is_read_back(ad7949_adc))
*val = (ad7949_adc->buffer >> AD7949_CFG_REG_SIZE_BITS) & mask;
else
*val = ad7949_adc->buffer & mask;
return 0;
}
#define AD7949_ADC_CHANNEL(chan) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
}
static const struct iio_chan_spec ad7949_adc_channels[] = {
AD7949_ADC_CHANNEL(0),
AD7949_ADC_CHANNEL(1),
AD7949_ADC_CHANNEL(2),
AD7949_ADC_CHANNEL(3),
AD7949_ADC_CHANNEL(4),
AD7949_ADC_CHANNEL(5),
AD7949_ADC_CHANNEL(6),
AD7949_ADC_CHANNEL(7),
};
static int ad7949_spi_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
int ret;
if (!val)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&ad7949_adc->lock);
ret = ad7949_spi_read_channel(ad7949_adc, val, chan->channel);
mutex_unlock(&ad7949_adc->lock);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(ad7949_adc->vref);
if (ret < 0)
return ret;
*val = ret / 5000;
return IIO_VAL_INT;
}
return -EINVAL;
}
static int ad7949_spi_reg_access(struct iio_dev *indio_dev,
unsigned int reg, unsigned int writeval,
unsigned int *readval)
{
struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
int ret = 0;
if (readval)
*readval = ad7949_adc->cfg;
else
ret = ad7949_spi_write_cfg(ad7949_adc,
writeval & AD7949_MASK_TOTAL, AD7949_MASK_TOTAL);
return ret;
}
static const struct iio_info ad7949_spi_info = {
.read_raw = ad7949_spi_read_raw,
.debugfs_reg_access = ad7949_spi_reg_access,
};
static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc)
{
int ret;
int val;
/* Sequencer disabled, CFG readback disabled, IN0 as default channel */
ad7949_adc->current_channel = 0;
ret = ad7949_spi_write_cfg(ad7949_adc, 0x3C79, AD7949_MASK_TOTAL);
/*
* Do two dummy conversions to apply the first configuration setting.
* Required only after the start up of the device.
*/
ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
return ret;
}
static int ad7949_spi_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
const struct ad7949_adc_spec *spec;
struct ad7949_adc_chip *ad7949_adc;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*ad7949_adc));
if (!indio_dev) {
dev_err(dev, "can not allocate iio device\n");
return -ENOMEM;
}
indio_dev->dev.parent = dev;
indio_dev->dev.of_node = dev->of_node;
indio_dev->info = &ad7949_spi_info;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ad7949_adc_channels;
spi_set_drvdata(spi, indio_dev);
ad7949_adc = iio_priv(indio_dev);
ad7949_adc->indio_dev = indio_dev;
ad7949_adc->spi = spi;
spec = &ad7949_adc_spec[spi_get_device_id(spi)->driver_data];
indio_dev->num_channels = spec->num_channels;
ad7949_adc->resolution = spec->resolution;
ad7949_adc->vref = devm_regulator_get(dev, "vref");
if (IS_ERR(ad7949_adc->vref)) {
dev_err(dev, "fail to request regulator\n");
return PTR_ERR(ad7949_adc->vref);
}
ret = regulator_enable(ad7949_adc->vref);
if (ret < 0) {
dev_err(dev, "fail to enable regulator\n");
return ret;
}
mutex_init(&ad7949_adc->lock);
ret = ad7949_spi_init(ad7949_adc);
if (ret) {
dev_err(dev, "enable to init this device: %d\n", ret);
goto err;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(dev, "fail to register iio device: %d\n", ret);
goto err;
}
return 0;
err:
mutex_destroy(&ad7949_adc->lock);
regulator_disable(ad7949_adc->vref);
return ret;
}
static int ad7949_spi_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
mutex_destroy(&ad7949_adc->lock);
regulator_disable(ad7949_adc->vref);
return 0;
}
static const struct of_device_id ad7949_spi_of_id[] = {
{ .compatible = "adi,ad7949" },
{ .compatible = "adi,ad7682" },
{ .compatible = "adi,ad7689" },
{ }
};
MODULE_DEVICE_TABLE(of, ad7949_spi_of_id);
static const struct spi_device_id ad7949_spi_id[] = {
{ "ad7949", ID_AD7949 },
{ "ad7682", ID_AD7682 },
{ "ad7689", ID_AD7689 },
{ }
};
MODULE_DEVICE_TABLE(spi, ad7949_spi_id);
static struct spi_driver ad7949_spi_driver = {
.driver = {
.name = "ad7949",
.of_match_table = ad7949_spi_of_id,
},
.probe = ad7949_spi_probe,
.remove = ad7949_spi_remove,
.id_table = ad7949_spi_id,
};
module_spi_driver(ad7949_spi_driver);
MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@essensium.com>");
MODULE_DESCRIPTION("Analog Devices 14/16-bit 8-channel ADC driver");
MODULE_LICENSE("GPL v2");

22
drivers/iio/adc/ad_sigma_delta.c
查看文件

@@ -278,6 +278,7 @@ int ad_sigma_delta_single_conversion(struct iio_dev *indio_dev,
{
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
unsigned int sample, raw_sample;
unsigned int data_reg;
int ret = 0;
if (iio_buffer_enabled(indio_dev))
@@ -305,7 +306,12 @@ int ad_sigma_delta_single_conversion(struct iio_dev *indio_dev,
if (ret < 0)
goto out;
ret = ad_sd_read_reg(sigma_delta, AD_SD_REG_DATA,
if (sigma_delta->info->data_reg != 0)
data_reg = sigma_delta->info->data_reg;
else
data_reg = AD_SD_REG_DATA;
ret = ad_sd_read_reg(sigma_delta, data_reg,
DIV_ROUND_UP(chan->scan_type.realbits + chan->scan_type.shift, 8),
&raw_sample);
@@ -392,6 +398,7 @@ static irqreturn_t ad_sd_trigger_handler(int irq, void *p)
struct iio_dev *indio_dev = pf->indio_dev;
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
unsigned int reg_size;
unsigned int data_reg;
uint8_t data[16];
int ret;
@@ -401,18 +408,23 @@ static irqreturn_t ad_sd_trigger_handler(int irq, void *p)
indio_dev->channels[0].scan_type.shift;
reg_size = DIV_ROUND_UP(reg_size, 8);
if (sigma_delta->info->data_reg != 0)
data_reg = sigma_delta->info->data_reg;
else
data_reg = AD_SD_REG_DATA;
switch (reg_size) {
case 4:
case 2:
case 1:
ret = ad_sd_read_reg_raw(sigma_delta, AD_SD_REG_DATA,
reg_size, &data[0]);
ret = ad_sd_read_reg_raw(sigma_delta, data_reg, reg_size,
&data[0]);
break;
case 3:
/* We store 24 bit samples in a 32 bit word. Keep the upper
* byte set to zero. */
ret = ad_sd_read_reg_raw(sigma_delta, AD_SD_REG_DATA,
reg_size, &data[1]);
ret = ad_sd_read_reg_raw(sigma_delta, data_reg, reg_size,
&data[1]);
break;
}

2
drivers/iio/adc/ina2xx-adc.c
查看文件

@@ -250,6 +250,7 @@ static int ina2xx_read_raw(struct iio_dev *indio_dev,
*val2 = chip->shunt_resistor_uohm;
return IIO_VAL_FRACTIONAL;
}
return -EINVAL;
case IIO_CHAN_INFO_HARDWAREGAIN:
switch (chan->address) {
@@ -262,6 +263,7 @@ static int ina2xx_read_raw(struct iio_dev *indio_dev,
*val = chip->range_vbus == 32 ? 1 : 2;
return IIO_VAL_INT;
}
return -EINVAL;
}
return -EINVAL;

5
drivers/iio/adc/max11100.c
查看文件

@@ -1,13 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
* iio/adc/max11100.c
* Maxim max11100 ADC Driver with IIO interface
*
* Copyright (C) 2016-17 Renesas Electronics Corporation
* Copyright (C) 2016-17 Jacopo Mondi
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/delay.h>
#include <linux/kernel.h>

5
drivers/iio/adc/max9611.c
查看文件

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
/*
* iio/adc/max9611.c
*
@@ -5,10 +6,6 @@
* 12-bit ADC interface.
*
* Copyright (C) 2017 Jacopo Mondi
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*

229
drivers/iio/adc/meson_saradc.c
查看文件

@@ -18,6 +18,7 @@
#include <linux/io.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_irq.h>
@@ -165,6 +166,14 @@
#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
#define MESON_SAR_ADC_TIMEOUT 100 /* ms */
#define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6
#define MESON_SAR_ADC_TEMP_OFFSET 27
/* temperature sensor calibration information in eFuse */
#define MESON_SAR_ADC_EFUSE_BYTES 4
#define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)
#define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)
/* for use with IIO_VAL_INT_PLUS_MICRO */
#define MILLION 1000000
@@ -175,16 +184,25 @@
.address = _chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS) | \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
BIT(IIO_CHAN_INFO_CALIBSCALE), \
.datasheet_name = "SAR_ADC_CH"#_chan, \
}
/*
* TODO: the hardware supports IIO_TEMP for channel 6 as well which is
* currently not supported by this driver.
*/
#define MESON_SAR_ADC_TEMP_CHAN(_chan) { \
.type = IIO_TEMP, \
.channel = _chan, \
.address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
BIT(IIO_CHAN_INFO_CALIBSCALE), \
.datasheet_name = "TEMP_SENSOR", \
}
static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
MESON_SAR_ADC_CHAN(0),
MESON_SAR_ADC_CHAN(1),
@@ -197,6 +215,19 @@ static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(8),
};
static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
MESON_SAR_ADC_CHAN(0),
MESON_SAR_ADC_CHAN(1),
MESON_SAR_ADC_CHAN(2),
MESON_SAR_ADC_CHAN(3),
MESON_SAR_ADC_CHAN(4),
MESON_SAR_ADC_CHAN(5),
MESON_SAR_ADC_CHAN(6),
MESON_SAR_ADC_CHAN(7),
MESON_SAR_ADC_TEMP_CHAN(8),
IIO_CHAN_SOFT_TIMESTAMP(9),
};
enum meson_sar_adc_avg_mode {
NO_AVERAGING = 0x0,
MEAN_AVERAGING = 0x1,
@@ -225,6 +256,9 @@ struct meson_sar_adc_param {
u32 bandgap_reg;
unsigned int resolution;
const struct regmap_config *regmap_config;
u8 temperature_trimming_bits;
unsigned int temperature_multiplier;
unsigned int temperature_divider;
};
struct meson_sar_adc_data {
@@ -246,6 +280,9 @@ struct meson_sar_adc_priv {
struct completion done;
int calibbias;
int calibscale;
bool temperature_sensor_calibrated;
u8 temperature_sensor_coefficient;
u16 temperature_sensor_adc_val;
};
static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
@@ -389,9 +426,16 @@ static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
regval);
if (chan->address == 6)
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
if (chan->type == IIO_TEMP)
regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
else
regval = 0;
regmap_update_bits(priv->regmap,
MESON_SAR_ADC_DELTA_10,
MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
}
}
static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
@@ -506,8 +550,12 @@ static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
enum meson_sar_adc_num_samples avg_samples,
int *val)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
int ret;
if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
return -ENOTSUPP;
ret = meson_sar_adc_lock(indio_dev);
if (ret)
return ret;
@@ -555,16 +603,30 @@ static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
break;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(priv->vref);
if (ret < 0) {
dev_err(indio_dev->dev.parent,
"failed to get vref voltage: %d\n", ret);
return ret;
}
if (chan->type == IIO_VOLTAGE) {
ret = regulator_get_voltage(priv->vref);
if (ret < 0) {
dev_err(indio_dev->dev.parent,
"failed to get vref voltage: %d\n",
ret);
return ret;
}
*val = ret / 1000;
*val2 = priv->param->resolution;
return IIO_VAL_FRACTIONAL_LOG2;
*val = ret / 1000;
*val2 = priv->param->resolution;
return IIO_VAL_FRACTIONAL_LOG2;
} else if (chan->type == IIO_TEMP) {
/* SoC specific multiplier and divider */
*val = priv->param->temperature_multiplier;
*val2 = priv->param->temperature_divider;
/* celsius to millicelsius */
*val *= 1000;
return IIO_VAL_FRACTIONAL;
} else {
return -EINVAL;
}
case IIO_CHAN_INFO_CALIBBIAS:
*val = priv->calibbias;
@@ -575,6 +637,13 @@ static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
*val2 = priv->calibscale % MILLION;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_OFFSET:
*val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
priv->param->temperature_divider,
priv->param->temperature_multiplier);
*val -= priv->temperature_sensor_adc_val;
return IIO_VAL_INT;
default:
return -EINVAL;
}
@@ -625,6 +694,65 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
return 0;
}
static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
struct nvmem_cell *temperature_calib;
size_t read_len;
int ret;
temperature_calib = devm_nvmem_cell_get(&indio_dev->dev,
"temperature_calib");
if (IS_ERR(temperature_calib)) {
ret = PTR_ERR(temperature_calib);
/*
* leave the temperature sensor disabled if no calibration data
* was passed via nvmem-cells.
*/
if (ret == -ENODEV)
return 0;
if (ret != -EPROBE_DEFER)
dev_err(indio_dev->dev.parent,
"failed to get temperature_calib cell\n");
return ret;
}
read_len = MESON_SAR_ADC_EFUSE_BYTES;
buf = nvmem_cell_read(temperature_calib, &read_len);
if (IS_ERR(buf)) {
dev_err(indio_dev->dev.parent,
"failed to read temperature_calib cell\n");
return PTR_ERR(buf);
} else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
kfree(buf);
dev_err(indio_dev->dev.parent,
"invalid read size of temperature_calib cell\n");
return -EINVAL;
}
trimming_bits = priv->param->temperature_trimming_bits;
trimming_mask = BIT(trimming_bits) - 1;
priv->temperature_sensor_calibrated =
buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
buf[3]);
priv->temperature_sensor_adc_val = buf[2];
priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
priv->temperature_sensor_adc_val >>= trimming_bits;
kfree(buf);
return 0;
}
static int meson_sar_adc_init(struct iio_dev *indio_dev)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
@@ -649,10 +777,12 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
meson_sar_adc_stop_sample_engine(indio_dev);
/* update the channel 6 MUX to select the temperature sensor */
/*
* disable this bit as seems to be only relevant for Meson6 (based
* on the vendor driver), which we don't support at the moment.
*/
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0);
/* disable all channels by default */
regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
@@ -709,6 +839,29 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
if (priv->temperature_sensor_calibrated) {
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
MESON_SAR_ADC_DELTA_10_TS_REVE1,
MESON_SAR_ADC_DELTA_10_TS_REVE1);
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
MESON_SAR_ADC_DELTA_10_TS_REVE0,
MESON_SAR_ADC_DELTA_10_TS_REVE0);
/*
* set bits [3:0] of the TSC (temperature sensor coefficient)
* to get the correct values when reading the temperature.
*/
regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
priv->temperature_sensor_coefficient);
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
} else {
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
MESON_SAR_ADC_DELTA_10_TS_REVE1, 0);
regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
}
ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
if (ret) {
dev_err(indio_dev->dev.parent,
@@ -894,6 +1047,17 @@ static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
.bandgap_reg = MESON_SAR_ADC_DELTA_10,
.regmap_config = &meson_sar_adc_regmap_config_meson8,
.resolution = 10,
.temperature_trimming_bits = 4,
.temperature_multiplier = 18 * 10000,
.temperature_divider = 1024 * 10 * 85,
};
static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
.has_bl30_integration = false,
.clock_rate = 1150000,
.bandgap_reg = MESON_SAR_ADC_DELTA_10,
.regmap_config = &meson_sar_adc_regmap_config_meson8,
.resolution = 10,
};
static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
@@ -918,12 +1082,12 @@ static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
};
static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
.param = &meson_sar_adc_meson8_param,
.param = &meson_sar_adc_meson8b_param,
.name = "meson-meson8b-saradc",
};
static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
.param = &meson_sar_adc_meson8_param,
.param = &meson_sar_adc_meson8b_param,
.name = "meson-meson8m2-saradc",
};
@@ -1009,9 +1173,6 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &meson_sar_adc_iio_info;
indio_dev->channels = meson_sar_adc_iio_channels;
indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
@@ -1078,6 +1239,22 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
priv->calibscale = MILLION;
if (priv->param->temperature_trimming_bits) {
ret = meson_sar_adc_temp_sensor_init(indio_dev);
if (ret)
return ret;
}
if (priv->temperature_sensor_calibrated) {
indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
indio_dev->num_channels =
ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
} else {
indio_dev->channels = meson_sar_adc_iio_channels;
indio_dev->num_channels =
ARRAY_SIZE(meson_sar_adc_iio_channels);
}
ret = meson_sar_adc_init(indio_dev);
if (ret)
goto err;

11
drivers/iio/adc/rcar-gyroadc.c
查看文件

@@ -1,17 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Renesas R-Car GyroADC driver
*
* Copyright 2016 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>

12
drivers/iio/adc/sc27xx_adc.c
查看文件

@@ -52,6 +52,9 @@
/* Timeout (ms) for the trylock of hardware spinlocks */
#define SC27XX_ADC_HWLOCK_TIMEOUT 5000
/* Timeout (ms) for ADC data conversion according to ADC datasheet */
#define SC27XX_ADC_RDY_TIMEOUT 100
/* Maximum ADC channel number */
#define SC27XX_ADC_CHANNEL_MAX 32
@@ -223,7 +226,14 @@ static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel,
if (ret)
goto disable_adc;
wait_for_completion(&data->completion);
ret = wait_for_completion_timeout(&data->completion,
msecs_to_jiffies(SC27XX_ADC_RDY_TIMEOUT));
if (!ret) {
dev_err(data->dev, "read ADC data timeout\n");
ret = -ETIMEDOUT;
} else {
ret = 0;
}
disable_adc:
regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,

37
drivers/iio/adc/ti-adc128s052.c
查看文件

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2014 Angelo Compagnucci <angelo.compagnucci@gmail.com>
*
@@ -6,16 +7,14 @@
* http://www.ti.com/lit/ds/symlink/adc128s052.pdf
* http://www.ti.com/lit/ds/symlink/adc122s021.pdf
* http://www.ti.com/lit/ds/symlink/adc124s021.pdf
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
struct adc128_configuration {
@@ -135,10 +134,15 @@ static const struct iio_info adc128_info = {
static int adc128_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
unsigned int config;
struct adc128 *adc;
int config = spi_get_device_id(spi)->driver_data;
int ret;
if (dev_fwnode(&spi->dev))
config = (unsigned long) device_get_match_data(&spi->dev);
else
config = spi_get_device_id(spi)->driver_data;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
if (!indio_dev)
return -ENOMEM;
@@ -186,23 +190,40 @@ static int adc128_remove(struct spi_device *spi)
static const struct of_device_id adc128_of_match[] = {
{ .compatible = "ti,adc128s052", },
{ .compatible = "ti,adc122s021", },
{ .compatible = "ti,adc122s051", },
{ .compatible = "ti,adc122s101", },
{ .compatible = "ti,adc124s021", },
{ .compatible = "ti,adc124s051", },
{ .compatible = "ti,adc124s101", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, adc128_of_match);
static const struct spi_device_id adc128_id[] = {
{ "adc128s052", 0}, /* index into adc128_config */
{ "adc122s021", 1},
{ "adc124s021", 2},
{ "adc128s052", 0 }, /* index into adc128_config */
{ "adc122s021", 1 },
{ "adc122s051", 1 },
{ "adc122s101", 1 },
{ "adc124s021", 2 },
{ "adc124s051", 2 },
{ "adc124s101", 2 },
{ }
};
MODULE_DEVICE_TABLE(spi, adc128_id);
#ifdef CONFIG_ACPI
static const struct acpi_device_id adc128_acpi_match[] = {
{ "AANT1280", 2 }, /* ADC124S021 compatible ACPI ID */
{ }
};
MODULE_DEVICE_TABLE(acpi, adc128_acpi_match);
#endif
static struct spi_driver adc128_driver = {
.driver = {
.name = "adc128s052",
.of_match_table = of_match_ptr(adc128_of_match),
.acpi_match_table = ACPI_PTR(adc128_acpi_match),
},
.probe = adc128_probe,
.remove = adc128_remove,