powerpc: Remove Xilinx PPC405/PPC440 support
The latest Xilinx design tools called ISE and EDK has been released in October 2013. New tool doesn't support any PPC405/PPC440 new designs. These platforms are no longer supported and tested. PowerPC 405/440 port is orphan from 2013 by commitcdeb89943b("MAINTAINERS: Fix incorrect status tag") and commit19624236cc("MAINTAINERS: Update Grant's email address and maintainership") that's why it is time to remove the support fot these platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/8c593895e2cb57d232d85ce4d8c3a1aa7f0869cc.1590079968.git.christophe.leroy@csgroup.eu
This commit is contained in:
Michal Simek
committed by
Michael Ellerman
Michael Ellerman
parent
0bdad33d6b
commit
7ade8495dc
@@ -79,7 +79,6 @@ $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
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$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
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$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
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$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
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$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
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# The pre-boot decompressors pull in a lot of kernel headers and other source
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# files. This creates a bit of a dependency headache since we need to copy
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@@ -129,14 +128,12 @@ src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
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src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
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src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
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src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
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src-wlib-$(CONFIG_XILINX_VIRTEX) += uartlite.c
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src-wlib-$(CONFIG_CPM) += cpm-serial.c
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src-plat-y := of.c epapr.c
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src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
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treeboot-walnut.c cuboot-acadia.c \
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cuboot-kilauea.c simpleboot.c \
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virtex405-head.S virtex.c
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cuboot-kilauea.c simpleboot.c
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src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
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cuboot-bamboo.c cuboot-sam440ep.c \
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cuboot-sequoia.c cuboot-rainier.c \
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@@ -144,7 +141,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
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cuboot-warp.c cuboot-yosemite.c \
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treeboot-iss4xx.c treeboot-currituck.c \
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treeboot-akebono.c \
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simpleboot.c fixed-head.S virtex.c
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simpleboot.c fixed-head.S
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src-plat-$(CONFIG_PPC_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
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src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
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src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
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@@ -4,4 +4,3 @@ subdir-y += fsl
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dtstree := $(srctree)/$(src)
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dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
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dtb-$(CONFIG_XILINX_VIRTEX440_GENERIC_BOARD) += virtex440-ml507.dtb virtex440-ml510.dtb
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@@ -1,406 +0,0 @@
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/*
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* This file supports the Xilinx ML507 board with the 440 processor.
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* A reference design for the FPGA is provided at http://git.xilinx.com.
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*
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* (C) Copyright 2008 Xilinx, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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* ---
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*
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* Device Tree Generator version: 1.1
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*
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* CAUTION: This file is automatically generated by libgen.
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* Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
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*
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* XPS project directory: ml507_ppc440_emb_ref
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,virtex440";
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dcr-parent = <&ppc440_0>;
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model = "testing";
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DDR2_SDRAM: memory@0 {
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device_type = "memory";
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reg = < 0 0x10000000 >;
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} ;
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chosen {
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bootargs = "console=ttyS0 root=/dev/ram";
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stdout-path = &RS232_Uart_1;
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} ;
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cpus {
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#address-cells = <1>;
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#cpus = <1>;
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#size-cells = <0>;
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ppc440_0: cpu@0 {
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clock-frequency = <400000000>;
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compatible = "PowerPC,440", "ibm,ppc440";
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d-cache-line-size = <0x20>;
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d-cache-size = <0x8000>;
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dcr-access-method = "native";
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dcr-controller ;
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device_type = "cpu";
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i-cache-line-size = <0x20>;
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i-cache-size = <0x8000>;
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model = "PowerPC,440";
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reg = <0>;
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timebase-frequency = <400000000>;
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xlnx,apu-control = <1>;
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xlnx,apu-udi-0 = <0>;
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xlnx,apu-udi-1 = <0>;
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xlnx,apu-udi-10 = <0>;
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xlnx,apu-udi-11 = <0>;
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xlnx,apu-udi-12 = <0>;
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xlnx,apu-udi-13 = <0>;
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xlnx,apu-udi-14 = <0>;
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xlnx,apu-udi-15 = <0>;
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xlnx,apu-udi-2 = <0>;
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xlnx,apu-udi-3 = <0>;
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xlnx,apu-udi-4 = <0>;
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xlnx,apu-udi-5 = <0>;
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xlnx,apu-udi-6 = <0>;
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xlnx,apu-udi-7 = <0>;
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xlnx,apu-udi-8 = <0>;
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xlnx,apu-udi-9 = <0>;
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xlnx,dcr-autolock-enable = <1>;
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xlnx,dcu-rd-ld-cache-plb-prio = <0>;
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xlnx,dcu-rd-noncache-plb-prio = <0>;
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xlnx,dcu-rd-touch-plb-prio = <0>;
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xlnx,dcu-rd-urgent-plb-prio = <0>;
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xlnx,dcu-wr-flush-plb-prio = <0>;
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xlnx,dcu-wr-store-plb-prio = <0>;
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xlnx,dcu-wr-urgent-plb-prio = <0>;
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xlnx,dma0-control = <0>;
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xlnx,dma0-plb-prio = <0>;
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xlnx,dma0-rxchannelctrl = <0x1010000>;
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xlnx,dma0-rxirqtimer = <0x3ff>;
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xlnx,dma0-txchannelctrl = <0x1010000>;
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xlnx,dma0-txirqtimer = <0x3ff>;
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xlnx,dma1-control = <0>;
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xlnx,dma1-plb-prio = <0>;
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xlnx,dma1-rxchannelctrl = <0x1010000>;
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xlnx,dma1-rxirqtimer = <0x3ff>;
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xlnx,dma1-txchannelctrl = <0x1010000>;
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xlnx,dma1-txirqtimer = <0x3ff>;
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xlnx,dma2-control = <0>;
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xlnx,dma2-plb-prio = <0>;
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xlnx,dma2-rxchannelctrl = <0x1010000>;
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xlnx,dma2-rxirqtimer = <0x3ff>;
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xlnx,dma2-txchannelctrl = <0x1010000>;
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xlnx,dma2-txirqtimer = <0x3ff>;
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xlnx,dma3-control = <0>;
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xlnx,dma3-plb-prio = <0>;
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xlnx,dma3-rxchannelctrl = <0x1010000>;
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xlnx,dma3-rxirqtimer = <0x3ff>;
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xlnx,dma3-txchannelctrl = <0x1010000>;
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xlnx,dma3-txirqtimer = <0x3ff>;
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xlnx,endian-reset = <0>;
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xlnx,generate-plb-timespecs = <1>;
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xlnx,icu-rd-fetch-plb-prio = <0>;
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xlnx,icu-rd-spec-plb-prio = <0>;
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xlnx,icu-rd-touch-plb-prio = <0>;
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xlnx,interconnect-imask = <0xffffffff>;
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xlnx,mplb-allow-lock-xfer = <1>;
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xlnx,mplb-arb-mode = <0>;
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xlnx,mplb-awidth = <0x20>;
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xlnx,mplb-counter = <0x500>;
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xlnx,mplb-dwidth = <0x80>;
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xlnx,mplb-max-burst = <8>;
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xlnx,mplb-native-dwidth = <0x80>;
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xlnx,mplb-p2p = <0>;
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xlnx,mplb-prio-dcur = <2>;
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xlnx,mplb-prio-dcuw = <3>;
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xlnx,mplb-prio-icu = <4>;
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xlnx,mplb-prio-splb0 = <1>;
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xlnx,mplb-prio-splb1 = <0>;
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xlnx,mplb-read-pipe-enable = <1>;
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xlnx,mplb-sync-tattribute = <0>;
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xlnx,mplb-wdog-enable = <1>;
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xlnx,mplb-write-pipe-enable = <1>;
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xlnx,mplb-write-post-enable = <1>;
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xlnx,num-dma = <1>;
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xlnx,pir = <0xf>;
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xlnx,ppc440mc-addr-base = <0>;
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xlnx,ppc440mc-addr-high = <0xfffffff>;
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xlnx,ppc440mc-arb-mode = <0>;
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xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
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xlnx,ppc440mc-control = <0xf810008f>;
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xlnx,ppc440mc-max-burst = <8>;
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xlnx,ppc440mc-prio-dcur = <2>;
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xlnx,ppc440mc-prio-dcuw = <3>;
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xlnx,ppc440mc-prio-icu = <4>;
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xlnx,ppc440mc-prio-splb0 = <1>;
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xlnx,ppc440mc-prio-splb1 = <0>;
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xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
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xlnx,ppcdm-asyncmode = <0>;
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xlnx,ppcds-asyncmode = <0>;
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xlnx,user-reset = <0>;
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DMA0: sdma@80 {
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compatible = "xlnx,ll-dma-1.00.a";
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dcr-reg = < 0x80 0x11 >;
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 10 2 11 2 >;
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} ;
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} ;
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} ;
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plb_v46_0: plb@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
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ranges ;
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DIP_Switches_8Bit: gpio@81460000 {
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compatible = "xlnx,xps-gpio-1.00.a";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 7 2 >;
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reg = < 0x81460000 0x10000 >;
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xlnx,all-inputs = <1>;
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xlnx,all-inputs-2 = <0>;
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xlnx,dout-default = <0>;
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xlnx,dout-default-2 = <0>;
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xlnx,family = "virtex5";
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xlnx,gpio-width = <8>;
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xlnx,interrupt-present = <1>;
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xlnx,is-bidir = <1>;
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xlnx,is-bidir-2 = <1>;
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xlnx,is-dual = <0>;
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xlnx,tri-default = <0xffffffff>;
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xlnx,tri-default-2 = <0xffffffff>;
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} ;
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FLASH: flash@fc000000 {
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bank-width = <2>;
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compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
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reg = < 0xfc000000 0x2000000 >;
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xlnx,family = "virtex5";
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xlnx,include-datawidth-matching-0 = <0x1>;
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xlnx,include-datawidth-matching-1 = <0x0>;
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xlnx,include-datawidth-matching-2 = <0x0>;
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xlnx,include-datawidth-matching-3 = <0x0>;
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xlnx,include-negedge-ioregs = <0x0>;
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xlnx,include-plb-ipif = <0x1>;
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xlnx,include-wrbuf = <0x1>;
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xlnx,max-mem-width = <0x10>;
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xlnx,mch-native-dwidth = <0x20>;
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xlnx,mch-plb-clk-period-ps = <0x2710>;
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xlnx,mch-splb-awidth = <0x20>;
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xlnx,mch0-accessbuf-depth = <0x10>;
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xlnx,mch0-protocol = <0x0>;
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xlnx,mch0-rddatabuf-depth = <0x10>;
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xlnx,mch1-accessbuf-depth = <0x10>;
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xlnx,mch1-protocol = <0x0>;
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xlnx,mch1-rddatabuf-depth = <0x10>;
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xlnx,mch2-accessbuf-depth = <0x10>;
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xlnx,mch2-protocol = <0x0>;
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xlnx,mch2-rddatabuf-depth = <0x10>;
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xlnx,mch3-accessbuf-depth = <0x10>;
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xlnx,mch3-protocol = <0x0>;
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xlnx,mch3-rddatabuf-depth = <0x10>;
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xlnx,mem0-width = <0x10>;
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xlnx,mem1-width = <0x20>;
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xlnx,mem2-width = <0x20>;
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xlnx,mem3-width = <0x20>;
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xlnx,num-banks-mem = <0x1>;
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xlnx,num-channels = <0x2>;
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xlnx,priority-mode = <0x0>;
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xlnx,synch-mem-0 = <0x0>;
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xlnx,synch-mem-1 = <0x0>;
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xlnx,synch-mem-2 = <0x0>;
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xlnx,synch-mem-3 = <0x0>;
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xlnx,synch-pipedelay-0 = <0x2>;
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xlnx,synch-pipedelay-1 = <0x2>;
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xlnx,synch-pipedelay-2 = <0x2>;
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xlnx,synch-pipedelay-3 = <0x2>;
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xlnx,tavdv-ps-mem-0 = <0x1adb0>;
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xlnx,tavdv-ps-mem-1 = <0x3a98>;
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xlnx,tavdv-ps-mem-2 = <0x3a98>;
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xlnx,tavdv-ps-mem-3 = <0x3a98>;
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xlnx,tcedv-ps-mem-0 = <0x1adb0>;
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xlnx,tcedv-ps-mem-1 = <0x3a98>;
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xlnx,tcedv-ps-mem-2 = <0x3a98>;
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xlnx,tcedv-ps-mem-3 = <0x3a98>;
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xlnx,thzce-ps-mem-0 = <0x88b8>;
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xlnx,thzce-ps-mem-1 = <0x1b58>;
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xlnx,thzce-ps-mem-2 = <0x1b58>;
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xlnx,thzce-ps-mem-3 = <0x1b58>;
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xlnx,thzoe-ps-mem-0 = <0x1b58>;
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xlnx,thzoe-ps-mem-1 = <0x1b58>;
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xlnx,thzoe-ps-mem-2 = <0x1b58>;
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xlnx,thzoe-ps-mem-3 = <0x1b58>;
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xlnx,tlzwe-ps-mem-0 = <0x88b8>;
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xlnx,tlzwe-ps-mem-1 = <0x0>;
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xlnx,tlzwe-ps-mem-2 = <0x0>;
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xlnx,tlzwe-ps-mem-3 = <0x0>;
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xlnx,twc-ps-mem-0 = <0x2af8>;
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xlnx,twc-ps-mem-1 = <0x3a98>;
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xlnx,twc-ps-mem-2 = <0x3a98>;
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xlnx,twc-ps-mem-3 = <0x3a98>;
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xlnx,twp-ps-mem-0 = <0x11170>;
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xlnx,twp-ps-mem-1 = <0x2ee0>;
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xlnx,twp-ps-mem-2 = <0x2ee0>;
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xlnx,twp-ps-mem-3 = <0x2ee0>;
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xlnx,xcl0-linesize = <0x4>;
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xlnx,xcl0-writexfer = <0x1>;
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xlnx,xcl1-linesize = <0x4>;
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xlnx,xcl1-writexfer = <0x1>;
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xlnx,xcl2-linesize = <0x4>;
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xlnx,xcl2-writexfer = <0x1>;
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xlnx,xcl3-linesize = <0x4>;
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xlnx,xcl3-writexfer = <0x1>;
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} ;
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Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,compound";
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ethernet@81c00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "xlnx,xps-ll-temac-1.01.b";
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device_type = "network";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 5 2 >;
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llink-connected = <&DMA0>;
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local-mac-address = [ 02 00 00 00 00 00 ];
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reg = < 0x81c00000 0x40 >;
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xlnx,bus2core-clk-ratio = <1>;
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xlnx,phy-type = <1>;
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xlnx,phyaddr = <1>;
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xlnx,rxcsum = <1>;
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xlnx,rxfifo = <0x1000>;
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xlnx,temac-type = <0>;
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xlnx,txcsum = <1>;
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xlnx,txfifo = <0x1000>;
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phy-handle = <&phy7>;
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clock-frequency = <100000000>;
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phy7: phy@7 {
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compatible = "marvell,88e1111";
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reg = <7>;
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} ;
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} ;
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} ;
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IIC_EEPROM: i2c@81600000 {
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compatible = "xlnx,xps-iic-2.00.a";
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interrupt-parent = <&xps_intc_0>;
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interrupts = < 6 2 >;
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reg = < 0x81600000 0x10000 >;
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xlnx,clk-freq = <0x5f5e100>;
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xlnx,family = "virtex5";
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xlnx,gpo-width = <0x1>;
|
||||
xlnx,iic-freq = <0x186a0>;
|
||||
xlnx,scl-inertial-delay = <0x0>;
|
||||
xlnx,sda-inertial-delay = <0x0>;
|
||||
xlnx,ten-bit-adr = <0x0>;
|
||||
} ;
|
||||
LEDs_8Bit: gpio@81400000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
reg = < 0x81400000 0x10000 >;
|
||||
xlnx,all-inputs = <0>;
|
||||
xlnx,all-inputs-2 = <0>;
|
||||
xlnx,dout-default = <0>;
|
||||
xlnx,dout-default-2 = <0>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpio-width = <8>;
|
||||
xlnx,interrupt-present = <0>;
|
||||
xlnx,is-bidir = <1>;
|
||||
xlnx,is-bidir-2 = <1>;
|
||||
xlnx,is-dual = <0>;
|
||||
xlnx,tri-default = <0xffffffff>;
|
||||
xlnx,tri-default-2 = <0xffffffff>;
|
||||
} ;
|
||||
LEDs_Positions: gpio@81420000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
reg = < 0x81420000 0x10000 >;
|
||||
xlnx,all-inputs = <0>;
|
||||
xlnx,all-inputs-2 = <0>;
|
||||
xlnx,dout-default = <0>;
|
||||
xlnx,dout-default-2 = <0>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpio-width = <5>;
|
||||
xlnx,interrupt-present = <0>;
|
||||
xlnx,is-bidir = <1>;
|
||||
xlnx,is-bidir-2 = <1>;
|
||||
xlnx,is-dual = <0>;
|
||||
xlnx,tri-default = <0xffffffff>;
|
||||
xlnx,tri-default-2 = <0xffffffff>;
|
||||
} ;
|
||||
Push_Buttons_5Bit: gpio@81440000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 8 2 >;
|
||||
reg = < 0x81440000 0x10000 >;
|
||||
xlnx,all-inputs = <1>;
|
||||
xlnx,all-inputs-2 = <0>;
|
||||
xlnx,dout-default = <0>;
|
||||
xlnx,dout-default-2 = <0>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpio-width = <5>;
|
||||
xlnx,interrupt-present = <1>;
|
||||
xlnx,is-bidir = <1>;
|
||||
xlnx,is-bidir-2 = <1>;
|
||||
xlnx,is-dual = <0>;
|
||||
xlnx,tri-default = <0xffffffff>;
|
||||
xlnx,tri-default-2 = <0xffffffff>;
|
||||
} ;
|
||||
RS232_Uart_1: serial@83e00000 {
|
||||
clock-frequency = <100000000>;
|
||||
compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
|
||||
current-speed = <9600>;
|
||||
device_type = "serial";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 9 2 >;
|
||||
reg = < 0x83e00000 0x10000 >;
|
||||
reg-offset = <0x1003>;
|
||||
reg-shift = <2>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,has-external-rclk = <0>;
|
||||
xlnx,has-external-xin = <0>;
|
||||
xlnx,is-a-16550 = <1>;
|
||||
} ;
|
||||
SysACE_CompactFlash: sysace@83600000 {
|
||||
compatible = "xlnx,xps-sysace-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 4 2 >;
|
||||
reg = < 0x83600000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,mem-width = <0x10>;
|
||||
} ;
|
||||
xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
|
||||
compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
|
||||
reg = < 0xffff0000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
} ;
|
||||
xps_intc_0: interrupt-controller@81800000 {
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "xlnx,xps-intc-1.00.a";
|
||||
interrupt-controller ;
|
||||
reg = < 0x81800000 0x10000 >;
|
||||
xlnx,num-intr-inputs = <0xc>;
|
||||
} ;
|
||||
xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
|
||||
compatible = "xlnx,xps-timebase-wdt-1.00.b";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 2 0 1 2 >;
|
||||
reg = < 0x83a00000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,wdt-enable-once = <0>;
|
||||
xlnx,wdt-interval = <0x1e>;
|
||||
} ;
|
||||
xps_timer_1: timer@83c00000 {
|
||||
compatible = "xlnx,xps-timer-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 3 2 >;
|
||||
reg = < 0x83c00000 0x10000 >;
|
||||
xlnx,count-width = <0x20>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gen0-assert = <1>;
|
||||
xlnx,gen1-assert = <1>;
|
||||
xlnx,one-timer-only = <1>;
|
||||
xlnx,trig0-assert = <1>;
|
||||
xlnx,trig1-assert = <1>;
|
||||
} ;
|
||||
} ;
|
||||
} ;
|
||||
@@ -1,466 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Xilinx ML510 Reference Design support
|
||||
*
|
||||
* This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design.
|
||||
* The reference design contains a bug which prevent PCI DMA from working
|
||||
* properly. A description of the bug is given in the plbv46_pci section. It
|
||||
* needs to be fixed by the user until Xilinx updates their reference design.
|
||||
*
|
||||
* Copyright 2009, Roderick Colenbrander
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
|
||||
dcr-parent = <&ppc440_0>;
|
||||
DDR2_SDRAM_DIMM0: memory@0 {
|
||||
device_type = "memory";
|
||||
reg = < 0x0 0x20000000 >;
|
||||
} ;
|
||||
alias {
|
||||
ethernet0 = &Hard_Ethernet_MAC;
|
||||
serial0 = &RS232_Uart_1;
|
||||
} ;
|
||||
chosen {
|
||||
bootargs = "console=ttyS0 root=/dev/ram";
|
||||
stdout-path = "/plb@0/serial@83e00000";
|
||||
} ;
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#cpus = <0x1>;
|
||||
#size-cells = <0>;
|
||||
ppc440_0: cpu@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <300000000>;
|
||||
compatible = "PowerPC,440", "ibm,ppc440";
|
||||
d-cache-line-size = <0x20>;
|
||||
d-cache-size = <0x8000>;
|
||||
dcr-access-method = "native";
|
||||
dcr-controller ;
|
||||
device_type = "cpu";
|
||||
i-cache-line-size = <0x20>;
|
||||
i-cache-size = <0x8000>;
|
||||
model = "PowerPC,440";
|
||||
reg = <0>;
|
||||
timebase-frequency = <300000000>;
|
||||
xlnx,apu-control = <0x2000>;
|
||||
xlnx,apu-udi-0 = <0x0>;
|
||||
xlnx,apu-udi-1 = <0x0>;
|
||||
xlnx,apu-udi-10 = <0x0>;
|
||||
xlnx,apu-udi-11 = <0x0>;
|
||||
xlnx,apu-udi-12 = <0x0>;
|
||||
xlnx,apu-udi-13 = <0x0>;
|
||||
xlnx,apu-udi-14 = <0x0>;
|
||||
xlnx,apu-udi-15 = <0x0>;
|
||||
xlnx,apu-udi-2 = <0x0>;
|
||||
xlnx,apu-udi-3 = <0x0>;
|
||||
xlnx,apu-udi-4 = <0x0>;
|
||||
xlnx,apu-udi-5 = <0x0>;
|
||||
xlnx,apu-udi-6 = <0x0>;
|
||||
xlnx,apu-udi-7 = <0x0>;
|
||||
xlnx,apu-udi-8 = <0x0>;
|
||||
xlnx,apu-udi-9 = <0x0>;
|
||||
xlnx,dcr-autolock-enable = <0x1>;
|
||||
xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
|
||||
xlnx,dcu-rd-noncache-plb-prio = <0x0>;
|
||||
xlnx,dcu-rd-touch-plb-prio = <0x0>;
|
||||
xlnx,dcu-rd-urgent-plb-prio = <0x0>;
|
||||
xlnx,dcu-wr-flush-plb-prio = <0x0>;
|
||||
xlnx,dcu-wr-store-plb-prio = <0x0>;
|
||||
xlnx,dcu-wr-urgent-plb-prio = <0x0>;
|
||||
xlnx,dma0-control = <0x0>;
|
||||
xlnx,dma0-plb-prio = <0x0>;
|
||||
xlnx,dma0-rxchannelctrl = <0x1010000>;
|
||||
xlnx,dma0-rxirqtimer = <0x3ff>;
|
||||
xlnx,dma0-txchannelctrl = <0x1010000>;
|
||||
xlnx,dma0-txirqtimer = <0x3ff>;
|
||||
xlnx,dma1-control = <0x0>;
|
||||
xlnx,dma1-plb-prio = <0x0>;
|
||||
xlnx,dma1-rxchannelctrl = <0x1010000>;
|
||||
xlnx,dma1-rxirqtimer = <0x3ff>;
|
||||
xlnx,dma1-txchannelctrl = <0x1010000>;
|
||||
xlnx,dma1-txirqtimer = <0x3ff>;
|
||||
xlnx,dma2-control = <0x0>;
|
||||
xlnx,dma2-plb-prio = <0x0>;
|
||||
xlnx,dma2-rxchannelctrl = <0x1010000>;
|
||||
xlnx,dma2-rxirqtimer = <0x3ff>;
|
||||
xlnx,dma2-txchannelctrl = <0x1010000>;
|
||||
xlnx,dma2-txirqtimer = <0x3ff>;
|
||||
xlnx,dma3-control = <0x0>;
|
||||
xlnx,dma3-plb-prio = <0x0>;
|
||||
xlnx,dma3-rxchannelctrl = <0x1010000>;
|
||||
xlnx,dma3-rxirqtimer = <0x3ff>;
|
||||
xlnx,dma3-txchannelctrl = <0x1010000>;
|
||||
xlnx,dma3-txirqtimer = <0x3ff>;
|
||||
xlnx,endian-reset = <0x0>;
|
||||
xlnx,generate-plb-timespecs = <0x1>;
|
||||
xlnx,icu-rd-fetch-plb-prio = <0x0>;
|
||||
xlnx,icu-rd-spec-plb-prio = <0x0>;
|
||||
xlnx,icu-rd-touch-plb-prio = <0x0>;
|
||||
xlnx,interconnect-imask = <0xffffffff>;
|
||||
xlnx,mplb-allow-lock-xfer = <0x1>;
|
||||
xlnx,mplb-arb-mode = <0x0>;
|
||||
xlnx,mplb-awidth = <0x20>;
|
||||
xlnx,mplb-counter = <0x500>;
|
||||
xlnx,mplb-dwidth = <0x80>;
|
||||
xlnx,mplb-max-burst = <0x8>;
|
||||
xlnx,mplb-native-dwidth = <0x80>;
|
||||
xlnx,mplb-p2p = <0x0>;
|
||||
xlnx,mplb-prio-dcur = <0x2>;
|
||||
xlnx,mplb-prio-dcuw = <0x3>;
|
||||
xlnx,mplb-prio-icu = <0x4>;
|
||||
xlnx,mplb-prio-splb0 = <0x1>;
|
||||
xlnx,mplb-prio-splb1 = <0x0>;
|
||||
xlnx,mplb-read-pipe-enable = <0x1>;
|
||||
xlnx,mplb-sync-tattribute = <0x0>;
|
||||
xlnx,mplb-wdog-enable = <0x1>;
|
||||
xlnx,mplb-write-pipe-enable = <0x1>;
|
||||
xlnx,mplb-write-post-enable = <0x1>;
|
||||
xlnx,num-dma = <0x0>;
|
||||
xlnx,pir = <0xf>;
|
||||
xlnx,ppc440mc-addr-base = <0x0>;
|
||||
xlnx,ppc440mc-addr-high = <0x1fffffff>;
|
||||
xlnx,ppc440mc-arb-mode = <0x0>;
|
||||
xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
|
||||
xlnx,ppc440mc-control = <0xf810008f>;
|
||||
xlnx,ppc440mc-max-burst = <0x8>;
|
||||
xlnx,ppc440mc-prio-dcur = <0x2>;
|
||||
xlnx,ppc440mc-prio-dcuw = <0x3>;
|
||||
xlnx,ppc440mc-prio-icu = <0x4>;
|
||||
xlnx,ppc440mc-prio-splb0 = <0x1>;
|
||||
xlnx,ppc440mc-prio-splb1 = <0x0>;
|
||||
xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
|
||||
xlnx,ppcdm-asyncmode = <0x0>;
|
||||
xlnx,ppcds-asyncmode = <0x0>;
|
||||
xlnx,user-reset = <0x0>;
|
||||
} ;
|
||||
} ;
|
||||
plb_v46_0: plb@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
|
||||
ranges ;
|
||||
FLASH: flash@fc000000 {
|
||||
bank-width = <2>;
|
||||
compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
|
||||
reg = < 0xfc000000 0x2000000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,include-datawidth-matching-0 = <0x1>;
|
||||
xlnx,include-datawidth-matching-1 = <0x0>;
|
||||
xlnx,include-datawidth-matching-2 = <0x0>;
|
||||
xlnx,include-datawidth-matching-3 = <0x0>;
|
||||
xlnx,include-negedge-ioregs = <0x0>;
|
||||
xlnx,include-plb-ipif = <0x1>;
|
||||
xlnx,include-wrbuf = <0x1>;
|
||||
xlnx,max-mem-width = <0x10>;
|
||||
xlnx,mch-native-dwidth = <0x20>;
|
||||
xlnx,mch-plb-clk-period-ps = <0x2710>;
|
||||
xlnx,mch-splb-awidth = <0x20>;
|
||||
xlnx,mch0-accessbuf-depth = <0x10>;
|
||||
xlnx,mch0-protocol = <0x0>;
|
||||
xlnx,mch0-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch1-accessbuf-depth = <0x10>;
|
||||
xlnx,mch1-protocol = <0x0>;
|
||||
xlnx,mch1-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch2-accessbuf-depth = <0x10>;
|
||||
xlnx,mch2-protocol = <0x0>;
|
||||
xlnx,mch2-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch3-accessbuf-depth = <0x10>;
|
||||
xlnx,mch3-protocol = <0x0>;
|
||||
xlnx,mch3-rddatabuf-depth = <0x10>;
|
||||
xlnx,mem0-width = <0x10>;
|
||||
xlnx,mem1-width = <0x20>;
|
||||
xlnx,mem2-width = <0x20>;
|
||||
xlnx,mem3-width = <0x20>;
|
||||
xlnx,num-banks-mem = <0x1>;
|
||||
xlnx,num-channels = <0x2>;
|
||||
xlnx,priority-mode = <0x0>;
|
||||
xlnx,synch-mem-0 = <0x0>;
|
||||
xlnx,synch-mem-1 = <0x0>;
|
||||
xlnx,synch-mem-2 = <0x0>;
|
||||
xlnx,synch-mem-3 = <0x0>;
|
||||
xlnx,synch-pipedelay-0 = <0x2>;
|
||||
xlnx,synch-pipedelay-1 = <0x2>;
|
||||
xlnx,synch-pipedelay-2 = <0x2>;
|
||||
xlnx,synch-pipedelay-3 = <0x2>;
|
||||
xlnx,tavdv-ps-mem-0 = <0x1adb0>;
|
||||
xlnx,tavdv-ps-mem-1 = <0x3a98>;
|
||||
xlnx,tavdv-ps-mem-2 = <0x3a98>;
|
||||
xlnx,tavdv-ps-mem-3 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-0 = <0x1adb0>;
|
||||
xlnx,tcedv-ps-mem-1 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-2 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-3 = <0x3a98>;
|
||||
xlnx,thzce-ps-mem-0 = <0x88b8>;
|
||||
xlnx,thzce-ps-mem-1 = <0x1b58>;
|
||||
xlnx,thzce-ps-mem-2 = <0x1b58>;
|
||||
xlnx,thzce-ps-mem-3 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-0 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-1 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-2 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-3 = <0x1b58>;
|
||||
xlnx,tlzwe-ps-mem-0 = <0x88b8>;
|
||||
xlnx,tlzwe-ps-mem-1 = <0x0>;
|
||||
xlnx,tlzwe-ps-mem-2 = <0x0>;
|
||||
xlnx,tlzwe-ps-mem-3 = <0x0>;
|
||||
xlnx,twc-ps-mem-0 = <0x1adb0>;
|
||||
xlnx,twc-ps-mem-1 = <0x3a98>;
|
||||
xlnx,twc-ps-mem-2 = <0x3a98>;
|
||||
xlnx,twc-ps-mem-3 = <0x3a98>;
|
||||
xlnx,twp-ps-mem-0 = <0x11170>;
|
||||
xlnx,twp-ps-mem-1 = <0x2ee0>;
|
||||
xlnx,twp-ps-mem-2 = <0x2ee0>;
|
||||
xlnx,twp-ps-mem-3 = <0x2ee0>;
|
||||
xlnx,xcl0-linesize = <0x4>;
|
||||
xlnx,xcl0-writexfer = <0x1>;
|
||||
xlnx,xcl1-linesize = <0x4>;
|
||||
xlnx,xcl1-writexfer = <0x1>;
|
||||
xlnx,xcl2-linesize = <0x4>;
|
||||
xlnx,xcl2-writexfer = <0x1>;
|
||||
xlnx,xcl3-linesize = <0x4>;
|
||||
xlnx,xcl3-writexfer = <0x1>;
|
||||
} ;
|
||||
Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,compound";
|
||||
ethernet@81c00000 {
|
||||
compatible = "xlnx,xps-ll-temac-1.01.b";
|
||||
device_type = "network";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 8 2 >;
|
||||
llink-connected = <&Hard_Ethernet_MAC_fifo>;
|
||||
local-mac-address = [ 02 00 00 00 00 00 ];
|
||||
reg = < 0x81c00000 0x40 >;
|
||||
xlnx,bus2core-clk-ratio = <0x1>;
|
||||
xlnx,phy-type = <0x3>;
|
||||
xlnx,phyaddr = <0x1>;
|
||||
xlnx,rxcsum = <0x0>;
|
||||
xlnx,rxfifo = <0x8000>;
|
||||
xlnx,temac-type = <0x0>;
|
||||
xlnx,txcsum = <0x0>;
|
||||
xlnx,txfifo = <0x8000>;
|
||||
} ;
|
||||
} ;
|
||||
Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
|
||||
compatible = "xlnx,xps-ll-fifo-1.01.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 6 2 >;
|
||||
reg = < 0x81a00000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
} ;
|
||||
IIC_EEPROM: i2c@81600000 {
|
||||
compatible = "xlnx,xps-iic-2.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 9 2 >;
|
||||
reg = < 0x81600000 0x10000 >;
|
||||
xlnx,clk-freq = <0x5f5e100>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpo-width = <0x1>;
|
||||
xlnx,iic-freq = <0x186a0>;
|
||||
xlnx,scl-inertial-delay = <0x5>;
|
||||
xlnx,sda-inertial-delay = <0x5>;
|
||||
xlnx,ten-bit-adr = <0x0>;
|
||||
} ;
|
||||
LCD_OPTIONAL: gpio@81420000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
reg = < 0x81420000 0x10000 >;
|
||||
xlnx,all-inputs = <0x0>;
|
||||
xlnx,all-inputs-2 = <0x0>;
|
||||
xlnx,dout-default = <0x0>;
|
||||
xlnx,dout-default-2 = <0x0>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpio-width = <0xb>;
|
||||
xlnx,interrupt-present = <0x0>;
|
||||
xlnx,is-bidir = <0x1>;
|
||||
xlnx,is-bidir-2 = <0x1>;
|
||||
xlnx,is-dual = <0x0>;
|
||||
xlnx,tri-default = <0xffffffff>;
|
||||
xlnx,tri-default-2 = <0xffffffff>;
|
||||
} ;
|
||||
LEDs_4Bit: gpio@81400000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
reg = < 0x81400000 0x10000 >;
|
||||
xlnx,all-inputs = <0x0>;
|
||||
xlnx,all-inputs-2 = <0x0>;
|
||||
xlnx,dout-default = <0x0>;
|
||||
xlnx,dout-default-2 = <0x0>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpio-width = <0x4>;
|
||||
xlnx,interrupt-present = <0x0>;
|
||||
xlnx,is-bidir = <0x1>;
|
||||
xlnx,is-bidir-2 = <0x1>;
|
||||
xlnx,is-dual = <0x0>;
|
||||
xlnx,tri-default = <0xffffffff>;
|
||||
xlnx,tri-default-2 = <0xffffffff>;
|
||||
} ;
|
||||
RS232_Uart_1: serial@83e00000 {
|
||||
clock-frequency = <100000000>;
|
||||
compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
|
||||
current-speed = <9600>;
|
||||
device_type = "serial";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 11 2 >;
|
||||
reg = < 0x83e00000 0x10000 >;
|
||||
reg-offset = <0x1003>;
|
||||
reg-shift = <2>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,has-external-rclk = <0x0>;
|
||||
xlnx,has-external-xin = <0x0>;
|
||||
xlnx,is-a-16550 = <0x1>;
|
||||
} ;
|
||||
SPI_EEPROM: xps-spi@feff8000 {
|
||||
compatible = "xlnx,xps-spi-2.00.b";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 10 2 >;
|
||||
reg = < 0xfeff8000 0x80 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,fifo-exist = <0x1>;
|
||||
xlnx,num-ss-bits = <0x1>;
|
||||
xlnx,num-transfer-bits = <0x8>;
|
||||
xlnx,sck-ratio = <0x80>;
|
||||
} ;
|
||||
SysACE_CompactFlash: sysace@83600000 {
|
||||
compatible = "xlnx,xps-sysace-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 7 2 >;
|
||||
reg = < 0x83600000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,mem-width = <0x10>;
|
||||
} ;
|
||||
plbv46_pci_0: plbv46-pci@85e00000 {
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "xlnx,plbv46-pci-1.03.a";
|
||||
device_type = "pci";
|
||||
reg = < 0x85e00000 0x10000 >;
|
||||
|
||||
/*
|
||||
* The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to
|
||||
* 0 which means that a read/write to the memory mapped
|
||||
* i/o region (which starts at 0xa0000000) for pci
|
||||
* bar 0 on the plb side translates to 0.
|
||||
* It is important to set this value to 0xa0000000, so
|
||||
* that inbound and outbound pci transactions work
|
||||
* properly including DMA.
|
||||
*/
|
||||
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf0000000 0 0x00010000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IRQ mapping for pci slots and ALI M1533
|
||||
* periperhals. In total there are 5 interrupt
|
||||
* lines connected to a xps_intc controller.
|
||||
* Four of them are PCI IRQ A, B, C, D and
|
||||
* which correspond to respectively xpx_intc
|
||||
* 5, 4, 3 and 2. The fifth interrupt line is
|
||||
* connected to the south bridge and this one
|
||||
* uses irq 1 and is active high instead of
|
||||
* active low.
|
||||
*
|
||||
* The M1533 contains various peripherals
|
||||
* including AC97 audio, a modem, USB, IDE and
|
||||
* some power management stuff. The modem
|
||||
* isn't connected on the ML510 and the power
|
||||
* management core also isn't used.
|
||||
*/
|
||||
|
||||
/* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
|
||||
0x3000 0 0 1 &xps_intc_0 3 2
|
||||
0x3000 0 0 2 &xps_intc_0 2 2
|
||||
0x3000 0 0 3 &xps_intc_0 5 2
|
||||
0x3000 0 0 4 &xps_intc_0 4 2
|
||||
|
||||
/* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
|
||||
/*
|
||||
0x11800 0 0 1 &xps_intc_0 5 0 2
|
||||
0x11800 0 0 2 &xps_intc_0 4 0 2
|
||||
0x11800 0 0 3 &xps_intc_0 3 0 2
|
||||
0x11800 0 0 4 &xps_intc_0 2 0 2
|
||||
*/
|
||||
|
||||
/* According to the datasheet + schematic
|
||||
* ABCD [FPGA] of slot 5 is mapped to DABC.
|
||||
* Testing showed that at least A maps to B,
|
||||
* the mapping of the other pins is a guess
|
||||
* and for that reason the lines have been
|
||||
* commented out.
|
||||
*/
|
||||
/* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
|
||||
0x2800 0 0 1 &xps_intc_0 4 2
|
||||
/*
|
||||
0x2800 0 0 2 &xps_intc_0 3 2
|
||||
0x2800 0 0 3 &xps_intc_0 2 2
|
||||
0x2800 0 0 4 &xps_intc_0 5 2
|
||||
*/
|
||||
|
||||
/* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
|
||||
/*
|
||||
0x11000 0 0 1 &xps_intc_0 4 0 2
|
||||
0x11000 0 0 2 &xps_intc_0 3 0 2
|
||||
0x11000 0 0 3 &xps_intc_0 2 0 2
|
||||
0x11000 0 0 4 &xps_intc_0 5 0 2
|
||||
*/
|
||||
|
||||
/* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
|
||||
0x0800 0 0 1 &i8259 7 2
|
||||
|
||||
/* IDSEL 0x1b / dev=11, bus=0 / IDE */
|
||||
0x5800 0 0 1 &i8259 14 2
|
||||
|
||||
/* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
|
||||
0x7800 0 0 1 &i8259 7 2
|
||||
>;
|
||||
ali_m1533 {
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
i8259: interrupt-controller@20 {
|
||||
reg = <1 0x20 2
|
||||
1 0xa0 2
|
||||
1 0x4d0 2>;
|
||||
interrupt-controller;
|
||||
device_type = "interrupt-controller";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "chrp,iic";
|
||||
|
||||
/* south bridge irq is active high */
|
||||
interrupts = <1 3>;
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
};
|
||||
};
|
||||
} ;
|
||||
xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
|
||||
compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
|
||||
reg = < 0xffff0000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
} ;
|
||||
xps_intc_0: interrupt-controller@81800000 {
|
||||
#interrupt-cells = <0x2>;
|
||||
compatible = "xlnx,xps-intc-1.00.a";
|
||||
interrupt-controller ;
|
||||
reg = < 0x81800000 0x10000 >;
|
||||
xlnx,num-intr-inputs = <0xc>;
|
||||
} ;
|
||||
xps_tft_0: tft@86e00000 {
|
||||
compatible = "xlnx,xps-tft-1.00.a";
|
||||
reg = < 0x86e00000 0x10000 >;
|
||||
xlnx,dcr-splb-slave-if = <0x1>;
|
||||
xlnx,default-tft-base-addr = <0x0>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,i2c-slave-addr = <0x76>;
|
||||
xlnx,mplb-awidth = <0x20>;
|
||||
xlnx,mplb-dwidth = <0x80>;
|
||||
xlnx,mplb-native-dwidth = <0x40>;
|
||||
xlnx,mplb-smallest-slave = <0x20>;
|
||||
xlnx,tft-interface = <0x1>;
|
||||
} ;
|
||||
} ;
|
||||
} ;
|
||||
@@ -88,7 +88,6 @@ int serial_console_init(void);
|
||||
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
|
||||
int cpm_console_init(void *devp, struct serial_console_data *scdp);
|
||||
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp);
|
||||
int uartlite_console_init(void *devp, struct serial_console_data *scdp);
|
||||
int opal_console_init(void *devp, struct serial_console_data *scdp);
|
||||
void *simple_alloc_init(char *base, unsigned long heap_size,
|
||||
unsigned long granularity, unsigned long max_allocs);
|
||||
|
||||
@@ -132,11 +132,6 @@ int serial_console_init(void)
|
||||
else if (dt_is_compatible(devp, "fsl,mpc5200-psc-uart"))
|
||||
rc = mpc5200_psc_console_init(devp, &serial_cd);
|
||||
#endif
|
||||
#ifdef CONFIG_XILINX_VIRTEX
|
||||
else if (dt_is_compatible(devp, "xlnx,opb-uartlite-1.00.b") ||
|
||||
dt_is_compatible(devp, "xlnx,xps-uartlite-1.00.a"))
|
||||
rc = uartlite_console_init(devp, &serial_cd);
|
||||
#endif
|
||||
#ifdef CONFIG_PPC64_BOOT_WRAPPER
|
||||
else if (dt_is_compatible(devp, "ibm,opal-console-raw"))
|
||||
rc = opal_console_init(devp, &serial_cd);
|
||||
|
||||
@@ -1,79 +0,0 @@
|
||||
/*
|
||||
* Xilinx UARTLITE bootloader driver
|
||||
*
|
||||
* Copyright (C) 2007 Secret Lab Technologies Ltd.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "types.h"
|
||||
#include "string.h"
|
||||
#include "stdio.h"
|
||||
#include "io.h"
|
||||
#include "ops.h"
|
||||
|
||||
#define ULITE_RX 0x00
|
||||
#define ULITE_TX 0x04
|
||||
#define ULITE_STATUS 0x08
|
||||
#define ULITE_CONTROL 0x0c
|
||||
|
||||
#define ULITE_STATUS_RXVALID 0x01
|
||||
#define ULITE_STATUS_TXFULL 0x08
|
||||
|
||||
#define ULITE_CONTROL_RST_RX 0x02
|
||||
|
||||
static void * reg_base;
|
||||
|
||||
static int uartlite_open(void)
|
||||
{
|
||||
/* Clear the RX FIFO */
|
||||
out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void uartlite_putc(unsigned char c)
|
||||
{
|
||||
u32 reg = ULITE_STATUS_TXFULL;
|
||||
while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */
|
||||
reg = in_be32(reg_base + ULITE_STATUS);
|
||||
out_be32(reg_base + ULITE_TX, c);
|
||||
}
|
||||
|
||||
static unsigned char uartlite_getc(void)
|
||||
{
|
||||
u32 reg = 0;
|
||||
while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */
|
||||
reg = in_be32(reg_base + ULITE_STATUS);
|
||||
return in_be32(reg_base + ULITE_RX);
|
||||
}
|
||||
|
||||
static u8 uartlite_tstc(void)
|
||||
{
|
||||
u32 reg = in_be32(reg_base + ULITE_STATUS);
|
||||
return reg & ULITE_STATUS_RXVALID;
|
||||
}
|
||||
|
||||
int uartlite_console_init(void *devp, struct serial_console_data *scdp)
|
||||
{
|
||||
int n;
|
||||
unsigned long reg_phys;
|
||||
|
||||
n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base));
|
||||
if (n != sizeof(reg_base)) {
|
||||
if (!dt_xlate_reg(devp, 0, ®_phys, NULL))
|
||||
return -1;
|
||||
|
||||
reg_base = (void *)reg_phys;
|
||||
}
|
||||
|
||||
scdp->open = uartlite_open;
|
||||
scdp->putc = uartlite_putc;
|
||||
scdp->getc = uartlite_getc;
|
||||
scdp->tstc = uartlite_tstc;
|
||||
scdp->close = NULL;
|
||||
return 0;
|
||||
}
|
||||
@@ -1,97 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* The platform specific code for virtex devices since a boot loader is not
|
||||
* always used.
|
||||
*
|
||||
* (C) Copyright 2008 Xilinx, Inc.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "io.h"
|
||||
#include "stdio.h"
|
||||
|
||||
#define UART_DLL 0 /* Out: Divisor Latch Low */
|
||||
#define UART_DLM 1 /* Out: Divisor Latch High */
|
||||
#define UART_FCR 2 /* Out: FIFO Control Register */
|
||||
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
|
||||
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
|
||||
#define UART_LCR 3 /* Out: Line Control Register */
|
||||
#define UART_MCR 4 /* Out: Modem Control Register */
|
||||
#define UART_MCR_RTS 0x02 /* RTS complement */
|
||||
#define UART_MCR_DTR 0x01 /* DTR complement */
|
||||
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
||||
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
|
||||
|
||||
static int virtex_ns16550_console_init(void *devp)
|
||||
{
|
||||
unsigned char *reg_base;
|
||||
u32 reg_shift, reg_offset, clk, spd;
|
||||
u16 divisor;
|
||||
int n;
|
||||
|
||||
if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1)
|
||||
return -1;
|
||||
|
||||
n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset));
|
||||
if (n == sizeof(reg_offset))
|
||||
reg_base += reg_offset;
|
||||
|
||||
n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift));
|
||||
if (n != sizeof(reg_shift))
|
||||
reg_shift = 0;
|
||||
|
||||
n = getprop(devp, "current-speed", (void *)&spd, sizeof(spd));
|
||||
if (n != sizeof(spd))
|
||||
spd = 9600;
|
||||
|
||||
/* should there be a default clock rate?*/
|
||||
n = getprop(devp, "clock-frequency", (void *)&clk, sizeof(clk));
|
||||
if (n != sizeof(clk))
|
||||
return -1;
|
||||
|
||||
divisor = clk / (16 * spd);
|
||||
|
||||
/* Access baud rate */
|
||||
out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB);
|
||||
|
||||
/* Baud rate based on input clock */
|
||||
out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF);
|
||||
out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8);
|
||||
|
||||
/* 8 data, 1 stop, no parity */
|
||||
out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8);
|
||||
|
||||
/* RTS/DTR */
|
||||
out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR);
|
||||
|
||||
/* Clear transmitter and receiver */
|
||||
out_8(reg_base + (UART_FCR << reg_shift),
|
||||
UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* For virtex, the kernel may be loaded without using a bootloader and if so
|
||||
some UARTs need more setup than is provided in the normal console init
|
||||
*/
|
||||
int platform_specific_init(void)
|
||||
{
|
||||
void *devp;
|
||||
char devtype[MAX_PROP_LEN];
|
||||
char path[MAX_PATH_LEN];
|
||||
|
||||
devp = finddevice("/chosen");
|
||||
if (devp == NULL)
|
||||
return -1;
|
||||
|
||||
if (getprop(devp, "linux,stdout-path", path, MAX_PATH_LEN) > 0) {
|
||||
devp = finddevice(path);
|
||||
if (devp == NULL)
|
||||
return -1;
|
||||
|
||||
if ((getprop(devp, "device_type", devtype, sizeof(devtype)) > 0)
|
||||
&& !strcmp(devtype, "serial")
|
||||
&& (dt_is_compatible(devp, "ns16550")))
|
||||
virtex_ns16550_console_init(devp);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@@ -1,31 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#include "ppc_asm.h"
|
||||
|
||||
.text
|
||||
.global _zimage_start
|
||||
_zimage_start:
|
||||
|
||||
/* PPC errata 213: needed by Virtex-4 FX */
|
||||
mfccr0 0
|
||||
oris 0,0,0x50000000@h
|
||||
mtccr0 0
|
||||
|
||||
/*
|
||||
* Invalidate the data cache if the data cache is turned off.
|
||||
* - The 405 core does not invalidate the data cache on power-up
|
||||
* or reset but does turn off the data cache. We cannot assume
|
||||
* that the cache contents are valid.
|
||||
* - If the data cache is turned on this must have been done by
|
||||
* a bootloader and we assume that the cache contents are
|
||||
* valid.
|
||||
*/
|
||||
mfdccr r9
|
||||
cmplwi r9,0
|
||||
bne 2f
|
||||
lis r9,0
|
||||
li r8,256
|
||||
mtctr r8
|
||||
1: dccci r0,r9
|
||||
addi r9,r9,0x20
|
||||
bdnz 1b
|
||||
2: b _zimage_start_lib
|
||||
@@ -324,14 +324,6 @@ adder875-redboot)
|
||||
platformo="$object/fixed-head.o $object/redboot-8xx.o"
|
||||
binary=y
|
||||
;;
|
||||
simpleboot-virtex405-*)
|
||||
platformo="$object/virtex405-head.o $object/simpleboot.o $object/virtex.o"
|
||||
binary=y
|
||||
;;
|
||||
simpleboot-virtex440-*)
|
||||
platformo="$object/fixed-head.o $object/simpleboot.o $object/virtex.o"
|
||||
binary=y
|
||||
;;
|
||||
simpleboot-*)
|
||||
platformo="$object/fixed-head.o $object/simpleboot.o"
|
||||
binary=y
|
||||
|
||||
Reference in New Issue
Block a user