xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[MTD] Refactor NAND hwcontrol to cmd_ctrl

Browse Source 
The hwcontrol function enforced a step by step state machine
for any kind of hardware chip access. Let the hardware driver
know which control bits are set and inform it about a change
of the control lines. Let the hardware driver write out the
command and address bytes directly. This gives a peformance
advantage for address bus controlled chips and simplifies the
quirks in the hardware drivers.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Thomas Gleixner
2006-05-23 23:25:53 +02:00
parent 3821720d51
commit 7abd3ef987
18 changed files with 419 additions and 532 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/mtd/nand/edb7312.c
View File

@@ -73,32 +73,26 @@ static struct mtd_partition partition_info[] = {
/*
* hardware specific access to control-lines
*
* NAND_NCE: bit 0 -> bit 7
* NAND_CLE: bit 1 -> bit 4
* NAND_ALE: bit 2 -> bit 5
*/
static void ep7312_hwcontrol(struct mtd_info *mtd, int cmd)
static void ep7312_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
switch (cmd) {
struct nand_chip *chip = mtd->priv;
case NAND_CTL_SETCLE:
clps_writeb(clps_readb(ep7312_pxdr) | 0x10, ep7312_pxdr);
break;
case NAND_CTL_CLRCLE:
clps_writeb(clps_readb(ep7312_pxdr) & ~0x10, ep7312_pxdr);
break;
if (ctrl & NAND_CTRL_CHANGE) {
unsigned char bits;
case NAND_CTL_SETALE:
clps_writeb(clps_readb(ep7312_pxdr) | 0x20, ep7312_pxdr);
break;
case NAND_CTL_CLRALE:
clps_writeb(clps_readb(ep7312_pxdr) & ~0x20, ep7312_pxdr);
break;
bits = (ctrl & (NAND_CLE | NAND_ALE)) << 3;
bits = (ctrl & NAND_NCE) << 7;
case NAND_CTL_SETNCE:
clps_writeb((clps_readb(ep7312_pxdr) | 0x80) & ~0x40, ep7312_pxdr);
break;
case NAND_CTL_CLRNCE:
clps_writeb((clps_readb(ep7312_pxdr) | 0x80) | 0x40, ep7312_pxdr);
break;
clps_writeb((clps_readb(ep7312_pxdr) & 0xB0) | 0x10,
ep7312_pxdr);
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, chip->IO_ADDR_W);
}
/*
@@ -159,7 +153,7 @@ static int __init ep7312_init(void)
/* insert callbacks */
this->IO_ADDR_R = ep7312_fio_base;
this->IO_ADDR_W = ep7312_fio_base;
this->hwcontrol = ep7312_hwcontrol;
this->cmd_ctrl = ep7312_hwcontrol;
this->dev_ready = ep7312_device_ready;
/* 15 us command delay time */
this->chip_delay = 15;