QE: Move QE from arch/powerpc to drivers/soc
ls1 has qe and ls1 has arm cpu. move qe from arch/powerpc to drivers/soc/fsl to adapt to powerpc and arm Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Zhao Qiang
491
include/soc/fsl/qe/immap_qe.h
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491
include/soc/fsl/qe/immap_qe.h
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@@ -0,0 +1,491 @@
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/*
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* QUICC Engine (QE) Internal Memory Map.
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* The Internal Memory Map for devices with QE on them. This
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* is the superset of all QE devices (8360, etc.).
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* Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ASM_POWERPC_IMMAP_QE_H
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#define _ASM_POWERPC_IMMAP_QE_H
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#ifdef __KERNEL__
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#include <linux/kernel.h>
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#include <asm/io.h>
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#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
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/* QE I-RAM */
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struct qe_iram {
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__be32 iadd; /* I-RAM Address Register */
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__be32 idata; /* I-RAM Data Register */
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u8 res0[0x04];
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__be32 iready; /* I-RAM Ready Register */
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u8 res1[0x70];
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} __attribute__ ((packed));
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/* QE Interrupt Controller */
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struct qe_ic_regs {
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__be32 qicr;
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__be32 qivec;
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__be32 qripnr;
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__be32 qipnr;
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__be32 qipxcc;
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__be32 qipycc;
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__be32 qipwcc;
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__be32 qipzcc;
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__be32 qimr;
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__be32 qrimr;
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__be32 qicnr;
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u8 res0[0x4];
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__be32 qiprta;
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__be32 qiprtb;
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u8 res1[0x4];
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__be32 qricr;
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u8 res2[0x20];
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__be32 qhivec;
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u8 res3[0x1C];
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} __attribute__ ((packed));
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/* Communications Processor */
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struct cp_qe {
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__be32 cecr; /* QE command register */
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__be32 ceccr; /* QE controller configuration register */
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__be32 cecdr; /* QE command data register */
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u8 res0[0xA];
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__be16 ceter; /* QE timer event register */
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u8 res1[0x2];
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__be16 cetmr; /* QE timers mask register */
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__be32 cetscr; /* QE time-stamp timer control register */
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__be32 cetsr1; /* QE time-stamp register 1 */
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__be32 cetsr2; /* QE time-stamp register 2 */
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u8 res2[0x8];
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__be32 cevter; /* QE virtual tasks event register */
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__be32 cevtmr; /* QE virtual tasks mask register */
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__be16 cercr; /* QE RAM control register */
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u8 res3[0x2];
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u8 res4[0x24];
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__be16 ceexe1; /* QE external request 1 event register */
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u8 res5[0x2];
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__be16 ceexm1; /* QE external request 1 mask register */
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u8 res6[0x2];
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__be16 ceexe2; /* QE external request 2 event register */
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u8 res7[0x2];
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__be16 ceexm2; /* QE external request 2 mask register */
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u8 res8[0x2];
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__be16 ceexe3; /* QE external request 3 event register */
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u8 res9[0x2];
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__be16 ceexm3; /* QE external request 3 mask register */
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u8 res10[0x2];
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__be16 ceexe4; /* QE external request 4 event register */
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u8 res11[0x2];
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__be16 ceexm4; /* QE external request 4 mask register */
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u8 res12[0x3A];
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__be32 ceurnr; /* QE microcode revision number register */
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u8 res13[0x244];
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} __attribute__ ((packed));
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/* QE Multiplexer */
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struct qe_mux {
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__be32 cmxgcr; /* CMX general clock route register */
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__be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
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__be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
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__be32 cmxsi1syr; /* CMX SI1 SYNC route register */
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__be32 cmxucr[4]; /* CMX UCCx clock route registers */
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__be32 cmxupcr; /* CMX UPC clock route register */
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u8 res0[0x1C];
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} __attribute__ ((packed));
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/* QE Timers */
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struct qe_timers {
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u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
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u8 res0[0x3];
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u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
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u8 res1[0xB];
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__be16 gtmdr1; /* Timer 1 mode register */
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__be16 gtmdr2; /* Timer 2 mode register */
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__be16 gtrfr1; /* Timer 1 reference register */
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__be16 gtrfr2; /* Timer 2 reference register */
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__be16 gtcpr1; /* Timer 1 capture register */
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__be16 gtcpr2; /* Timer 2 capture register */
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__be16 gtcnr1; /* Timer 1 counter */
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__be16 gtcnr2; /* Timer 2 counter */
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__be16 gtmdr3; /* Timer 3 mode register */
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__be16 gtmdr4; /* Timer 4 mode register */
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__be16 gtrfr3; /* Timer 3 reference register */
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__be16 gtrfr4; /* Timer 4 reference register */
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__be16 gtcpr3; /* Timer 3 capture register */
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__be16 gtcpr4; /* Timer 4 capture register */
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__be16 gtcnr3; /* Timer 3 counter */
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__be16 gtcnr4; /* Timer 4 counter */
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__be16 gtevr1; /* Timer 1 event register */
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__be16 gtevr2; /* Timer 2 event register */
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__be16 gtevr3; /* Timer 3 event register */
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__be16 gtevr4; /* Timer 4 event register */
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__be16 gtps; /* Timer 1 prescale register */
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u8 res2[0x46];
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} __attribute__ ((packed));
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/* BRG */
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struct qe_brg {
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__be32 brgc[16]; /* BRG configuration registers */
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u8 res0[0x40];
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} __attribute__ ((packed));
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/* SPI */
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struct spi {
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u8 res0[0x20];
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__be32 spmode; /* SPI mode register */
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u8 res1[0x2];
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u8 spie; /* SPI event register */
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u8 res2[0x1];
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u8 res3[0x2];
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u8 spim; /* SPI mask register */
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u8 res4[0x1];
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u8 res5[0x1];
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u8 spcom; /* SPI command register */
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u8 res6[0x2];
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__be32 spitd; /* SPI transmit data register (cpu mode) */
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__be32 spird; /* SPI receive data register (cpu mode) */
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u8 res7[0x8];
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} __attribute__ ((packed));
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/* SI */
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struct si1 {
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__be16 siamr1; /* SI1 TDMA mode register */
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__be16 sibmr1; /* SI1 TDMB mode register */
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__be16 sicmr1; /* SI1 TDMC mode register */
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__be16 sidmr1; /* SI1 TDMD mode register */
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u8 siglmr1_h; /* SI1 global mode register high */
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u8 res0[0x1];
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u8 sicmdr1_h; /* SI1 command register high */
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u8 res2[0x1];
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u8 sistr1_h; /* SI1 status register high */
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u8 res3[0x1];
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__be16 sirsr1_h; /* SI1 RAM shadow address register high */
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u8 sitarc1; /* SI1 RAM counter Tx TDMA */
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u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
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u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
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u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
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u8 sirarc1; /* SI1 RAM counter Rx TDMA */
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u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
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u8 sircrc1; /* SI1 RAM counter Rx TDMC */
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u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
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u8 res4[0x8];
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__be16 siemr1; /* SI1 TDME mode register 16 bits */
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__be16 sifmr1; /* SI1 TDMF mode register 16 bits */
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__be16 sigmr1; /* SI1 TDMG mode register 16 bits */
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__be16 sihmr1; /* SI1 TDMH mode register 16 bits */
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u8 siglmg1_l; /* SI1 global mode register low 8 bits */
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u8 res5[0x1];
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u8 sicmdr1_l; /* SI1 command register low 8 bits */
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u8 res6[0x1];
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u8 sistr1_l; /* SI1 status register low 8 bits */
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u8 res7[0x1];
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__be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
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u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
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u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
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u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
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u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
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u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
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u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
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u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
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u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
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u8 res8[0x8];
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__be32 siml1; /* SI1 multiframe limit register */
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u8 siedm1; /* SI1 extended diagnostic mode register */
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u8 res9[0xBB];
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} __attribute__ ((packed));
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/* SI Routing Tables */
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struct sir {
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u8 tx[0x400];
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u8 rx[0x400];
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u8 res0[0x800];
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} __attribute__ ((packed));
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/* USB Controller */
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struct qe_usb_ctlr {
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u8 usb_usmod;
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u8 usb_usadr;
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u8 usb_uscom;
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u8 res1[1];
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__be16 usb_usep[4];
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u8 res2[4];
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__be16 usb_usber;
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u8 res3[2];
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__be16 usb_usbmr;
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u8 res4[1];
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u8 usb_usbs;
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__be16 usb_ussft;
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u8 res5[2];
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__be16 usb_usfrn;
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u8 res6[0x22];
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} __attribute__ ((packed));
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/* MCC */
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struct qe_mcc {
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__be32 mcce; /* MCC event register */
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__be32 mccm; /* MCC mask register */
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__be32 mccf; /* MCC configuration register */
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__be32 merl; /* MCC emergency request level register */
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u8 res0[0xF0];
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} __attribute__ ((packed));
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/* QE UCC Slow */
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struct ucc_slow {
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__be32 gumr_l; /* UCCx general mode register (low) */
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__be32 gumr_h; /* UCCx general mode register (high) */
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__be16 upsmr; /* UCCx protocol-specific mode register */
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u8 res0[0x2];
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__be16 utodr; /* UCCx transmit on demand register */
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__be16 udsr; /* UCCx data synchronization register */
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__be16 ucce; /* UCCx event register */
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u8 res1[0x2];
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__be16 uccm; /* UCCx mask register */
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u8 res2[0x1];
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u8 uccs; /* UCCx status register */
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u8 res3[0x24];
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__be16 utpt;
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u8 res4[0x52];
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u8 guemr; /* UCC general extended mode register */
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} __attribute__ ((packed));
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/* QE UCC Fast */
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struct ucc_fast {
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__be32 gumr; /* UCCx general mode register */
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__be32 upsmr; /* UCCx protocol-specific mode register */
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__be16 utodr; /* UCCx transmit on demand register */
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u8 res0[0x2];
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__be16 udsr; /* UCCx data synchronization register */
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u8 res1[0x2];
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__be32 ucce; /* UCCx event register */
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__be32 uccm; /* UCCx mask register */
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u8 uccs; /* UCCx status register */
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u8 res2[0x7];
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__be32 urfb; /* UCC receive FIFO base */
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__be16 urfs; /* UCC receive FIFO size */
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u8 res3[0x2];
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__be16 urfet; /* UCC receive FIFO emergency threshold */
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__be16 urfset; /* UCC receive FIFO special emergency
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threshold */
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__be32 utfb; /* UCC transmit FIFO base */
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__be16 utfs; /* UCC transmit FIFO size */
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u8 res4[0x2];
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__be16 utfet; /* UCC transmit FIFO emergency threshold */
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u8 res5[0x2];
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__be16 utftt; /* UCC transmit FIFO transmit threshold */
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u8 res6[0x2];
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__be16 utpt; /* UCC transmit polling timer */
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u8 res7[0x2];
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__be32 urtry; /* UCC retry counter register */
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u8 res8[0x4C];
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u8 guemr; /* UCC general extended mode register */
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} __attribute__ ((packed));
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struct ucc {
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union {
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struct ucc_slow slow;
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struct ucc_fast fast;
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u8 res[0x200]; /* UCC blocks are 512 bytes each */
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};
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} __attribute__ ((packed));
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/* MultiPHY UTOPIA POS Controllers (UPC) */
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struct upc {
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__be32 upgcr; /* UTOPIA/POS general configuration register */
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__be32 uplpa; /* UTOPIA/POS last PHY address */
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__be32 uphec; /* ATM HEC register */
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__be32 upuc; /* UTOPIA/POS UCC configuration */
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__be32 updc1; /* UTOPIA/POS device 1 configuration */
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__be32 updc2; /* UTOPIA/POS device 2 configuration */
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__be32 updc3; /* UTOPIA/POS device 3 configuration */
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__be32 updc4; /* UTOPIA/POS device 4 configuration */
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__be32 upstpa; /* UTOPIA/POS STPA threshold */
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u8 res0[0xC];
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__be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
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__be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
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__be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
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__be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
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__be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
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__be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
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__be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
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__be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
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__be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
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__be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
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__be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
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__be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
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__be32 upde1; /* UTOPIA/POS device 1 event */
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__be32 upde2; /* UTOPIA/POS device 2 event */
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__be32 upde3; /* UTOPIA/POS device 3 event */
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__be32 upde4; /* UTOPIA/POS device 4 event */
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__be16 uprp1;
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__be16 uprp2;
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__be16 uprp3;
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__be16 uprp4;
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u8 res1[0x8];
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__be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
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__be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
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__be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
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__be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
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__be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
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__be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
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__be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
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__be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
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__be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
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__be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
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__be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
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__be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
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__be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
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__be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
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__be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
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__be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
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__be32 uper1; /* Device 1 port enable register */
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__be32 uper2; /* Device 2 port enable register */
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__be32 uper3; /* Device 3 port enable register */
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__be32 uper4; /* Device 4 port enable register */
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u8 res2[0x150];
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} __attribute__ ((packed));
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/* SDMA */
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struct sdma {
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__be32 sdsr; /* Serial DMA status register */
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__be32 sdmr; /* Serial DMA mode register */
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__be32 sdtr1; /* SDMA system bus threshold register */
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__be32 sdtr2; /* SDMA secondary bus threshold register */
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__be32 sdhy1; /* SDMA system bus hysteresis register */
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__be32 sdhy2; /* SDMA secondary bus hysteresis register */
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__be32 sdta1; /* SDMA system bus address register */
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__be32 sdta2; /* SDMA secondary bus address register */
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__be32 sdtm1; /* SDMA system bus MSNUM register */
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__be32 sdtm2; /* SDMA secondary bus MSNUM register */
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u8 res0[0x10];
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__be32 sdaqr; /* SDMA address bus qualify register */
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__be32 sdaqmr; /* SDMA address bus qualify mask register */
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u8 res1[0x4];
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__be32 sdebcr; /* SDMA CAM entries base register */
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u8 res2[0x38];
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} __attribute__ ((packed));
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/* Debug Space */
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struct dbg {
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__be32 bpdcr; /* Breakpoint debug command register */
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__be32 bpdsr; /* Breakpoint debug status register */
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||||
__be32 bpdmr; /* Breakpoint debug mask register */
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__be32 bprmrr0; /* Breakpoint request mode risc register 0 */
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__be32 bprmrr1; /* Breakpoint request mode risc register 1 */
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u8 res0[0x8];
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__be32 bprmtr0; /* Breakpoint request mode trb register 0 */
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__be32 bprmtr1; /* Breakpoint request mode trb register 1 */
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u8 res1[0x8];
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__be32 bprmir; /* Breakpoint request mode immediate register */
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__be32 bprmsr; /* Breakpoint request mode serial register */
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__be32 bpemr; /* Breakpoint exit mode register */
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||||
u8 res2[0x48];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/*
|
||||
* RISC Special Registers (Trap and Breakpoint). These are described in
|
||||
* the QE Developer's Handbook.
|
||||
*/
|
||||
struct rsp {
|
||||
__be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
|
||||
u8 res0[64];
|
||||
__be32 ibcr0;
|
||||
__be32 ibs0;
|
||||
__be32 ibcnr0;
|
||||
u8 res1[4];
|
||||
__be32 ibcr1;
|
||||
__be32 ibs1;
|
||||
__be32 ibcnr1;
|
||||
__be32 npcr;
|
||||
__be32 dbcr;
|
||||
__be32 dbar;
|
||||
__be32 dbamr;
|
||||
__be32 dbsr;
|
||||
__be32 dbcnr;
|
||||
u8 res2[12];
|
||||
__be32 dbdr_h;
|
||||
__be32 dbdr_l;
|
||||
__be32 dbdmr_h;
|
||||
__be32 dbdmr_l;
|
||||
__be32 bsr;
|
||||
__be32 bor;
|
||||
__be32 bior;
|
||||
u8 res3[4];
|
||||
__be32 iatr[4];
|
||||
__be32 eccr; /* Exception control configuration register */
|
||||
__be32 eicr;
|
||||
u8 res4[0x100-0xf8];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct qe_immap {
|
||||
struct qe_iram iram; /* I-RAM */
|
||||
struct qe_ic_regs ic; /* Interrupt Controller */
|
||||
struct cp_qe cp; /* Communications Processor */
|
||||
struct qe_mux qmx; /* QE Multiplexer */
|
||||
struct qe_timers qet; /* QE Timers */
|
||||
struct spi spi[0x2]; /* spi */
|
||||
struct qe_mcc mcc; /* mcc */
|
||||
struct qe_brg brg; /* brg */
|
||||
struct qe_usb_ctlr usb; /* USB */
|
||||
struct si1 si1; /* SI */
|
||||
u8 res11[0x800];
|
||||
struct sir sir; /* SI Routing Tables */
|
||||
struct ucc ucc1; /* ucc1 */
|
||||
struct ucc ucc3; /* ucc3 */
|
||||
struct ucc ucc5; /* ucc5 */
|
||||
struct ucc ucc7; /* ucc7 */
|
||||
u8 res12[0x600];
|
||||
struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
|
||||
struct ucc ucc2; /* ucc2 */
|
||||
struct ucc ucc4; /* ucc4 */
|
||||
struct ucc ucc6; /* ucc6 */
|
||||
struct ucc ucc8; /* ucc8 */
|
||||
u8 res13[0x600];
|
||||
struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
|
||||
struct sdma sdma; /* SDMA */
|
||||
struct dbg dbg; /* 0x104080 - 0x1040FF
|
||||
Debug Space */
|
||||
struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
|
||||
RISC Special Registers
|
||||
(Trap and Breakpoint) */
|
||||
u8 res14[0x300]; /* 0x104300 - 0x1045FF */
|
||||
u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
|
||||
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
|
||||
u8 muram[0xC000]; /* 0x110000 - 0x11C000
|
||||
Multi-user RAM */
|
||||
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
|
||||
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
extern struct qe_immap __iomem *qe_immr;
|
||||
extern phys_addr_t get_qe_base(void);
|
||||
|
||||
/*
|
||||
* Returns the offset within the QE address space of the given pointer.
|
||||
*
|
||||
* Note that the QE does not support 36-bit physical addresses, so if
|
||||
* get_qe_base() returns a number above 4GB, the caller will probably fail.
|
||||
*/
|
||||
static inline phys_addr_t immrbar_virt_to_phys(void *address)
|
||||
{
|
||||
void *q = (void *)qe_immr;
|
||||
|
||||
/* Is it a MURAM address? */
|
||||
if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
|
||||
return get_qe_base() + (address - q);
|
||||
|
||||
/* It's an address returned by kmalloc */
|
||||
return virt_to_phys(address);
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_IMMAP_QE_H */
|
||||
790
include/soc/fsl/qe/qe.h
Normal file
790
include/soc/fsl/qe/qe.h
Normal file
@@ -0,0 +1,790 @@
|
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* Authors: Shlomi Gridish <gridish@freescale.com>
|
||||
* Li Yang <leoli@freescale.com>
|
||||
*
|
||||
* Description:
|
||||
* QUICC Engine (QE) external definitions and structure.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#ifndef _ASM_POWERPC_QE_H
|
||||
#define _ASM_POWERPC_QE_H
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/genalloc.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <asm/cpm.h>
|
||||
#include <soc/fsl/qe/immap_qe.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
|
||||
#define QE_NUM_OF_BRGS 16
|
||||
#define QE_NUM_OF_PORTS 1024
|
||||
|
||||
/* Memory partitions
|
||||
*/
|
||||
#define MEM_PART_SYSTEM 0
|
||||
#define MEM_PART_SECONDARY 1
|
||||
#define MEM_PART_MURAM 2
|
||||
|
||||
/* Clocks and BRGs */
|
||||
enum qe_clock {
|
||||
QE_CLK_NONE = 0,
|
||||
QE_BRG1, /* Baud Rate Generator 1 */
|
||||
QE_BRG2, /* Baud Rate Generator 2 */
|
||||
QE_BRG3, /* Baud Rate Generator 3 */
|
||||
QE_BRG4, /* Baud Rate Generator 4 */
|
||||
QE_BRG5, /* Baud Rate Generator 5 */
|
||||
QE_BRG6, /* Baud Rate Generator 6 */
|
||||
QE_BRG7, /* Baud Rate Generator 7 */
|
||||
QE_BRG8, /* Baud Rate Generator 8 */
|
||||
QE_BRG9, /* Baud Rate Generator 9 */
|
||||
QE_BRG10, /* Baud Rate Generator 10 */
|
||||
QE_BRG11, /* Baud Rate Generator 11 */
|
||||
QE_BRG12, /* Baud Rate Generator 12 */
|
||||
QE_BRG13, /* Baud Rate Generator 13 */
|
||||
QE_BRG14, /* Baud Rate Generator 14 */
|
||||
QE_BRG15, /* Baud Rate Generator 15 */
|
||||
QE_BRG16, /* Baud Rate Generator 16 */
|
||||
QE_CLK1, /* Clock 1 */
|
||||
QE_CLK2, /* Clock 2 */
|
||||
QE_CLK3, /* Clock 3 */
|
||||
QE_CLK4, /* Clock 4 */
|
||||
QE_CLK5, /* Clock 5 */
|
||||
QE_CLK6, /* Clock 6 */
|
||||
QE_CLK7, /* Clock 7 */
|
||||
QE_CLK8, /* Clock 8 */
|
||||
QE_CLK9, /* Clock 9 */
|
||||
QE_CLK10, /* Clock 10 */
|
||||
QE_CLK11, /* Clock 11 */
|
||||
QE_CLK12, /* Clock 12 */
|
||||
QE_CLK13, /* Clock 13 */
|
||||
QE_CLK14, /* Clock 14 */
|
||||
QE_CLK15, /* Clock 15 */
|
||||
QE_CLK16, /* Clock 16 */
|
||||
QE_CLK17, /* Clock 17 */
|
||||
QE_CLK18, /* Clock 18 */
|
||||
QE_CLK19, /* Clock 19 */
|
||||
QE_CLK20, /* Clock 20 */
|
||||
QE_CLK21, /* Clock 21 */
|
||||
QE_CLK22, /* Clock 22 */
|
||||
QE_CLK23, /* Clock 23 */
|
||||
QE_CLK24, /* Clock 24 */
|
||||
QE_CLK_DUMMY
|
||||
};
|
||||
|
||||
static inline bool qe_clock_is_brg(enum qe_clock clk)
|
||||
{
|
||||
return clk >= QE_BRG1 && clk <= QE_BRG16;
|
||||
}
|
||||
|
||||
extern spinlock_t cmxgcr_lock;
|
||||
|
||||
/* Export QE common operations */
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
extern void qe_reset(void);
|
||||
#else
|
||||
static inline void qe_reset(void) {}
|
||||
#endif
|
||||
|
||||
int cpm_muram_init(void);
|
||||
|
||||
#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
|
||||
unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
|
||||
int cpm_muram_free(unsigned long offset);
|
||||
unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
|
||||
unsigned long cpm_muram_alloc_common(unsigned long size, genpool_algo_t algo,
|
||||
void *data);
|
||||
void __iomem *cpm_muram_addr(unsigned long offset);
|
||||
unsigned long cpm_muram_offset(void __iomem *addr);
|
||||
dma_addr_t cpm_muram_dma(void __iomem *addr);
|
||||
#else
|
||||
static inline unsigned long cpm_muram_alloc(unsigned long size,
|
||||
unsigned long align)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int cpm_muram_free(unsigned long offset)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
|
||||
unsigned long size)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline void __iomem *cpm_muram_addr(unsigned long offset)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline unsigned long cpm_muram_offset(void __iomem *addr)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
|
||||
|
||||
/* QE PIO */
|
||||
#define QE_PIO_PINS 32
|
||||
|
||||
struct qe_pio_regs {
|
||||
__be32 cpodr; /* Open drain register */
|
||||
__be32 cpdata; /* Data register */
|
||||
__be32 cpdir1; /* Direction register */
|
||||
__be32 cpdir2; /* Direction register */
|
||||
__be32 cppar1; /* Pin assignment register */
|
||||
__be32 cppar2; /* Pin assignment register */
|
||||
#ifdef CONFIG_PPC_85xx
|
||||
u8 pad[8];
|
||||
#endif
|
||||
};
|
||||
|
||||
#define QE_PIO_DIR_IN 2
|
||||
#define QE_PIO_DIR_OUT 1
|
||||
extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
|
||||
int dir, int open_drain, int assignment,
|
||||
int has_irq);
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
extern int par_io_init(struct device_node *np);
|
||||
extern int par_io_of_config(struct device_node *np);
|
||||
extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
|
||||
int assignment, int has_irq);
|
||||
extern int par_io_data_set(u8 port, u8 pin, u8 val);
|
||||
#else
|
||||
static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
|
||||
static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
|
||||
static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
|
||||
int assignment, int has_irq) { return -ENOSYS; }
|
||||
static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
|
||||
/*
|
||||
* Pin multiplexing functions.
|
||||
*/
|
||||
struct qe_pin;
|
||||
#ifdef CONFIG_QE_GPIO
|
||||
extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
|
||||
extern void qe_pin_free(struct qe_pin *qe_pin);
|
||||
extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
|
||||
extern void qe_pin_set_dedicated(struct qe_pin *pin);
|
||||
#else
|
||||
static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
static inline void qe_pin_free(struct qe_pin *qe_pin) {}
|
||||
static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
|
||||
static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
|
||||
#endif /* CONFIG_QE_GPIO */
|
||||
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
|
||||
#else
|
||||
static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
|
||||
u32 cmd_input)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
|
||||
/* QE internal API */
|
||||
enum qe_clock qe_clock_source(const char *source);
|
||||
unsigned int qe_get_brg_clk(void);
|
||||
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
|
||||
int qe_get_snum(void);
|
||||
void qe_put_snum(u8 snum);
|
||||
unsigned int qe_get_num_of_risc(void);
|
||||
unsigned int qe_get_num_of_snums(void);
|
||||
|
||||
static inline int qe_alive_during_sleep(void)
|
||||
{
|
||||
/*
|
||||
* MPC8568E reference manual says:
|
||||
*
|
||||
* "...power down sequence waits for all I/O interfaces to become idle.
|
||||
* In some applications this may happen eventually without actively
|
||||
* shutting down interfaces, but most likely, software will have to
|
||||
* take steps to shut down the eTSEC, QUICC Engine Block, and PCI
|
||||
* interfaces before issuing the command (either the write to the core
|
||||
* MSR[WE] as described above or writing to POWMGTCSR) to put the
|
||||
* device into sleep state."
|
||||
*
|
||||
* MPC8569E reference manual has a similar paragraph.
|
||||
*/
|
||||
#ifdef CONFIG_PPC_85xx
|
||||
return 0;
|
||||
#else
|
||||
return 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* we actually use cpm_muram implementation, define this for convenience */
|
||||
#define qe_muram_init cpm_muram_init
|
||||
#define qe_muram_alloc cpm_muram_alloc
|
||||
#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
|
||||
#define qe_muram_free cpm_muram_free
|
||||
#define qe_muram_addr cpm_muram_addr
|
||||
#define qe_muram_offset cpm_muram_offset
|
||||
|
||||
/* Structure that defines QE firmware binary files.
|
||||
*
|
||||
* See Documentation/powerpc/qe_firmware.txt for a description of these
|
||||
* fields.
|
||||
*/
|
||||
struct qe_firmware {
|
||||
struct qe_header {
|
||||
__be32 length; /* Length of the entire structure, in bytes */
|
||||
u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
|
||||
u8 version; /* Version of this layout. First ver is '1' */
|
||||
} header;
|
||||
u8 id[62]; /* Null-terminated identifier string */
|
||||
u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
|
||||
u8 count; /* Number of microcode[] structures */
|
||||
struct {
|
||||
__be16 model; /* The SOC model */
|
||||
u8 major; /* The SOC revision major */
|
||||
u8 minor; /* The SOC revision minor */
|
||||
} __attribute__ ((packed)) soc;
|
||||
u8 padding[4]; /* Reserved, for alignment */
|
||||
__be64 extended_modes; /* Extended modes */
|
||||
__be32 vtraps[8]; /* Virtual trap addresses */
|
||||
u8 reserved[4]; /* Reserved, for future expansion */
|
||||
struct qe_microcode {
|
||||
u8 id[32]; /* Null-terminated identifier */
|
||||
__be32 traps[16]; /* Trap addresses, 0 == ignore */
|
||||
__be32 eccr; /* The value for the ECCR register */
|
||||
__be32 iram_offset; /* Offset into I-RAM for the code */
|
||||
__be32 count; /* Number of 32-bit words of the code */
|
||||
__be32 code_offset; /* Offset of the actual microcode */
|
||||
u8 major; /* The microcode version major */
|
||||
u8 minor; /* The microcode version minor */
|
||||
u8 revision; /* The microcode version revision */
|
||||
u8 padding; /* Reserved, for alignment */
|
||||
u8 reserved[4]; /* Reserved, for future expansion */
|
||||
} __attribute__ ((packed)) microcode[1];
|
||||
/* All microcode binaries should be located here */
|
||||
/* CRC32 should be located here, after the microcode binaries */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct qe_firmware_info {
|
||||
char id[64]; /* Firmware name */
|
||||
u32 vtraps[8]; /* Virtual trap addresses */
|
||||
u64 extended_modes; /* Extended modes */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
/* Upload a firmware to the QE */
|
||||
int qe_upload_firmware(const struct qe_firmware *firmware);
|
||||
#else
|
||||
static inline int qe_upload_firmware(const struct qe_firmware *firmware)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
|
||||
/* Obtain information on the uploaded firmware */
|
||||
struct qe_firmware_info *qe_get_firmware_info(void);
|
||||
|
||||
/* QE USB */
|
||||
int qe_usb_clock_set(enum qe_clock clk, int rate);
|
||||
|
||||
/* Buffer descriptors */
|
||||
struct qe_bd {
|
||||
__be16 status;
|
||||
__be16 length;
|
||||
__be32 buf;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define BD_STATUS_MASK 0xffff0000
|
||||
#define BD_LENGTH_MASK 0x0000ffff
|
||||
|
||||
/* Alignment */
|
||||
#define QE_INTR_TABLE_ALIGN 16 /* ??? */
|
||||
#define QE_ALIGNMENT_OF_BD 8
|
||||
#define QE_ALIGNMENT_OF_PRAM 64
|
||||
|
||||
/* RISC allocation */
|
||||
#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
|
||||
#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
|
||||
#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
|
||||
#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
|
||||
#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
|
||||
QE_RISC_ALLOCATION_RISC2)
|
||||
#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
|
||||
QE_RISC_ALLOCATION_RISC2 | \
|
||||
QE_RISC_ALLOCATION_RISC3 | \
|
||||
QE_RISC_ALLOCATION_RISC4)
|
||||
|
||||
/* QE extended filtering Table Lookup Key Size */
|
||||
enum qe_fltr_tbl_lookup_key_size {
|
||||
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
|
||||
= 0x3f, /* LookupKey parsed by the Generate LookupKey
|
||||
CMD is truncated to 8 bytes */
|
||||
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
|
||||
= 0x5f, /* LookupKey parsed by the Generate LookupKey
|
||||
CMD is truncated to 16 bytes */
|
||||
};
|
||||
|
||||
/* QE FLTR extended filtering Largest External Table Lookup Key Size */
|
||||
enum qe_fltr_largest_external_tbl_lookup_key_size {
|
||||
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
|
||||
= 0x0,/* not used */
|
||||
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
|
||||
= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
|
||||
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
|
||||
= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
|
||||
};
|
||||
|
||||
/* structure representing QE parameter RAM */
|
||||
struct qe_timer_tables {
|
||||
u16 tm_base; /* QE timer table base adr */
|
||||
u16 tm_ptr; /* QE timer table pointer */
|
||||
u16 r_tmr; /* QE timer mode register */
|
||||
u16 r_tmv; /* QE timer valid register */
|
||||
u32 tm_cmd; /* QE timer cmd register */
|
||||
u32 tm_cnt; /* QE timer internal cnt */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define QE_FLTR_TAD_SIZE 8
|
||||
|
||||
/* QE extended filtering Termination Action Descriptor (TAD) */
|
||||
struct qe_fltr_tad {
|
||||
u8 serialized[QE_FLTR_TAD_SIZE];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* Communication Direction */
|
||||
enum comm_dir {
|
||||
COMM_DIR_NONE = 0,
|
||||
COMM_DIR_RX = 1,
|
||||
COMM_DIR_TX = 2,
|
||||
COMM_DIR_RX_AND_TX = 3
|
||||
};
|
||||
|
||||
/* QE CMXUCR Registers.
|
||||
* There are two UCCs represented in each of the four CMXUCR registers.
|
||||
* These values are for the UCC in the LSBs
|
||||
*/
|
||||
#define QE_CMXUCR_MII_ENET_MNG 0x00007000
|
||||
#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
|
||||
#define QE_CMXUCR_GRANT 0x00008000
|
||||
#define QE_CMXUCR_TSA 0x00004000
|
||||
#define QE_CMXUCR_BKPT 0x00000100
|
||||
#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
|
||||
|
||||
/* QE CMXGCR Registers.
|
||||
*/
|
||||
#define QE_CMXGCR_MII_ENET_MNG 0x00007000
|
||||
#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
|
||||
#define QE_CMXGCR_USBCS 0x0000000f
|
||||
#define QE_CMXGCR_USBCS_CLK3 0x1
|
||||
#define QE_CMXGCR_USBCS_CLK5 0x2
|
||||
#define QE_CMXGCR_USBCS_CLK7 0x3
|
||||
#define QE_CMXGCR_USBCS_CLK9 0x4
|
||||
#define QE_CMXGCR_USBCS_CLK13 0x5
|
||||
#define QE_CMXGCR_USBCS_CLK17 0x6
|
||||
#define QE_CMXGCR_USBCS_CLK19 0x7
|
||||
#define QE_CMXGCR_USBCS_CLK21 0x8
|
||||
#define QE_CMXGCR_USBCS_BRG9 0x9
|
||||
#define QE_CMXGCR_USBCS_BRG10 0xa
|
||||
|
||||
/* QE CECR Commands.
|
||||
*/
|
||||
#define QE_CR_FLG 0x00010000
|
||||
#define QE_RESET 0x80000000
|
||||
#define QE_INIT_TX_RX 0x00000000
|
||||
#define QE_INIT_RX 0x00000001
|
||||
#define QE_INIT_TX 0x00000002
|
||||
#define QE_ENTER_HUNT_MODE 0x00000003
|
||||
#define QE_STOP_TX 0x00000004
|
||||
#define QE_GRACEFUL_STOP_TX 0x00000005
|
||||
#define QE_RESTART_TX 0x00000006
|
||||
#define QE_CLOSE_RX_BD 0x00000007
|
||||
#define QE_SWITCH_COMMAND 0x00000007
|
||||
#define QE_SET_GROUP_ADDRESS 0x00000008
|
||||
#define QE_START_IDMA 0x00000009
|
||||
#define QE_MCC_STOP_RX 0x00000009
|
||||
#define QE_ATM_TRANSMIT 0x0000000a
|
||||
#define QE_HPAC_CLEAR_ALL 0x0000000b
|
||||
#define QE_GRACEFUL_STOP_RX 0x0000001a
|
||||
#define QE_RESTART_RX 0x0000001b
|
||||
#define QE_HPAC_SET_PRIORITY 0x0000010b
|
||||
#define QE_HPAC_STOP_TX 0x0000020b
|
||||
#define QE_HPAC_STOP_RX 0x0000030b
|
||||
#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
|
||||
#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
|
||||
#define QE_HPAC_START_TX 0x0000060b
|
||||
#define QE_HPAC_START_RX 0x0000070b
|
||||
#define QE_USB_STOP_TX 0x0000000a
|
||||
#define QE_USB_RESTART_TX 0x0000000c
|
||||
#define QE_QMC_STOP_TX 0x0000000c
|
||||
#define QE_QMC_STOP_RX 0x0000000d
|
||||
#define QE_SS7_SU_FIL_RESET 0x0000000e
|
||||
/* jonathbr added from here down for 83xx */
|
||||
#define QE_RESET_BCS 0x0000000a
|
||||
#define QE_MCC_INIT_TX_RX_16 0x00000003
|
||||
#define QE_MCC_STOP_TX 0x00000004
|
||||
#define QE_MCC_INIT_TX_1 0x00000005
|
||||
#define QE_MCC_INIT_RX_1 0x00000006
|
||||
#define QE_MCC_RESET 0x00000007
|
||||
#define QE_SET_TIMER 0x00000008
|
||||
#define QE_RANDOM_NUMBER 0x0000000c
|
||||
#define QE_ATM_MULTI_THREAD_INIT 0x00000011
|
||||
#define QE_ASSIGN_PAGE 0x00000012
|
||||
#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
|
||||
#define QE_START_FLOW_CONTROL 0x00000014
|
||||
#define QE_STOP_FLOW_CONTROL 0x00000015
|
||||
#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
|
||||
|
||||
#define QE_ASSIGN_RISC 0x00000010
|
||||
#define QE_CR_MCN_NORMAL_SHIFT 6
|
||||
#define QE_CR_MCN_USB_SHIFT 4
|
||||
#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
|
||||
#define QE_CR_SNUM_SHIFT 17
|
||||
|
||||
/* QE CECR Sub Block - sub block of QE command.
|
||||
*/
|
||||
#define QE_CR_SUBBLOCK_INVALID 0x00000000
|
||||
#define QE_CR_SUBBLOCK_USB 0x03200000
|
||||
#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
|
||||
#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
|
||||
#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
|
||||
#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
|
||||
#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
|
||||
#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
|
||||
#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
|
||||
#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
|
||||
#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
|
||||
#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
|
||||
#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
|
||||
#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
|
||||
#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
|
||||
#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
|
||||
#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
|
||||
#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
|
||||
#define QE_CR_SUBBLOCK_MCC1 0x03800000
|
||||
#define QE_CR_SUBBLOCK_MCC2 0x03a00000
|
||||
#define QE_CR_SUBBLOCK_MCC3 0x03000000
|
||||
#define QE_CR_SUBBLOCK_IDMA1 0x02800000
|
||||
#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
|
||||
#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
|
||||
#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
|
||||
#define QE_CR_SUBBLOCK_HPAC 0x01e00000
|
||||
#define QE_CR_SUBBLOCK_SPI1 0x01400000
|
||||
#define QE_CR_SUBBLOCK_SPI2 0x01600000
|
||||
#define QE_CR_SUBBLOCK_RAND 0x01c00000
|
||||
#define QE_CR_SUBBLOCK_TIMER 0x01e00000
|
||||
#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
|
||||
|
||||
/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
|
||||
#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
|
||||
#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
|
||||
#define QE_CR_PROTOCOL_QMC 0x02
|
||||
#define QE_CR_PROTOCOL_UART 0x04
|
||||
#define QE_CR_PROTOCOL_ATM_POS 0x0A
|
||||
#define QE_CR_PROTOCOL_ETHERNET 0x0C
|
||||
#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
|
||||
|
||||
/* BRG configuration register */
|
||||
#define QE_BRGC_ENABLE 0x00010000
|
||||
#define QE_BRGC_DIVISOR_SHIFT 1
|
||||
#define QE_BRGC_DIVISOR_MAX 0xFFF
|
||||
#define QE_BRGC_DIV16 1
|
||||
|
||||
/* QE Timers registers */
|
||||
#define QE_GTCFR1_PCAS 0x80
|
||||
#define QE_GTCFR1_STP2 0x20
|
||||
#define QE_GTCFR1_RST2 0x10
|
||||
#define QE_GTCFR1_GM2 0x08
|
||||
#define QE_GTCFR1_GM1 0x04
|
||||
#define QE_GTCFR1_STP1 0x02
|
||||
#define QE_GTCFR1_RST1 0x01
|
||||
|
||||
/* SDMA registers */
|
||||
#define QE_SDSR_BER1 0x02000000
|
||||
#define QE_SDSR_BER2 0x01000000
|
||||
|
||||
#define QE_SDMR_GLB_1_MSK 0x80000000
|
||||
#define QE_SDMR_ADR_SEL 0x20000000
|
||||
#define QE_SDMR_BER1_MSK 0x02000000
|
||||
#define QE_SDMR_BER2_MSK 0x01000000
|
||||
#define QE_SDMR_EB1_MSK 0x00800000
|
||||
#define QE_SDMR_ER1_MSK 0x00080000
|
||||
#define QE_SDMR_ER2_MSK 0x00040000
|
||||
#define QE_SDMR_CEN_MASK 0x0000E000
|
||||
#define QE_SDMR_SBER_1 0x00000200
|
||||
#define QE_SDMR_SBER_2 0x00000200
|
||||
#define QE_SDMR_EB1_PR_MASK 0x000000C0
|
||||
#define QE_SDMR_ER1_PR 0x00000008
|
||||
|
||||
#define QE_SDMR_CEN_SHIFT 13
|
||||
#define QE_SDMR_EB1_PR_SHIFT 6
|
||||
|
||||
#define QE_SDTM_MSNUM_SHIFT 24
|
||||
|
||||
#define QE_SDEBCR_BA_MASK 0x01FFFFFF
|
||||
|
||||
/* Communication Processor */
|
||||
#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
|
||||
#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
|
||||
#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
|
||||
|
||||
/* I-RAM */
|
||||
#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
|
||||
#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
|
||||
#define QE_IRAM_READY 0x80000000 /* Ready */
|
||||
|
||||
/* UPC */
|
||||
#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
|
||||
#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
|
||||
#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
|
||||
#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
|
||||
#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
|
||||
|
||||
/* UCC GUEMR register */
|
||||
#define UCC_GUEMR_MODE_MASK_RX 0x02
|
||||
#define UCC_GUEMR_MODE_FAST_RX 0x02
|
||||
#define UCC_GUEMR_MODE_SLOW_RX 0x00
|
||||
#define UCC_GUEMR_MODE_MASK_TX 0x01
|
||||
#define UCC_GUEMR_MODE_FAST_TX 0x01
|
||||
#define UCC_GUEMR_MODE_SLOW_TX 0x00
|
||||
#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
|
||||
#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
|
||||
must be set 1 */
|
||||
|
||||
/* structure representing UCC SLOW parameter RAM */
|
||||
struct ucc_slow_pram {
|
||||
__be16 rbase; /* RX BD base address */
|
||||
__be16 tbase; /* TX BD base address */
|
||||
u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
|
||||
u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
|
||||
__be16 mrblr; /* Rx buffer length */
|
||||
__be32 rstate; /* Rx internal state */
|
||||
__be32 rptr; /* Rx internal data pointer */
|
||||
__be16 rbptr; /* rb BD Pointer */
|
||||
__be16 rcount; /* Rx internal byte count */
|
||||
__be32 rtemp; /* Rx temp */
|
||||
__be32 tstate; /* Tx internal state */
|
||||
__be32 tptr; /* Tx internal data pointer */
|
||||
__be16 tbptr; /* Tx BD pointer */
|
||||
__be16 tcount; /* Tx byte count */
|
||||
__be32 ttemp; /* Tx temp */
|
||||
__be32 rcrc; /* temp receive CRC */
|
||||
__be32 tcrc; /* temp transmit CRC */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
|
||||
#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
|
||||
#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
|
||||
#define UCC_SLOW_GUMR_H_REVD 0x00002000
|
||||
#define UCC_SLOW_GUMR_H_TRX 0x00001000
|
||||
#define UCC_SLOW_GUMR_H_TTX 0x00000800
|
||||
#define UCC_SLOW_GUMR_H_CDP 0x00000400
|
||||
#define UCC_SLOW_GUMR_H_CTSP 0x00000200
|
||||
#define UCC_SLOW_GUMR_H_CDS 0x00000100
|
||||
#define UCC_SLOW_GUMR_H_CTSS 0x00000080
|
||||
#define UCC_SLOW_GUMR_H_TFL 0x00000040
|
||||
#define UCC_SLOW_GUMR_H_RFW 0x00000020
|
||||
#define UCC_SLOW_GUMR_H_TXSY 0x00000010
|
||||
#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
|
||||
#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
|
||||
#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
|
||||
#define UCC_SLOW_GUMR_H_RTSM 0x00000002
|
||||
#define UCC_SLOW_GUMR_H_RSYN 0x00000001
|
||||
|
||||
#define UCC_SLOW_GUMR_L_TCI 0x10000000
|
||||
#define UCC_SLOW_GUMR_L_RINV 0x02000000
|
||||
#define UCC_SLOW_GUMR_L_TINV 0x01000000
|
||||
#define UCC_SLOW_GUMR_L_TEND 0x00040000
|
||||
#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
|
||||
#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
|
||||
#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
|
||||
#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
|
||||
#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
|
||||
#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
|
||||
#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
|
||||
#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
|
||||
#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
|
||||
#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
|
||||
#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
|
||||
#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
|
||||
#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
|
||||
#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
|
||||
#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
|
||||
#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
|
||||
#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
|
||||
#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
|
||||
#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
|
||||
#define UCC_SLOW_GUMR_L_ENR 0x00000020
|
||||
#define UCC_SLOW_GUMR_L_ENT 0x00000010
|
||||
#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
|
||||
#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
|
||||
#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
|
||||
#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
|
||||
#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
|
||||
|
||||
/* General UCC FAST Mode Register */
|
||||
#define UCC_FAST_GUMR_TCI 0x20000000
|
||||
#define UCC_FAST_GUMR_TRX 0x10000000
|
||||
#define UCC_FAST_GUMR_TTX 0x08000000
|
||||
#define UCC_FAST_GUMR_CDP 0x04000000
|
||||
#define UCC_FAST_GUMR_CTSP 0x02000000
|
||||
#define UCC_FAST_GUMR_CDS 0x01000000
|
||||
#define UCC_FAST_GUMR_CTSS 0x00800000
|
||||
#define UCC_FAST_GUMR_TXSY 0x00020000
|
||||
#define UCC_FAST_GUMR_RSYN 0x00010000
|
||||
#define UCC_FAST_GUMR_RTSM 0x00002000
|
||||
#define UCC_FAST_GUMR_REVD 0x00000400
|
||||
#define UCC_FAST_GUMR_ENR 0x00000020
|
||||
#define UCC_FAST_GUMR_ENT 0x00000010
|
||||
|
||||
/* UART Slow UCC Event Register (UCCE) */
|
||||
#define UCC_UART_UCCE_AB 0x0200
|
||||
#define UCC_UART_UCCE_IDLE 0x0100
|
||||
#define UCC_UART_UCCE_GRA 0x0080
|
||||
#define UCC_UART_UCCE_BRKE 0x0040
|
||||
#define UCC_UART_UCCE_BRKS 0x0020
|
||||
#define UCC_UART_UCCE_CCR 0x0008
|
||||
#define UCC_UART_UCCE_BSY 0x0004
|
||||
#define UCC_UART_UCCE_TX 0x0002
|
||||
#define UCC_UART_UCCE_RX 0x0001
|
||||
|
||||
/* HDLC Slow UCC Event Register (UCCE) */
|
||||
#define UCC_HDLC_UCCE_GLR 0x1000
|
||||
#define UCC_HDLC_UCCE_GLT 0x0800
|
||||
#define UCC_HDLC_UCCE_IDLE 0x0100
|
||||
#define UCC_HDLC_UCCE_BRKE 0x0040
|
||||
#define UCC_HDLC_UCCE_BRKS 0x0020
|
||||
#define UCC_HDLC_UCCE_TXE 0x0010
|
||||
#define UCC_HDLC_UCCE_RXF 0x0008
|
||||
#define UCC_HDLC_UCCE_BSY 0x0004
|
||||
#define UCC_HDLC_UCCE_TXB 0x0002
|
||||
#define UCC_HDLC_UCCE_RXB 0x0001
|
||||
|
||||
/* BISYNC Slow UCC Event Register (UCCE) */
|
||||
#define UCC_BISYNC_UCCE_GRA 0x0080
|
||||
#define UCC_BISYNC_UCCE_TXE 0x0010
|
||||
#define UCC_BISYNC_UCCE_RCH 0x0008
|
||||
#define UCC_BISYNC_UCCE_BSY 0x0004
|
||||
#define UCC_BISYNC_UCCE_TXB 0x0002
|
||||
#define UCC_BISYNC_UCCE_RXB 0x0001
|
||||
|
||||
/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
|
||||
#define UCC_GETH_UCCE_MPD 0x80000000
|
||||
#define UCC_GETH_UCCE_SCAR 0x40000000
|
||||
#define UCC_GETH_UCCE_GRA 0x20000000
|
||||
#define UCC_GETH_UCCE_CBPR 0x10000000
|
||||
#define UCC_GETH_UCCE_BSY 0x08000000
|
||||
#define UCC_GETH_UCCE_RXC 0x04000000
|
||||
#define UCC_GETH_UCCE_TXC 0x02000000
|
||||
#define UCC_GETH_UCCE_TXE 0x01000000
|
||||
#define UCC_GETH_UCCE_TXB7 0x00800000
|
||||
#define UCC_GETH_UCCE_TXB6 0x00400000
|
||||
#define UCC_GETH_UCCE_TXB5 0x00200000
|
||||
#define UCC_GETH_UCCE_TXB4 0x00100000
|
||||
#define UCC_GETH_UCCE_TXB3 0x00080000
|
||||
#define UCC_GETH_UCCE_TXB2 0x00040000
|
||||
#define UCC_GETH_UCCE_TXB1 0x00020000
|
||||
#define UCC_GETH_UCCE_TXB0 0x00010000
|
||||
#define UCC_GETH_UCCE_RXB7 0x00008000
|
||||
#define UCC_GETH_UCCE_RXB6 0x00004000
|
||||
#define UCC_GETH_UCCE_RXB5 0x00002000
|
||||
#define UCC_GETH_UCCE_RXB4 0x00001000
|
||||
#define UCC_GETH_UCCE_RXB3 0x00000800
|
||||
#define UCC_GETH_UCCE_RXB2 0x00000400
|
||||
#define UCC_GETH_UCCE_RXB1 0x00000200
|
||||
#define UCC_GETH_UCCE_RXB0 0x00000100
|
||||
#define UCC_GETH_UCCE_RXF7 0x00000080
|
||||
#define UCC_GETH_UCCE_RXF6 0x00000040
|
||||
#define UCC_GETH_UCCE_RXF5 0x00000020
|
||||
#define UCC_GETH_UCCE_RXF4 0x00000010
|
||||
#define UCC_GETH_UCCE_RXF3 0x00000008
|
||||
#define UCC_GETH_UCCE_RXF2 0x00000004
|
||||
#define UCC_GETH_UCCE_RXF1 0x00000002
|
||||
#define UCC_GETH_UCCE_RXF0 0x00000001
|
||||
|
||||
/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
|
||||
#define UCC_UART_UPSMR_FLC 0x8000
|
||||
#define UCC_UART_UPSMR_SL 0x4000
|
||||
#define UCC_UART_UPSMR_CL_MASK 0x3000
|
||||
#define UCC_UART_UPSMR_CL_8 0x3000
|
||||
#define UCC_UART_UPSMR_CL_7 0x2000
|
||||
#define UCC_UART_UPSMR_CL_6 0x1000
|
||||
#define UCC_UART_UPSMR_CL_5 0x0000
|
||||
#define UCC_UART_UPSMR_UM_MASK 0x0c00
|
||||
#define UCC_UART_UPSMR_UM_NORMAL 0x0000
|
||||
#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
|
||||
#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
|
||||
#define UCC_UART_UPSMR_FRZ 0x0200
|
||||
#define UCC_UART_UPSMR_RZS 0x0100
|
||||
#define UCC_UART_UPSMR_SYN 0x0080
|
||||
#define UCC_UART_UPSMR_DRT 0x0040
|
||||
#define UCC_UART_UPSMR_PEN 0x0010
|
||||
#define UCC_UART_UPSMR_RPM_MASK 0x000c
|
||||
#define UCC_UART_UPSMR_RPM_ODD 0x0000
|
||||
#define UCC_UART_UPSMR_RPM_LOW 0x0004
|
||||
#define UCC_UART_UPSMR_RPM_EVEN 0x0008
|
||||
#define UCC_UART_UPSMR_RPM_HIGH 0x000C
|
||||
#define UCC_UART_UPSMR_TPM_MASK 0x0003
|
||||
#define UCC_UART_UPSMR_TPM_ODD 0x0000
|
||||
#define UCC_UART_UPSMR_TPM_LOW 0x0001
|
||||
#define UCC_UART_UPSMR_TPM_EVEN 0x0002
|
||||
#define UCC_UART_UPSMR_TPM_HIGH 0x0003
|
||||
|
||||
/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
|
||||
#define UCC_GETH_UPSMR_FTFE 0x80000000
|
||||
#define UCC_GETH_UPSMR_PTPE 0x40000000
|
||||
#define UCC_GETH_UPSMR_ECM 0x04000000
|
||||
#define UCC_GETH_UPSMR_HSE 0x02000000
|
||||
#define UCC_GETH_UPSMR_PRO 0x00400000
|
||||
#define UCC_GETH_UPSMR_CAP 0x00200000
|
||||
#define UCC_GETH_UPSMR_RSH 0x00100000
|
||||
#define UCC_GETH_UPSMR_RPM 0x00080000
|
||||
#define UCC_GETH_UPSMR_R10M 0x00040000
|
||||
#define UCC_GETH_UPSMR_RLPB 0x00020000
|
||||
#define UCC_GETH_UPSMR_TBIM 0x00010000
|
||||
#define UCC_GETH_UPSMR_RES1 0x00002000
|
||||
#define UCC_GETH_UPSMR_RMM 0x00001000
|
||||
#define UCC_GETH_UPSMR_CAM 0x00000400
|
||||
#define UCC_GETH_UPSMR_BRO 0x00000200
|
||||
#define UCC_GETH_UPSMR_SMM 0x00000080
|
||||
#define UCC_GETH_UPSMR_SGMM 0x00000020
|
||||
|
||||
/* UCC Transmit On Demand Register (UTODR) */
|
||||
#define UCC_SLOW_TOD 0x8000
|
||||
#define UCC_FAST_TOD 0x8000
|
||||
|
||||
/* UCC Bus Mode Register masks */
|
||||
/* Not to be confused with the Bundle Mode Register */
|
||||
#define UCC_BMR_GBL 0x20
|
||||
#define UCC_BMR_BO_BE 0x10
|
||||
#define UCC_BMR_CETM 0x04
|
||||
#define UCC_BMR_DTB 0x02
|
||||
#define UCC_BMR_BDB 0x01
|
||||
|
||||
/* Function code masks */
|
||||
#define FC_GBL 0x20
|
||||
#define FC_DTB_LCL 0x02
|
||||
#define UCC_FAST_FUNCTION_CODE_GBL 0x20
|
||||
#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
|
||||
#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_QE_H */
|
||||
139
include/soc/fsl/qe/qe_ic.h
Normal file
139
include/soc/fsl/qe/qe_ic.h
Normal file
@@ -0,0 +1,139 @@
|
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* Authors: Shlomi Gridish <gridish@freescale.com>
|
||||
* Li Yang <leoli@freescale.com>
|
||||
*
|
||||
* Description:
|
||||
* QE IC external definitions and structure.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#ifndef _ASM_POWERPC_QE_IC_H
|
||||
#define _ASM_POWERPC_QE_IC_H
|
||||
|
||||
#include <linux/irq.h>
|
||||
|
||||
struct device_node;
|
||||
struct qe_ic;
|
||||
|
||||
#define NUM_OF_QE_IC_GROUPS 6
|
||||
|
||||
/* Flags when we init the QE IC */
|
||||
#define QE_IC_SPREADMODE_GRP_W 0x00000001
|
||||
#define QE_IC_SPREADMODE_GRP_X 0x00000002
|
||||
#define QE_IC_SPREADMODE_GRP_Y 0x00000004
|
||||
#define QE_IC_SPREADMODE_GRP_Z 0x00000008
|
||||
#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
|
||||
#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
|
||||
|
||||
#define QE_IC_LOW_SIGNAL 0x00000100
|
||||
#define QE_IC_HIGH_SIGNAL 0x00000200
|
||||
|
||||
#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
|
||||
#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
|
||||
#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
|
||||
#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
|
||||
#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
|
||||
#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
|
||||
#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
|
||||
#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
|
||||
#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
|
||||
#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
|
||||
#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
|
||||
#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
|
||||
#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
|
||||
|
||||
/* QE interrupt sources groups */
|
||||
enum qe_ic_grp_id {
|
||||
QE_IC_GRP_W = 0, /* QE interrupt controller group W */
|
||||
QE_IC_GRP_X, /* QE interrupt controller group X */
|
||||
QE_IC_GRP_Y, /* QE interrupt controller group Y */
|
||||
QE_IC_GRP_Z, /* QE interrupt controller group Z */
|
||||
QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
|
||||
QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
void qe_ic_init(struct device_node *node, unsigned int flags,
|
||||
void (*low_handler)(struct irq_desc *desc),
|
||||
void (*high_handler)(struct irq_desc *desc));
|
||||
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
|
||||
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
|
||||
#else
|
||||
static inline void qe_ic_init(struct device_node *node, unsigned int flags,
|
||||
void (*low_handler)(struct irq_desc *desc),
|
||||
void (*high_handler)(struct irq_desc *desc))
|
||||
{}
|
||||
static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
|
||||
{ return 0; }
|
||||
static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
|
||||
{ return 0; }
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
|
||||
void qe_ic_set_highest_priority(unsigned int virq, int high);
|
||||
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
|
||||
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
|
||||
|
||||
static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
|
||||
{
|
||||
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
|
||||
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
|
||||
|
||||
if (cascade_irq != NO_IRQ)
|
||||
generic_handle_irq(cascade_irq);
|
||||
}
|
||||
|
||||
static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
|
||||
{
|
||||
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
|
||||
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
|
||||
|
||||
if (cascade_irq != NO_IRQ)
|
||||
generic_handle_irq(cascade_irq);
|
||||
}
|
||||
|
||||
static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
|
||||
{
|
||||
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
|
||||
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
|
||||
if (cascade_irq != NO_IRQ)
|
||||
generic_handle_irq(cascade_irq);
|
||||
|
||||
chip->irq_eoi(&desc->irq_data);
|
||||
}
|
||||
|
||||
static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
|
||||
{
|
||||
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
|
||||
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
|
||||
if (cascade_irq != NO_IRQ)
|
||||
generic_handle_irq(cascade_irq);
|
||||
|
||||
chip->irq_eoi(&desc->irq_data);
|
||||
}
|
||||
|
||||
static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
|
||||
{
|
||||
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
|
||||
unsigned int cascade_irq;
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
|
||||
cascade_irq = qe_ic_get_high_irq(qe_ic);
|
||||
if (cascade_irq == NO_IRQ)
|
||||
cascade_irq = qe_ic_get_low_irq(qe_ic);
|
||||
|
||||
if (cascade_irq != NO_IRQ)
|
||||
generic_handle_irq(cascade_irq);
|
||||
|
||||
chip->irq_eoi(&desc->irq_data);
|
||||
}
|
||||
|
||||
#endif /* _ASM_POWERPC_QE_IC_H */
|
||||
64
include/soc/fsl/qe/ucc.h
Normal file
64
include/soc/fsl/qe/ucc.h
Normal file
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* Authors: Shlomi Gridish <gridish@freescale.com>
|
||||
* Li Yang <leoli@freescale.com>
|
||||
*
|
||||
* Description:
|
||||
* Internal header file for UCC unit routines.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#ifndef __UCC_H__
|
||||
#define __UCC_H__
|
||||
|
||||
#include <soc/fsl/qe/immap_qe.h>
|
||||
#include <soc/fsl/qe/qe.h>
|
||||
|
||||
#define STATISTICS
|
||||
|
||||
#define UCC_MAX_NUM 8
|
||||
|
||||
/* Slow or fast type for UCCs.
|
||||
*/
|
||||
enum ucc_speed_type {
|
||||
UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
|
||||
UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
|
||||
};
|
||||
|
||||
/* ucc_set_type
|
||||
* Sets UCC to slow or fast mode.
|
||||
*
|
||||
* ucc_num - (In) number of UCC (0-7).
|
||||
* speed - (In) slow or fast mode for UCC.
|
||||
*/
|
||||
int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
|
||||
|
||||
int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
|
||||
|
||||
int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
|
||||
enum comm_dir mode);
|
||||
|
||||
int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
|
||||
|
||||
/* QE MUX clock routing for UCC
|
||||
*/
|
||||
static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
|
||||
{
|
||||
return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
|
||||
}
|
||||
|
||||
static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
|
||||
{
|
||||
return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
|
||||
}
|
||||
|
||||
static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
|
||||
{
|
||||
return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
|
||||
}
|
||||
|
||||
#endif /* __UCC_H__ */
|
||||
244
include/soc/fsl/qe/ucc_fast.h
Normal file
244
include/soc/fsl/qe/ucc_fast.h
Normal file
@@ -0,0 +1,244 @@
|
||||
/*
|
||||
* Internal header file for UCC FAST unit routines.
|
||||
*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* Authors: Shlomi Gridish <gridish@freescale.com>
|
||||
* Li Yang <leoli@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#ifndef __UCC_FAST_H__
|
||||
#define __UCC_FAST_H__
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <soc/fsl/qe/immap_qe.h>
|
||||
#include <soc/fsl/qe/qe.h>
|
||||
|
||||
#include <soc/fsl/qe/ucc.h>
|
||||
|
||||
/* Receive BD's status */
|
||||
#define R_E 0x80000000 /* buffer empty */
|
||||
#define R_W 0x20000000 /* wrap bit */
|
||||
#define R_I 0x10000000 /* interrupt on reception */
|
||||
#define R_L 0x08000000 /* last */
|
||||
#define R_F 0x04000000 /* first */
|
||||
|
||||
/* transmit BD's status */
|
||||
#define T_R 0x80000000 /* ready bit */
|
||||
#define T_W 0x20000000 /* wrap bit */
|
||||
#define T_I 0x10000000 /* interrupt on completion */
|
||||
#define T_L 0x08000000 /* last */
|
||||
|
||||
/* Rx Data buffer must be 4 bytes aligned in most cases */
|
||||
#define UCC_FAST_RX_ALIGN 4
|
||||
#define UCC_FAST_MRBLR_ALIGNMENT 4
|
||||
#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
|
||||
|
||||
/* Sizes */
|
||||
#define UCC_FAST_URFS_MIN_VAL 0x88
|
||||
#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
|
||||
|
||||
/* ucc_fast_channel_protocol_mode - UCC FAST mode */
|
||||
enum ucc_fast_channel_protocol_mode {
|
||||
UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
|
||||
UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
|
||||
UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
|
||||
UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
|
||||
UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
|
||||
};
|
||||
|
||||
/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
|
||||
enum ucc_fast_transparent_txrx {
|
||||
UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
|
||||
UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
|
||||
};
|
||||
|
||||
/* UCC fast diagnostic mode */
|
||||
enum ucc_fast_diag_mode {
|
||||
UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
|
||||
UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
|
||||
UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
|
||||
UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
|
||||
};
|
||||
|
||||
/* UCC fast Sync length (transparent mode only) */
|
||||
enum ucc_fast_sync_len {
|
||||
UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
|
||||
UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
|
||||
UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
|
||||
UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
|
||||
};
|
||||
|
||||
/* UCC fast RTS mode */
|
||||
enum ucc_fast_ready_to_send {
|
||||
UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
|
||||
UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
|
||||
};
|
||||
|
||||
/* UCC fast receiver decoding mode */
|
||||
enum ucc_fast_rx_decoding_method {
|
||||
UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
|
||||
UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
|
||||
UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
|
||||
UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
|
||||
};
|
||||
|
||||
/* UCC fast transmitter encoding mode */
|
||||
enum ucc_fast_tx_encoding_method {
|
||||
UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
|
||||
UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
|
||||
UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
|
||||
UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
|
||||
};
|
||||
|
||||
/* UCC fast CRC length */
|
||||
enum ucc_fast_transparent_tcrc {
|
||||
UCC_FAST_16_BIT_CRC = 0x00000000,
|
||||
UCC_FAST_CRC_RESERVED0 = 0x00000040,
|
||||
UCC_FAST_32_BIT_CRC = 0x00000080,
|
||||
UCC_FAST_CRC_RESERVED1 = 0x000000C0
|
||||
};
|
||||
|
||||
/* Fast UCC initialization structure */
|
||||
struct ucc_fast_info {
|
||||
int ucc_num;
|
||||
enum qe_clock rx_clock;
|
||||
enum qe_clock tx_clock;
|
||||
u32 regs;
|
||||
int irq;
|
||||
u32 uccm_mask;
|
||||
int bd_mem_part;
|
||||
int brkpt_support;
|
||||
int grant_support;
|
||||
int tsa;
|
||||
int cdp;
|
||||
int cds;
|
||||
int ctsp;
|
||||
int ctss;
|
||||
int tci;
|
||||
int txsy;
|
||||
int rtsm;
|
||||
int revd;
|
||||
int rsyn;
|
||||
u16 max_rx_buf_length;
|
||||
u16 urfs;
|
||||
u16 urfet;
|
||||
u16 urfset;
|
||||
u16 utfs;
|
||||
u16 utfet;
|
||||
u16 utftt;
|
||||
u16 ufpt;
|
||||
enum ucc_fast_channel_protocol_mode mode;
|
||||
enum ucc_fast_transparent_txrx ttx_trx;
|
||||
enum ucc_fast_tx_encoding_method tenc;
|
||||
enum ucc_fast_rx_decoding_method renc;
|
||||
enum ucc_fast_transparent_tcrc tcrc;
|
||||
enum ucc_fast_sync_len synl;
|
||||
};
|
||||
|
||||
struct ucc_fast_private {
|
||||
struct ucc_fast_info *uf_info;
|
||||
struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */
|
||||
u32 __iomem *p_ucce; /* a pointer to the event register in memory. */
|
||||
u32 __iomem *p_uccm; /* a pointer to the mask register in memory. */
|
||||
#ifdef CONFIG_UGETH_TX_ON_DEMAND
|
||||
u16 __iomem *p_utodr; /* pointer to the transmit on demand register */
|
||||
#endif
|
||||
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
|
||||
int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
|
||||
int stopped_tx; /* Whether channel has been stopped for Tx
|
||||
(STOP_TX, etc.) */
|
||||
int stopped_rx; /* Whether channel has been stopped for Rx */
|
||||
u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
|
||||
virtual fifo */
|
||||
u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
|
||||
virtual fifo */
|
||||
#ifdef STATISTICS
|
||||
u32 tx_frames; /* Transmitted frames counter. */
|
||||
u32 rx_frames; /* Received frames counter (only frames
|
||||
passed to application). */
|
||||
u32 tx_discarded; /* Discarded tx frames counter (frames that
|
||||
were discarded by the driver due to errors).
|
||||
*/
|
||||
u32 rx_discarded; /* Discarded rx frames counter (frames that
|
||||
were discarded by the driver due to errors).
|
||||
*/
|
||||
#endif /* STATISTICS */
|
||||
u16 mrblr; /* maximum receive buffer length */
|
||||
};
|
||||
|
||||
/* ucc_fast_init
|
||||
* Initializes Fast UCC according to user provided parameters.
|
||||
*
|
||||
* uf_info - (In) pointer to the fast UCC info structure.
|
||||
* uccf_ret - (Out) pointer to the fast UCC structure.
|
||||
*/
|
||||
int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
|
||||
|
||||
/* ucc_fast_free
|
||||
* Frees all resources for fast UCC.
|
||||
*
|
||||
* uccf - (In) pointer to the fast UCC structure.
|
||||
*/
|
||||
void ucc_fast_free(struct ucc_fast_private * uccf);
|
||||
|
||||
/* ucc_fast_enable
|
||||
* Enables a fast UCC port.
|
||||
* This routine enables Tx and/or Rx through the General UCC Mode Register.
|
||||
*
|
||||
* uccf - (In) pointer to the fast UCC structure.
|
||||
* mode - (In) TX, RX, or both.
|
||||
*/
|
||||
void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
|
||||
|
||||
/* ucc_fast_disable
|
||||
* Disables a fast UCC port.
|
||||
* This routine disables Tx and/or Rx through the General UCC Mode Register.
|
||||
*
|
||||
* uccf - (In) pointer to the fast UCC structure.
|
||||
* mode - (In) TX, RX, or both.
|
||||
*/
|
||||
void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
|
||||
|
||||
/* ucc_fast_irq
|
||||
* Handles interrupts on fast UCC.
|
||||
* Called from the general interrupt routine to handle interrupts on fast UCC.
|
||||
*
|
||||
* uccf - (In) pointer to the fast UCC structure.
|
||||
*/
|
||||
void ucc_fast_irq(struct ucc_fast_private * uccf);
|
||||
|
||||
/* ucc_fast_transmit_on_demand
|
||||
* Immediately forces a poll of the transmitter for data to be sent.
|
||||
* Typically, the hardware performs a periodic poll for data that the
|
||||
* transmit routine has set up to be transmitted. In cases where
|
||||
* this polling cycle is not soon enough, this optional routine can
|
||||
* be invoked to force a poll right away, instead. Proper use for
|
||||
* each transmission for which this functionality is desired is to
|
||||
* call the transmit routine and then this routine right after.
|
||||
*
|
||||
* uccf - (In) pointer to the fast UCC structure.
|
||||
*/
|
||||
void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
|
||||
|
||||
u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
|
||||
|
||||
void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
|
||||
|
||||
#endif /* __UCC_FAST_H__ */
|
||||
277
include/soc/fsl/qe/ucc_slow.h
Normal file
277
include/soc/fsl/qe/ucc_slow.h
Normal file
@@ -0,0 +1,277 @@
|
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* Authors: Shlomi Gridish <gridish@freescale.com>
|
||||
* Li Yang <leoli@freescale.com>
|
||||
*
|
||||
* Description:
|
||||
* Internal header file for UCC SLOW unit routines.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#ifndef __UCC_SLOW_H__
|
||||
#define __UCC_SLOW_H__
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <soc/fsl/qe/immap_qe.h>
|
||||
#include <soc/fsl/qe/qe.h>
|
||||
|
||||
#include <soc/fsl/qe/ucc.h>
|
||||
|
||||
/* transmit BD's status */
|
||||
#define T_R 0x80000000 /* ready bit */
|
||||
#define T_PAD 0x40000000 /* add pads to short frames */
|
||||
#define T_W 0x20000000 /* wrap bit */
|
||||
#define T_I 0x10000000 /* interrupt on completion */
|
||||
#define T_L 0x08000000 /* last */
|
||||
|
||||
#define T_A 0x04000000 /* Address - the data transmitted as address
|
||||
chars */
|
||||
#define T_TC 0x04000000 /* transmit CRC */
|
||||
#define T_CM 0x02000000 /* continuous mode */
|
||||
#define T_DEF 0x02000000 /* collision on previous attempt to transmit */
|
||||
#define T_P 0x01000000 /* Preamble - send Preamble sequence before
|
||||
data */
|
||||
#define T_HB 0x01000000 /* heartbeat */
|
||||
#define T_NS 0x00800000 /* No Stop */
|
||||
#define T_LC 0x00800000 /* late collision */
|
||||
#define T_RL 0x00400000 /* retransmission limit */
|
||||
#define T_UN 0x00020000 /* underrun */
|
||||
#define T_CT 0x00010000 /* CTS lost */
|
||||
#define T_CSL 0x00010000 /* carrier sense lost */
|
||||
#define T_RC 0x003c0000 /* retry count */
|
||||
|
||||
/* Receive BD's status */
|
||||
#define R_E 0x80000000 /* buffer empty */
|
||||
#define R_W 0x20000000 /* wrap bit */
|
||||
#define R_I 0x10000000 /* interrupt on reception */
|
||||
#define R_L 0x08000000 /* last */
|
||||
#define R_C 0x08000000 /* the last byte in this buffer is a cntl
|
||||
char */
|
||||
#define R_F 0x04000000 /* first */
|
||||
#define R_A 0x04000000 /* the first byte in this buffer is address
|
||||
byte */
|
||||
#define R_CM 0x02000000 /* continuous mode */
|
||||
#define R_ID 0x01000000 /* buffer close on reception of idles */
|
||||
#define R_M 0x01000000 /* Frame received because of promiscuous
|
||||
mode */
|
||||
#define R_AM 0x00800000 /* Address match */
|
||||
#define R_DE 0x00800000 /* Address match */
|
||||
#define R_LG 0x00200000 /* Break received */
|
||||
#define R_BR 0x00200000 /* Frame length violation */
|
||||
#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
|
||||
#define R_FR 0x00100000 /* Framing Error (no stop bit) character
|
||||
received */
|
||||
#define R_PR 0x00080000 /* Parity Error character received */
|
||||
#define R_AB 0x00080000 /* Frame Aborted */
|
||||
#define R_SH 0x00080000 /* frame is too short */
|
||||
#define R_CR 0x00040000 /* CRC Error */
|
||||
#define R_OV 0x00020000 /* Overrun */
|
||||
#define R_CD 0x00010000 /* CD lost */
|
||||
#define R_CL 0x00010000 /* this frame is closed because of a
|
||||
collision */
|
||||
|
||||
/* Rx Data buffer must be 4 bytes aligned in most cases.*/
|
||||
#define UCC_SLOW_RX_ALIGN 4
|
||||
#define UCC_SLOW_MRBLR_ALIGNMENT 4
|
||||
#define UCC_SLOW_PRAM_SIZE 0x100
|
||||
#define ALIGNMENT_OF_UCC_SLOW_PRAM 64
|
||||
|
||||
/* UCC Slow Channel Protocol Mode */
|
||||
enum ucc_slow_channel_protocol_mode {
|
||||
UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
|
||||
UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
|
||||
UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
|
||||
};
|
||||
|
||||
/* UCC Slow Transparent Transmit CRC (TCRC) */
|
||||
enum ucc_slow_transparent_tcrc {
|
||||
/* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
|
||||
UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
|
||||
/* CRC16 (BISYNC). (X16 + X15 + X2 + 1) */
|
||||
UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
|
||||
/* 32-bit CCITT CRC (Ethernet and HDLC) */
|
||||
UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
|
||||
};
|
||||
|
||||
/* UCC Slow oversampling rate for transmitter (TDCR) */
|
||||
enum ucc_slow_tx_oversampling_rate {
|
||||
/* 1x clock mode */
|
||||
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
|
||||
/* 8x clock mode */
|
||||
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
|
||||
/* 16x clock mode */
|
||||
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
|
||||
/* 32x clock mode */
|
||||
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
|
||||
};
|
||||
|
||||
/* UCC Slow Oversampling rate for receiver (RDCR)
|
||||
*/
|
||||
enum ucc_slow_rx_oversampling_rate {
|
||||
/* 1x clock mode */
|
||||
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
|
||||
/* 8x clock mode */
|
||||
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
|
||||
/* 16x clock mode */
|
||||
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
|
||||
/* 32x clock mode */
|
||||
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
|
||||
};
|
||||
|
||||
/* UCC Slow Transmitter encoding method (TENC)
|
||||
*/
|
||||
enum ucc_slow_tx_encoding_method {
|
||||
UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
|
||||
UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
|
||||
};
|
||||
|
||||
/* UCC Slow Receiver decoding method (RENC)
|
||||
*/
|
||||
enum ucc_slow_rx_decoding_method {
|
||||
UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
|
||||
UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
|
||||
};
|
||||
|
||||
/* UCC Slow Diagnostic mode (DIAG)
|
||||
*/
|
||||
enum ucc_slow_diag_mode {
|
||||
UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
|
||||
UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
|
||||
UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
|
||||
UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
|
||||
};
|
||||
|
||||
struct ucc_slow_info {
|
||||
int ucc_num;
|
||||
int protocol; /* QE_CR_PROTOCOL_xxx */
|
||||
enum qe_clock rx_clock;
|
||||
enum qe_clock tx_clock;
|
||||
phys_addr_t regs;
|
||||
int irq;
|
||||
u16 uccm_mask;
|
||||
int data_mem_part;
|
||||
int init_tx;
|
||||
int init_rx;
|
||||
u32 tx_bd_ring_len;
|
||||
u32 rx_bd_ring_len;
|
||||
int rx_interrupts;
|
||||
int brkpt_support;
|
||||
int grant_support;
|
||||
int tsa;
|
||||
int cdp;
|
||||
int cds;
|
||||
int ctsp;
|
||||
int ctss;
|
||||
int rinv;
|
||||
int tinv;
|
||||
int rtsm;
|
||||
int rfw;
|
||||
int tci;
|
||||
int tend;
|
||||
int tfl;
|
||||
int txsy;
|
||||
u16 max_rx_buf_length;
|
||||
enum ucc_slow_transparent_tcrc tcrc;
|
||||
enum ucc_slow_channel_protocol_mode mode;
|
||||
enum ucc_slow_diag_mode diag;
|
||||
enum ucc_slow_tx_oversampling_rate tdcr;
|
||||
enum ucc_slow_rx_oversampling_rate rdcr;
|
||||
enum ucc_slow_tx_encoding_method tenc;
|
||||
enum ucc_slow_rx_decoding_method renc;
|
||||
};
|
||||
|
||||
struct ucc_slow_private {
|
||||
struct ucc_slow_info *us_info;
|
||||
struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
|
||||
struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */
|
||||
u32 us_pram_offset;
|
||||
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
|
||||
int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
|
||||
int stopped_tx; /* Whether channel has been stopped for Tx
|
||||
(STOP_TX, etc.) */
|
||||
int stopped_rx; /* Whether channel has been stopped for Rx */
|
||||
struct list_head confQ; /* frames passed to chip waiting for tx */
|
||||
u32 first_tx_bd_mask; /* mask is used in Tx routine to save status
|
||||
and length for first BD in a frame */
|
||||
u32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
|
||||
u32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
|
||||
struct qe_bd *confBd; /* next BD for confirm after Tx */
|
||||
struct qe_bd *tx_bd; /* next BD for new Tx request */
|
||||
struct qe_bd *rx_bd; /* next BD to collect after Rx */
|
||||
void *p_rx_frame; /* accumulating receive frame */
|
||||
u16 *p_ucce; /* a pointer to the event register in memory.
|
||||
*/
|
||||
u16 *p_uccm; /* a pointer to the mask register in memory */
|
||||
u16 saved_uccm; /* a saved mask for the RX Interrupt bits */
|
||||
#ifdef STATISTICS
|
||||
u32 tx_frames; /* Transmitted frames counters */
|
||||
u32 rx_frames; /* Received frames counters (only frames
|
||||
passed to application) */
|
||||
u32 rx_discarded; /* Discarded frames counters (frames that
|
||||
were discarded by the driver due to
|
||||
errors) */
|
||||
#endif /* STATISTICS */
|
||||
};
|
||||
|
||||
/* ucc_slow_init
|
||||
* Initializes Slow UCC according to provided parameters.
|
||||
*
|
||||
* us_info - (In) pointer to the slow UCC info structure.
|
||||
* uccs_ret - (Out) pointer to the slow UCC structure.
|
||||
*/
|
||||
int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
|
||||
|
||||
/* ucc_slow_free
|
||||
* Frees all resources for slow UCC.
|
||||
*
|
||||
* uccs - (In) pointer to the slow UCC structure.
|
||||
*/
|
||||
void ucc_slow_free(struct ucc_slow_private * uccs);
|
||||
|
||||
/* ucc_slow_enable
|
||||
* Enables a fast UCC port.
|
||||
* This routine enables Tx and/or Rx through the General UCC Mode Register.
|
||||
*
|
||||
* uccs - (In) pointer to the slow UCC structure.
|
||||
* mode - (In) TX, RX, or both.
|
||||
*/
|
||||
void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
|
||||
|
||||
/* ucc_slow_disable
|
||||
* Disables a fast UCC port.
|
||||
* This routine disables Tx and/or Rx through the General UCC Mode Register.
|
||||
*
|
||||
* uccs - (In) pointer to the slow UCC structure.
|
||||
* mode - (In) TX, RX, or both.
|
||||
*/
|
||||
void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
|
||||
|
||||
/* ucc_slow_graceful_stop_tx
|
||||
* Smoothly stops transmission on a specified slow UCC.
|
||||
*
|
||||
* uccs - (In) pointer to the slow UCC structure.
|
||||
*/
|
||||
void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
|
||||
|
||||
/* ucc_slow_stop_tx
|
||||
* Stops transmission on a specified slow UCC.
|
||||
*
|
||||
* uccs - (In) pointer to the slow UCC structure.
|
||||
*/
|
||||
void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
|
||||
|
||||
/* ucc_slow_restart_tx
|
||||
* Restarts transmitting on a specified slow UCC.
|
||||
*
|
||||
* uccs - (In) pointer to the slow UCC structure.
|
||||
*/
|
||||
void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
|
||||
|
||||
u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
|
||||
|
||||
#endif /* __UCC_SLOW_H__ */
|
||||
Reference in New Issue
Block a user