clk: meson: Add support for Meson clock controller

This patchset adds the infrastructure for registering and managing the
core clocks found on Amlogic MesonX SoCs. In particular:

- PLLs
- CPU clock
- Fixed rate clocks, fixed factor clocks, ...

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Carlo Caione
2015-06-01 13:13:53 +02:00
committed by Stephen Boyd
parent b787f68c36
commit 7a29a86943
7 changed files with 929 additions and 0 deletions

View File

@@ -0,0 +1,25 @@
/*
* Meson8b clock tree IDs
*/
#ifndef __MESON8B_CLKC_H
#define __MESON8B_CLKC_H
#define CLKID_UNUSED 0
#define CLKID_XTAL 1
#define CLKID_PLL_FIXED 2
#define CLKID_PLL_VID 3
#define CLKID_PLL_SYS 4
#define CLKID_FCLK_DIV2 5
#define CLKID_FCLK_DIV3 6
#define CLKID_FCLK_DIV4 7
#define CLKID_FCLK_DIV5 8
#define CLKID_FCLK_DIV7 9
#define CLKID_CLK81 10
#define CLKID_MALI 11
#define CLKID_CPUCLK 12
#define CLKID_ZERO 13
#define CLK_NR_CLKS (CLKID_ZERO + 1)
#endif /* __MESON8B_CLKC_H */