Merge drm/drm-next into drm-intel-next-queued
Although there's nothing crucial missing, it's been a long time since the last backmerge. Catch up with drm-next. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
@@ -338,6 +338,15 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
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/*
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* Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
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*
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* This is a simple tiled layout using tiles of 16x16 pixels in a row-major
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* layout. For YCbCr formats Cb/Cr components are taken in such a way that
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* they correspond to their 16x16 luma block.
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
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/*
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* Qualcomm Compressed Format
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*
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@@ -82,6 +82,14 @@ struct kfd_ioctl_set_cu_mask_args {
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__u64 cu_mask_ptr; /* to KFD */
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};
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struct kfd_ioctl_get_queue_wave_state_args {
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uint64_t ctl_stack_address; /* to KFD */
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uint32_t ctl_stack_used_size; /* from KFD */
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uint32_t save_area_used_size; /* from KFD */
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uint32_t queue_id; /* to KFD */
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uint32_t pad;
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};
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/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
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#define KFD_IOC_CACHE_POLICY_COHERENT 0
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#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
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@@ -475,7 +483,10 @@ struct kfd_ioctl_unmap_memory_from_gpu_args {
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#define AMDKFD_IOC_SET_CU_MASK \
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AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
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#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
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AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
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#define AMDKFD_COMMAND_START 0x01
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#define AMDKFD_COMMAND_END 0x1B
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#define AMDKFD_COMMAND_END 0x1C
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#endif
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@@ -952,6 +952,7 @@ struct kvm_ppc_resize_hpt {
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#define KVM_CAP_S390_HPAGE_1M 156
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#define KVM_CAP_NESTED_STATE 157
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#define KVM_CAP_ARM_INJECT_SERROR_ESR 158
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#define KVM_CAP_MSR_PLATFORM_INFO 159
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#ifdef KVM_CAP_IRQ_ROUTING
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@@ -144,7 +144,7 @@ enum perf_event_sample_format {
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PERF_SAMPLE_MAX = 1U << 20, /* non-ABI */
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__PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63,
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__PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */
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};
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/*
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@@ -37,6 +37,7 @@
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#include <linux/types.h>
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#include <linux/socket.h> /* For __kernel_sockaddr_storage. */
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#include <linux/in6.h> /* For struct in6_addr. */
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#define RDS_IB_ABI_VERSION 0x301
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@@ -176,7 +176,7 @@ struct vhost_memory {
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#define VHOST_BACKEND_F_IOTLB_MSG_V2 0x1
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#define VHOST_SET_BACKEND_FEATURES _IOW(VHOST_VIRTIO, 0x25, __u64)
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#define VHOST_GET_BACKEND_FEATURES _IOW(VHOST_VIRTIO, 0x26, __u64)
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#define VHOST_GET_BACKEND_FEATURES _IOR(VHOST_VIRTIO, 0x26, __u64)
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/* VHOST_NET specific defines */
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@@ -10,6 +10,8 @@
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#ifndef __HDA_TPLG_INTERFACE_H__
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#define __HDA_TPLG_INTERFACE_H__
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#include <linux/types.h>
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/*
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* Default types range from 0~12. type can range from 0 to 0xff
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* SST types start at higher to avoid any overlapping in future
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@@ -143,10 +145,10 @@ enum skl_module_param_type {
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};
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struct skl_dfw_algo_data {
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u32 set_params:2;
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u32 rsvd:30;
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u32 param_id;
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u32 max;
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__u32 set_params:2;
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__u32 rsvd:30;
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__u32 param_id;
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__u32 max;
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char params[0];
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} __packed;
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@@ -163,68 +165,68 @@ enum skl_tuple_type {
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/* v4 configuration data */
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struct skl_dfw_v4_module_pin {
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u16 module_id;
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u16 instance_id;
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__u16 module_id;
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__u16 instance_id;
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} __packed;
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struct skl_dfw_v4_module_fmt {
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u32 channels;
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u32 freq;
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u32 bit_depth;
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u32 valid_bit_depth;
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u32 ch_cfg;
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u32 interleaving_style;
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u32 sample_type;
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u32 ch_map;
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__u32 channels;
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__u32 freq;
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__u32 bit_depth;
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__u32 valid_bit_depth;
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__u32 ch_cfg;
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__u32 interleaving_style;
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__u32 sample_type;
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__u32 ch_map;
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} __packed;
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struct skl_dfw_v4_module_caps {
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u32 set_params:2;
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u32 rsvd:30;
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u32 param_id;
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u32 caps_size;
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u32 caps[HDA_SST_CFG_MAX];
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__u32 set_params:2;
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__u32 rsvd:30;
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__u32 param_id;
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__u32 caps_size;
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__u32 caps[HDA_SST_CFG_MAX];
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} __packed;
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struct skl_dfw_v4_pipe {
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u8 pipe_id;
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u8 pipe_priority;
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u16 conn_type:4;
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u16 rsvd:4;
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u16 memory_pages:8;
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__u8 pipe_id;
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__u8 pipe_priority;
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__u16 conn_type:4;
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__u16 rsvd:4;
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__u16 memory_pages:8;
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} __packed;
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struct skl_dfw_v4_module {
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char uuid[SKL_UUID_STR_SZ];
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u16 module_id;
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u16 instance_id;
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u32 max_mcps;
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u32 mem_pages;
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u32 obs;
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u32 ibs;
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u32 vbus_id;
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__u16 module_id;
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__u16 instance_id;
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__u32 max_mcps;
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__u32 mem_pages;
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__u32 obs;
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__u32 ibs;
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__u32 vbus_id;
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u32 max_in_queue:8;
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u32 max_out_queue:8;
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u32 time_slot:8;
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u32 core_id:4;
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u32 rsvd1:4;
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__u32 max_in_queue:8;
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__u32 max_out_queue:8;
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__u32 time_slot:8;
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__u32 core_id:4;
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__u32 rsvd1:4;
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u32 module_type:8;
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u32 conn_type:4;
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u32 dev_type:4;
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u32 hw_conn_type:4;
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u32 rsvd2:12;
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__u32 module_type:8;
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__u32 conn_type:4;
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__u32 dev_type:4;
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__u32 hw_conn_type:4;
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__u32 rsvd2:12;
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u32 params_fixup:8;
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u32 converter:8;
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u32 input_pin_type:1;
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u32 output_pin_type:1;
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u32 is_dynamic_in_pin:1;
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u32 is_dynamic_out_pin:1;
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u32 is_loadable:1;
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u32 rsvd3:11;
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__u32 params_fixup:8;
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__u32 converter:8;
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__u32 input_pin_type:1;
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__u32 output_pin_type:1;
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__u32 is_dynamic_in_pin:1;
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__u32 is_dynamic_out_pin:1;
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__u32 is_loadable:1;
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__u32 rsvd3:11;
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struct skl_dfw_v4_pipe pipe;
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struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE];
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