Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (92 commits) powerpc: Remove unused 'protect4gb' boot parameter powerpc: Build-in e1000e for pseries & ppc64_defconfig powerpc/pseries: Make request_ras_irqs() available to other pseries code powerpc/numa: Use ibm,architecture-vec-5 to detect form 1 affinity powerpc/numa: Set a smaller value for RECLAIM_DISTANCE to enable zone reclaim powerpc: Use smt_snooze_delay=-1 to always busy loop powerpc: Remove check of ibm,smt-snooze-delay OF property powerpc/kdump: Fix race in kdump shutdown powerpc/kexec: Fix race in kexec shutdown powerpc/kexec: Speedup kexec hash PTE tear down powerpc/pseries: Add hcall to read 4 ptes at a time in real mode powerpc: Use more accurate limit for first segment memory allocations powerpc/kdump: Use chip->shutdown to disable IRQs powerpc/kdump: CPUs assume the context of the oopsing CPU powerpc/crashdump: Do not fail on NULL pointer dereferencing powerpc/eeh: Fix oops when probing in early boot powerpc/pci: Check devices status property when scanning OF tree powerpc/vio: Switch VIO Bus PM to use generic helpers powerpc: Avoid bad relocations in iSeries code powerpc: Use common cpu_die (fixes SMP+SUSPEND build) ...
This commit is contained in:
Linus Torvalds
@@ -16,6 +16,7 @@
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#include <linux/of_gpio.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#define MPC8XXX_GPIO_PINS 32
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@@ -35,6 +36,7 @@ struct mpc8xxx_gpio_chip {
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* open drain mode safely
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*/
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u32 data;
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struct irq_host *irq;
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};
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static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
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@@ -128,12 +130,136 @@ static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val
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return 0;
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}
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static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
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return irq_create_mapping(mpc8xxx_gc->irq, offset);
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else
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return -ENXIO;
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}
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static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned int mask;
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mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
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if (mask)
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generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
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32 - ffs(mask)));
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}
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static void mpc8xxx_irq_unmask(unsigned int virq)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_mask(unsigned int virq)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_ack(unsigned int virq)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(virq)));
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}
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static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(virq_to_hw(virq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(virq_to_hw(virq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static struct irq_chip mpc8xxx_irq_chip = {
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.name = "mpc8xxx-gpio",
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.unmask = mpc8xxx_irq_unmask,
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.mask = mpc8xxx_irq_mask,
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.ack = mpc8xxx_irq_ack,
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.set_type = mpc8xxx_irq_set_type,
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};
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static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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set_irq_chip_data(virq, h->host_data);
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set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
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set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_flags)
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{
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/* interrupt sense values coming from the device tree equal either
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* EDGE_FALLING or EDGE_BOTH
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*/
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*out_hwirq = intspec[0];
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*out_flags = intspec[1];
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return 0;
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}
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static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
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.map = mpc8xxx_gpio_irq_map,
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.xlate = mpc8xxx_gpio_irq_xlate,
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};
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static void __init mpc8xxx_add_controller(struct device_node *np)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct of_gpio_chip *of_gc;
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struct gpio_chip *gc;
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unsigned hwirq;
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int ret;
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mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
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@@ -158,11 +284,32 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
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else
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gc->get = mpc8xxx_gpio_get;
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gc->set = mpc8xxx_gpio_set;
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gc->to_irq = mpc8xxx_gpio_to_irq;
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ret = of_mm_gpiochip_add(np, mm_gc);
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if (ret)
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goto err;
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hwirq = irq_of_parse_and_map(np, 0);
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if (hwirq == NO_IRQ)
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goto skip_irq;
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mpc8xxx_gc->irq =
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irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
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&mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
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if (!mpc8xxx_gc->irq)
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goto skip_irq;
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mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
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/* ack and mask all irqs */
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out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
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out_be32(mm_gc->regs + GPIO_IMR, 0);
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set_irq_data(hwirq, mpc8xxx_gc);
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set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
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skip_irq:
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return;
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err:
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@@ -568,12 +568,12 @@ static void __init mpic_scan_ht_pics(struct mpic *mpic)
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#endif /* CONFIG_MPIC_U3_HT_IRQS */
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#ifdef CONFIG_SMP
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static int irq_choose_cpu(const cpumask_t *mask)
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static int irq_choose_cpu(const struct cpumask *mask)
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{
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int cpuid;
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if (cpumask_equal(mask, cpu_all_mask)) {
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static int irq_rover;
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static int irq_rover = 0;
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static DEFINE_RAW_SPINLOCK(irq_rover_lock);
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unsigned long flags;
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@@ -581,15 +581,11 @@ static int irq_choose_cpu(const cpumask_t *mask)
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do_round_robin:
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raw_spin_lock_irqsave(&irq_rover_lock, flags);
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while (!cpu_online(irq_rover)) {
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if (++irq_rover >= NR_CPUS)
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irq_rover = 0;
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}
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irq_rover = cpumask_next(irq_rover, cpu_online_mask);
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if (irq_rover >= nr_cpu_ids)
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irq_rover = cpumask_first(cpu_online_mask);
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cpuid = irq_rover;
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do {
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if (++irq_rover >= NR_CPUS)
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irq_rover = 0;
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} while (!cpu_online(irq_rover));
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raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
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} else {
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@@ -601,7 +597,7 @@ static int irq_choose_cpu(const cpumask_t *mask)
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return get_hard_smp_processor_id(cpuid);
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}
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#else
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static int irq_choose_cpu(const cpumask_t *mask)
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static int irq_choose_cpu(const struct cpumask *mask)
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{
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return hard_smp_processor_id();
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}
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@@ -814,12 +810,16 @@ int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
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mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
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} else {
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cpumask_t tmp;
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cpumask_var_t tmp;
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cpumask_and(&tmp, cpumask, cpu_online_mask);
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alloc_cpumask_var(&tmp, GFP_KERNEL);
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cpumask_and(tmp, cpumask, cpu_online_mask);
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mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
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mpic_physmask(cpus_addr(tmp)[0]));
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mpic_physmask(cpumask_bits(tmp)[0]));
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free_cpumask_var(tmp);
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}
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return 0;
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@@ -1479,21 +1479,6 @@ void mpic_teardown_this_cpu(int secondary)
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}
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void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
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{
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struct mpic *mpic = mpic_primary;
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BUG_ON(mpic == NULL);
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#ifdef DEBUG_IPI
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DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
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#endif
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mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
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ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
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mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
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}
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static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
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{
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u32 src;
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@@ -1589,8 +1574,25 @@ void mpic_request_ipis(void)
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}
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}
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static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
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{
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struct mpic *mpic = mpic_primary;
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BUG_ON(mpic == NULL);
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#ifdef DEBUG_IPI
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DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
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#endif
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mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
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ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
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mpic_physmask(cpumask_bits(cpu_mask)[0]));
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}
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void smp_mpic_message_pass(int target, int msg)
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{
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cpumask_var_t tmp;
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/* make sure we're sending something that translates to an IPI */
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if ((unsigned int)msg > 3) {
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printk("SMP %d: smp_message_pass: unknown msg %d\n",
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@@ -1599,13 +1601,17 @@ void smp_mpic_message_pass(int target, int msg)
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}
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switch (target) {
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case MSG_ALL:
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mpic_send_ipi(msg, 0xffffffff);
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mpic_send_ipi(msg, cpu_online_mask);
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break;
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case MSG_ALL_BUT_SELF:
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mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
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alloc_cpumask_var(&tmp, GFP_NOWAIT);
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cpumask_andnot(tmp, cpu_online_mask,
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cpumask_of(smp_processor_id()));
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mpic_send_ipi(msg, tmp);
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free_cpumask_var(tmp);
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break;
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default:
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mpic_send_ipi(msg, 1 << target);
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mpic_send_ipi(msg, cpumask_of(target));
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break;
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}
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}
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@@ -1616,7 +1622,7 @@ int __init smp_mpic_probe(void)
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DBG("smp_mpic_probe()...\n");
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nr_cpus = cpus_weight(cpu_possible_map);
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nr_cpus = cpumask_weight(cpu_possible_mask);
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DBG("nr_cpus: %d\n", nr_cpus);
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@@ -191,11 +191,31 @@ static int __init ppc4xx_l2c_probe(void)
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arch_initcall(ppc4xx_l2c_probe);
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/*
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* At present, this routine just applies a system reset.
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* Apply a system reset. Alternatively a board specific value may be
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* provided via the "reset-type" property in the cpu node.
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*/
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void ppc4xx_reset_system(char *cmd)
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{
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mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_RST_SYSTEM);
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struct device_node *np;
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u32 reset_type = DBCR0_RST_SYSTEM;
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const u32 *prop;
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np = of_find_node_by_type(NULL, "cpu");
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if (np) {
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prop = of_get_property(np, "reset-type", NULL);
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/*
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* Check if property exists and if it is in range:
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* 1 - PPC4xx core reset
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* 2 - PPC4xx chip reset
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* 3 - PPC4xx system reset (default)
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*/
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if ((prop) && ((prop[0] >= 1) && (prop[0] <= 3)))
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reset_type = prop[0] << 28;
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}
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mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | reset_type);
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while (1)
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; /* Just in case the reset doesn't work */
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}
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Reference in New Issue
Block a user