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RISC-V: Setup exception vector early

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The trap vector is set only in trap_init which may be too late in some
cases. Early ioremap/efi spits many warning messages which may be useful.

Setup the trap vector early so that any warning/bug can be handled before
generic code invokes trap_init.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Atish Patra
2020-07-15 16:30:06 -07:00
committed by Palmer Dabbelt
parent 925ac7b663
commit 79b1feba54
3 changed files with 10 additions and 10 deletions
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10
arch/riscv/kernel/head.S
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@@ -77,10 +77,16 @@ relocate:
csrw CSR_SATP, a0
.align 2
1:
/* Set trap vector to spin forever to help debug */
la a0, .Lsecondary_park
/* Set trap vector to exception handler */
la a0, handle_exception
csrw CSR_TVEC, a0
/*
* Set sup0 scratch register to 0, indicating to exception vector that
* we are presently executing in kernel.
*/
csrw CSR_SCRATCH, zero
/* Reload the global pointer */
.option push
.option norelax