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cxl: Fixes for Coherent Accelerator Interface Architecture 2.0

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A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards. These patches have been tested on Simulation environment and
quite a bit of them have been tested on real hardware.

This patch brings new fixes after a series of tests carried out on new
equipment:
  - Add POWER9 definition.
  - Re-enable any masked interrupts when the AFU is not activated
    after resetting the AFU.
  - Remove the api cxl_is_psl8/9 which is no longer useful.
  - Do not dump CAPI1 registers.
  - Rewrite cxl_is_page_fault() function.
  - Do not register slb callack on P9.

Fixes: f24be42aab ("cxl: Add psl9 specific code")
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Christophe Lombard
2017-06-13 17:41:05 +02:00
committed by Michael Ellerman
parent 34f19ff1b5
commit 797625deae
6 changed files with 57 additions and 47 deletions
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23
drivers/misc/cxl/fault.c
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@@ -187,7 +187,7 @@ static struct mm_struct *get_mem_context(struct cxl_context *ctx)
static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)
{
if ((cxl_is_psl8(ctx->afu)) && (dsisr & CXL_PSL_DSISR_An_DS))
if ((cxl_is_power8() && (dsisr & CXL_PSL_DSISR_An_DS)))
return true;
return false;
@@ -195,15 +195,22 @@ static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)
static bool cxl_is_page_fault(struct cxl_context *ctx, u64 dsisr)
{
if ((cxl_is_psl8(ctx->afu)) && (dsisr & CXL_PSL_DSISR_An_DM))
u64 crs; /* Translation Checkout Response Status */
if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_An_DM))
return true;
if ((cxl_is_psl9(ctx->afu)) &&
((dsisr & CXL_PSL9_DSISR_An_CO_MASK) &
(CXL_PSL9_DSISR_An_PF_SLR | CXL_PSL9_DSISR_An_PF_RGC |
CXL_PSL9_DSISR_An_PF_RGP | CXL_PSL9_DSISR_An_PF_HRH |
CXL_PSL9_DSISR_An_PF_STEG)))
return true;
if (cxl_is_power9()) {
crs = (dsisr & CXL_PSL9_DSISR_An_CO_MASK);
if ((crs == CXL_PSL9_DSISR_An_PF_SLR) ||
(crs == CXL_PSL9_DSISR_An_PF_RGC) ||
(crs == CXL_PSL9_DSISR_An_PF_RGP) ||
(crs == CXL_PSL9_DSISR_An_PF_HRH) ||
(crs == CXL_PSL9_DSISR_An_PF_STEG) ||
(crs == CXL_PSL9_DSISR_An_URTCH)) {
return true;
}
}
return false;
}