Merge branch 'mlx5_uar' into rdma.git /for-next
Meir Lichtinger says:
====================
ConnectX-7 supports setting relaxed ordering read/write mkey attribute by
UMR, indicated by new HCA capabilities, so extend mlx5_ib driver to
configure UMR control segment
====================
Based on the mlx5-next branch at
git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux
due to dependencies.
* branch 'mlx5_uar':
RDMA/mlx5: Set mkey relaxed ordering by UMR with ConnectX-7
RDMA/mlx5: Use MLX5_SET macro instead of local structure
RDMA/mlx5: ConnectX-7 new capabilities to set relaxed ordering by UMR
This commit is contained in:
Jason Gunthorpe
@@ -1356,15 +1356,6 @@ static inline void init_query_mad(struct ib_smp *mad)
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mad->method = IB_MGMT_METHOD_GET;
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}
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static inline u8 convert_access(int acc)
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{
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return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
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(acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
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(acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
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(acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
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MLX5_PERM_LOCAL_READ;
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}
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static inline int is_qp1(enum ib_qp_type qp_type)
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{
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return qp_type == MLX5_IB_QPT_HW_GSI;
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@@ -1463,8 +1454,13 @@ static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev,
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return false;
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if (access_flags & IB_ACCESS_RELAXED_ORDERING &&
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(MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) ||
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MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)))
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MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) &&
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!MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
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return false;
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if (access_flags & IB_ACCESS_RELAXED_ORDERING &&
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MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) &&
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!MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
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return false;
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return true;
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@@ -263,7 +263,9 @@ static __be64 get_umr_update_translation_mask(void)
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return cpu_to_be64(result);
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}
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static __be64 get_umr_update_access_mask(int atomic)
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static __be64 get_umr_update_access_mask(int atomic,
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int relaxed_ordering_write,
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int relaxed_ordering_read)
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{
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u64 result;
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@@ -275,6 +277,12 @@ static __be64 get_umr_update_access_mask(int atomic)
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if (atomic)
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result |= MLX5_MKEY_MASK_A;
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if (relaxed_ordering_write)
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result |= MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE;
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if (relaxed_ordering_read)
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result |= MLX5_MKEY_MASK_RELAXED_ORDERING_READ;
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return cpu_to_be64(result);
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}
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@@ -289,17 +297,28 @@ static __be64 get_umr_update_pd_mask(void)
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static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
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{
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if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
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MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
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(mask & MLX5_MKEY_MASK_A &&
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MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
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if (mask & MLX5_MKEY_MASK_PAGE_SIZE &&
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MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
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return -EPERM;
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if (mask & MLX5_MKEY_MASK_A &&
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MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
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return -EPERM;
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if (mask & MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE &&
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!MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
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return -EPERM;
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if (mask & MLX5_MKEY_MASK_RELAXED_ORDERING_READ &&
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!MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
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return -EPERM;
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return 0;
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}
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static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
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struct mlx5_wqe_umr_ctrl_seg *umr,
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const struct ib_send_wr *wr, int atomic)
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const struct ib_send_wr *wr)
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{
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const struct mlx5_umr_wr *umrwr = umr_wr(wr);
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@@ -325,7 +344,10 @@ static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
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if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
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umr->mkey_mask |= get_umr_update_translation_mask();
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if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
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umr->mkey_mask |= get_umr_update_access_mask(atomic);
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umr->mkey_mask |= get_umr_update_access_mask(
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!!(MLX5_CAP_GEN(dev->mdev, atomic)),
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!!(MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)),
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!!(MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)));
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umr->mkey_mask |= get_umr_update_pd_mask();
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}
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if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
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@@ -383,20 +405,31 @@ static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
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memset(seg, 0, sizeof(*seg));
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if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
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seg->status = MLX5_MKEY_STATUS_FREE;
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MLX5_SET(mkc, seg, free, 1);
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MLX5_SET(mkc, seg, a,
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!!(umrwr->access_flags & IB_ACCESS_REMOTE_ATOMIC));
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MLX5_SET(mkc, seg, rw,
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!!(umrwr->access_flags & IB_ACCESS_REMOTE_WRITE));
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MLX5_SET(mkc, seg, rr, !!(umrwr->access_flags & IB_ACCESS_REMOTE_READ));
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MLX5_SET(mkc, seg, lw, !!(umrwr->access_flags & IB_ACCESS_LOCAL_WRITE));
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MLX5_SET(mkc, seg, lr, 1);
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MLX5_SET(mkc, seg, relaxed_ordering_write,
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!!(umrwr->access_flags & IB_ACCESS_RELAXED_ORDERING));
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MLX5_SET(mkc, seg, relaxed_ordering_read,
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!!(umrwr->access_flags & IB_ACCESS_RELAXED_ORDERING));
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seg->flags = convert_access(umrwr->access_flags);
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if (umrwr->pd)
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seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
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MLX5_SET(mkc, seg, pd, to_mpd(umrwr->pd)->pdn);
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if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
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!umrwr->length)
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seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
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MLX5_SET(mkc, seg, length64, 1);
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seg->start_addr = cpu_to_be64(umrwr->virt_addr);
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seg->len = cpu_to_be64(umrwr->length);
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seg->log2_page_size = umrwr->page_shift;
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seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
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mlx5_mkey_variant(umrwr->mkey));
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MLX5_SET64(mkc, seg, start_addr, umrwr->virt_addr);
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MLX5_SET64(mkc, seg, len, umrwr->length);
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MLX5_SET(mkc, seg, log_page_size, umrwr->page_shift);
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MLX5_SET(mkc, seg, qpn, 0xffffff);
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MLX5_SET(mkc, seg, mkey_7_0, mlx5_mkey_variant(umrwr->mkey));
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}
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static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
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@@ -1224,8 +1257,7 @@ static int handle_qpt_reg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
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(*ctrl)->imm = cpu_to_be32(umr_wr(wr)->mkey);
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err = set_reg_umr_segment(dev, *seg, wr,
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!!(MLX5_CAP_GEN(dev->mdev, atomic)));
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err = set_reg_umr_segment(dev, *seg, wr);
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if (unlikely(err))
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goto out;
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*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
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