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phy: qcom-qmp: Rename UFS PCS QMP v4 registers

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The UFS QMP v4 PHY has a largely different register set versus USB and
PCIe.  Rename the register offsets to denote that the value is specific for
the UFS PCS register.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Wesley Cheng
2020-05-04 16:54:27 -07:00
committed by Vinod Koul
parent e4d8b05ad5
commit 78c2aac2a0
2 changed files with 30 additions and 30 deletions
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40
drivers/phy/qualcomm/phy-qcom-qmp.h
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@@ -425,26 +425,26 @@
#define QSERDES_V4_RX_VTH_CODE 0x1c4
/* Only for QMP V4 PHY - UFS PCS registers */
#define QPHY_V4_PHY_START 0x000
#define QPHY_V4_POWER_DOWN_CONTROL 0x004
#define QPHY_V4_SW_RESET 0x008
#define QPHY_V4_TIMER_20US_CORECLK_STEPS_MSB 0x00c
#define QPHY_V4_TIMER_20US_CORECLK_STEPS_LSB 0x010
#define QPHY_V4_PLL_CNTL 0x02c
#define QPHY_V4_TX_LARGE_AMP_DRV_LVL 0x030
#define QPHY_V4_TX_SMALL_AMP_DRV_LVL 0x038
#define QPHY_V4_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V4_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V4_RX_HSGEAR_CAPABILITY 0x0b4
#define QPHY_V4_DEBUG_BUS_CLKSEL 0x124
#define QPHY_V4_LINECFG_DISABLE 0x148
#define QPHY_V4_RX_MIN_HIBERN8_TIME 0x150
#define QPHY_V4_RX_SIGDET_CTRL2 0x158
#define QPHY_V4_TX_PWM_GEAR_BAND 0x160
#define QPHY_V4_TX_HS_GEAR_BAND 0x168
#define QPHY_V4_PCS_READY_STATUS 0x180
#define QPHY_V4_TX_MID_TERM_CTRL1 0x1d8
#define QPHY_V4_MULTI_LANE_CTRL1 0x1e0
#define QPHY_V4_PCS_UFS_PHY_START 0x000
#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
#define QPHY_V4_PCS_UFS_SW_RESET 0x008
#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
#define QPHY_V4_PCS_UFS_READY_STATUS 0x180
#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
/* PCIE GEN3 COM registers */
#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14