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@@ -51,7 +51,9 @@
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#define EP93XX_I2S_WRDLEN_24 (1 << 0)
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#define EP93XX_I2S_WRDLEN_32 (2 << 0)
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#define EP93XX_I2S_LINCTRLDATA_R_JUST (1 << 2) /* Right justify */
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#define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */
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#define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */
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#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
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#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
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@@ -170,25 +172,25 @@ static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
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unsigned int clk_cfg, lin_ctrl;
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unsigned int clk_cfg;
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unsigned int txlin_ctrl = 0;
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unsigned int rxlin_ctrl = 0;
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clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
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lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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clk_cfg |= EP93XX_I2S_CLKCFG_REL;
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lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
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lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
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lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
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rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST;
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txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST;
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break;
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default:
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@@ -213,32 +215,32 @@ static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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/* Negative bit clock, lrclk low on left word */
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clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
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clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS);
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break;
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case SND_SOC_DAIFMT_NB_IF:
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/* Negative bit clock, lrclk low on right word */
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clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
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clk_cfg |= EP93XX_I2S_CLKCFG_REL;
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clk_cfg |= EP93XX_I2S_CLKCFG_LRS;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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/* Positive bit clock, lrclk low on left word */
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clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
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clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
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clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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/* Positive bit clock, lrclk low on right word */
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clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
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clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS;
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break;
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}
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/* Write new register values */
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ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
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ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
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ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl);
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl);
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return 0;
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}
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