MIPS: Netlogic: Support for multi-chip configuration
Upto 4 Netlogic XLP SoCs can be connected over ICI links to form a coherent multi-node system. Each SoC has its own set of on-chip devices including PIC. To support this, add a per SoC stucture and use it for the PIC and SYS block addresses instead of using global variables. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4469 Signed-off-by: John Crispin <blogic@openwrt.org>
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committed by
John Crispin

parent
2a37b1ae44
commit
77ae798f5b
@@ -70,33 +70,34 @@
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*/
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/* Globals */
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static uint64_t nlm_irq_mask;
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static DEFINE_SPINLOCK(nlm_pic_lock);
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static void xlp_pic_enable(struct irq_data *d)
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{
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unsigned long flags;
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struct nlm_soc_info *nodep;
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int irt;
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nodep = nlm_current_node();
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irt = nlm_irq_to_irt(d->irq);
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if (irt == -1)
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return;
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spin_lock_irqsave(&nlm_pic_lock, flags);
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nlm_pic_enable_irt(nlm_pic_base, irt);
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spin_unlock_irqrestore(&nlm_pic_lock, flags);
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spin_lock_irqsave(&nodep->piclock, flags);
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nlm_pic_enable_irt(nodep->picbase, irt);
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spin_unlock_irqrestore(&nodep->piclock, flags);
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}
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static void xlp_pic_disable(struct irq_data *d)
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{
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struct nlm_soc_info *nodep;
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unsigned long flags;
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int irt;
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nodep = nlm_current_node();
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irt = nlm_irq_to_irt(d->irq);
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if (irt == -1)
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return;
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spin_lock_irqsave(&nlm_pic_lock, flags);
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nlm_pic_disable_irt(nlm_pic_base, irt);
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spin_unlock_irqrestore(&nlm_pic_lock, flags);
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spin_lock_irqsave(&nodep->piclock, flags);
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nlm_pic_disable_irt(nodep->picbase, irt);
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spin_unlock_irqrestore(&nodep->piclock, flags);
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}
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static void xlp_pic_mask_ack(struct irq_data *d)
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@@ -109,8 +110,10 @@ static void xlp_pic_mask_ack(struct irq_data *d)
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static void xlp_pic_unmask(struct irq_data *d)
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{
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void *hd = irq_data_get_irq_handler_data(d);
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struct nlm_soc_info *nodep;
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int irt;
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nodep = nlm_current_node();
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irt = nlm_irq_to_irt(d->irq);
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if (irt == -1)
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return;
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@@ -120,7 +123,7 @@ static void xlp_pic_unmask(struct irq_data *d)
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extra_ack(d);
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}
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/* Ack is a single write, no need to lock */
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nlm_pic_ack(nlm_pic_base, irt);
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nlm_pic_ack(nodep->picbase, irt);
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}
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static struct irq_chip xlp_pic = {
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@@ -177,7 +180,11 @@ struct irq_chip nlm_cpu_intr = {
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void __init init_nlm_common_irqs(void)
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{
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int i, irq, irt;
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uint64_t irqmask;
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struct nlm_soc_info *nodep;
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nodep = nlm_current_node();
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irqmask = (1ULL << IRQ_TIMER);
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for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
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irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
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@@ -189,7 +196,7 @@ void __init init_nlm_common_irqs(void)
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nlm_smp_function_ipi_handler);
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irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
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nlm_smp_resched_ipi_handler);
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nlm_irq_mask |=
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irqmask |=
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((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
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#endif
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@@ -197,11 +204,11 @@ void __init init_nlm_common_irqs(void)
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irt = nlm_irq_to_irt(irq);
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if (irt == -1)
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continue;
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nlm_irq_mask |= (1ULL << irq);
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nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
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irqmask |= (1ULL << irq);
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nlm_pic_init_irt(nodep->picbase, irt, irq, 0);
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}
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nlm_irq_mask |= (1ULL << IRQ_TIMER);
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nodep->irqmask = irqmask;
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}
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void __init arch_init_irq(void)
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@@ -209,29 +216,39 @@ void __init arch_init_irq(void)
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/* Initialize the irq descriptors */
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init_nlm_common_irqs();
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write_c0_eimr(nlm_irq_mask);
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write_c0_eimr(nlm_current_node()->irqmask);
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}
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void __cpuinit nlm_smp_irq_init(void)
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{
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/* set interrupt mask for non-zero cpus */
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write_c0_eimr(nlm_irq_mask);
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write_c0_eimr(nlm_current_node()->irqmask);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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uint64_t eirr;
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int i;
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int i, node;
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node = nlm_nodeid();
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eirr = read_c0_eirr() & read_c0_eimr();
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if (eirr & (1 << IRQ_TIMER)) {
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do_IRQ(IRQ_TIMER);
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return;
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}
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#ifdef CONFIG_SMP
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if (eirr & IRQ_IPI_SMP_FUNCTION) {
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do_IRQ(IRQ_IPI_SMP_FUNCTION);
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return;
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}
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if (eirr & IRQ_IPI_SMP_RESCHEDULE) {
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do_IRQ(IRQ_IPI_SMP_RESCHEDULE);
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return;
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}
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#endif
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i = __ilog2_u64(eirr);
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if (i == -1)
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return;
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do_IRQ(i);
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do_IRQ(nlm_irq_to_xirq(node, i));
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}
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