Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (35 commits) powerpc/5121: make clock debug output more readable powerpc/5xxx: Add common mpc5xxx_get_bus_frequency() function powerpc/5200: Update pcm030.dts to add i2c eeprom and delete cruft powerpc/5200: convert mpc52xx_psc_spi to use cs_control callback fbdev/xilinxfb: Fix improper casting and tighen up probe path usb/ps3: Add missing annotations powerpc: Add memory clobber to mtspr() powerpc: Fix invalid construct in our CPU selection Kconfig ps3rom: Use ps3_system_bus_[gs]et_drvdata() instead of direct access powerpc: Add configurable -Werror for arch/powerpc of_serial: Add UPF_FIXED_TYPE flag drivers/hvc: Add missing __devexit_p() net/ps3: gelic - Add missing annotations powerpc: Introduce macro spin_event_timeout() powerpc/warp: Fix ISA_DMA_THRESHOLD default powerpc/bootwrapper: Custom build options for XPedite52xx targets powerpc/85xx: Add defconfig for X-ES MPC85xx boards powerpc/85xx: Add dts files for X-ES MPC85xx boards powerpc/85xx: Add platform support for X-ES MPC85xx boards 83xx: add support for the kmeter1 board. ...
This commit is contained in:
Linus Torvalds
@@ -167,7 +167,7 @@
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interrupt-parent = <&ipic>;
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interrupts = <39 0x8>;
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phy_type = "ulpi";
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port1;
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port0;
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};
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/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
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usb@23000 {
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||||
|
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@@ -152,6 +152,16 @@
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interrupt-parent = <&mpic>;
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dfsrr;
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hwmon@48 {
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||||
compatible = "national,lm92";
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reg = <0x48>;
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};
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hwmon@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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||||
};
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||||
|
||||
rtc@51 {
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compatible = "epson,rx8581";
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reg = <0x00000051>;
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||||
|
||||
520
arch/powerpc/boot/dts/kmeter1.dts
Normal file
520
arch/powerpc/boot/dts/kmeter1.dts
Normal file
@@ -0,0 +1,520 @@
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/*
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* Keymile KMETER1 Device Tree Source
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*
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* 2008 DENX Software Engineering GmbH
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "KMETER1";
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compatible = "keymile,KMETER1";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet_piggy2;
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ethernet1 = &enet_estar1;
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ethernet2 = &enet_estar2;
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ethernet3 = &enet_eth1;
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ethernet4 = &enet_eth2;
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ethernet5 = &enet_eth3;
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ethernet6 = &enet_eth4;
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serial0 = &serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8360@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <32768>; // L1, 32K
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i-cache-size = <32768>; // L1, 32K
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timebase-frequency = <0>; /* Filled in by U-Boot */
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bus-frequency = <0>; /* Filled in by U-Boot */
|
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clock-frequency = <0>; /* Filled in by U-Boot */
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||||
};
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};
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|
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memory {
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device_type = "memory";
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reg = <0 0>; /* Filled in by U-Boot */
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};
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|
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soc8360@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8360-immr", "simple-bus";
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ranges = <0x0 0xe0000000 0x00200000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>; /* Filled in by U-Boot */
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
|
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <264000000>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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interrupt-parent = <&ipic>;
|
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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ipic: pic@700 {
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "fsl,pq2pro-pic", "fsl,ipic";
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interrupt-controller;
|
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reg = <0x700 0x100>;
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};
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par_io@1400 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1400 0x100>;
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compatible = "fsl,mpc8360-par_io";
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num-ports = <7>;
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pio_ucc1: ucc_pin@0 {
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reg = <0>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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0 3 1 0 1 0 /* TxD0 */
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0 4 1 0 1 0 /* TxD1 */
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0 5 1 0 1 0 /* TxD2 */
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0 6 1 0 1 0 /* TxD3 */
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0 9 2 0 1 0 /* RxD0 */
|
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0 10 2 0 1 0 /* RxD1 */
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0 11 2 0 1 0 /* RxD2 */
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0 12 2 0 1 0 /* RxD3 */
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||||
0 7 1 0 1 0 /* TX_EN */
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0 8 1 0 1 0 /* TX_ER */
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0 15 2 0 1 0 /* RX_DV */
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0 16 2 0 1 0 /* RX_ER */
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||||
0 0 2 0 1 0 /* RX_CLK */
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||||
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
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||||
2 8 2 0 1 0 /* GTX125 - CLK9 */
|
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>;
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};
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pio_ucc2: ucc_pin@1 {
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||||
reg = <1>;
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pio-map = <
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||||
/* port pin dir open_drain assignment has_irq */
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||||
0 1 3 0 2 0 /* MDIO */
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||||
0 2 1 0 1 0 /* MDC */
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||||
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||||
0 17 1 0 1 0 /* TxD0 */
|
||||
0 18 1 0 1 0 /* TxD1 */
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0 19 1 0 1 0 /* TxD2 */
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0 20 1 0 1 0 /* TxD3 */
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||||
0 23 2 0 1 0 /* RxD0 */
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||||
0 24 2 0 1 0 /* RxD1 */
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0 25 2 0 1 0 /* RxD2 */
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0 26 2 0 1 0 /* RxD3 */
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0 21 1 0 1 0 /* TX_EN */
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0 22 1 0 1 0 /* TX_ER */
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||||
0 29 2 0 1 0 /* RX_DV */
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||||
0 30 2 0 1 0 /* RX_ER */
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||||
0 31 2 0 1 0 /* RX_CLK */
|
||||
2 2 1 0 2 0 /* GTX_CLK - CLK3 */
|
||||
2 3 2 0 1 0 /* GTX125 - CLK4 */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc4: ucc_pin@3 {
|
||||
reg = <3>;
|
||||
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
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||||
|
||||
1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
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||||
1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
|
||||
1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
|
||||
1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
|
||||
1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
|
||||
1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
|
||||
1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
|
||||
|
||||
2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc5: ucc_pin@4 {
|
||||
reg = <4>;
|
||||
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
|
||||
3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
|
||||
3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
|
||||
3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
|
||||
3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
|
||||
3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
|
||||
3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc6: ucc_pin@5 {
|
||||
reg = <5>;
|
||||
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
|
||||
3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
|
||||
3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
|
||||
3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
|
||||
3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
|
||||
3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
|
||||
3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc7: ucc_pin@6 {
|
||||
reg = <6>;
|
||||
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
|
||||
4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
|
||||
4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
|
||||
4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
|
||||
4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
|
||||
4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
|
||||
4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
|
||||
>;
|
||||
};
|
||||
|
||||
pio_ucc8: ucc_pin@7 {
|
||||
reg = <7>;
|
||||
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
0 2 1 0 1 0 /* MDC */
|
||||
|
||||
4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
|
||||
4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
|
||||
4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
|
||||
4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
|
||||
4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
|
||||
4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
|
||||
4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
|
||||
|
||||
2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
|
||||
>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qe@100000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0x100000 0x100000>;
|
||||
reg = <0x100000 0x480>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
brg-frequency = <0>; /* Filled in by U-Boot */
|
||||
bus-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x00010000 0x0000c000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0xc000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
|
||||
enet_estar1: ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk9";
|
||||
phy-handle = <&phy_estar1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
pio-handle = <&pio_ucc1>;
|
||||
};
|
||||
|
||||
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
|
||||
enet_estar2: ucc@3000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <2>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk4";
|
||||
phy-handle = <&phy_estar2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
pio-handle = <&pio_ucc2>;
|
||||
};
|
||||
|
||||
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
|
||||
enet_piggy2: ucc@3200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <4>;
|
||||
reg = <0x3200 0x200>;
|
||||
interrupts = <35>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk17";
|
||||
phy-handle = <&phy_piggy2>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc4>;
|
||||
};
|
||||
|
||||
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
|
||||
enet_eth1: ucc@2400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <5>;
|
||||
reg = <0x2400 0x200>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth1>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc5>;
|
||||
};
|
||||
|
||||
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
|
||||
enet_eth2: ucc@3400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <6>;
|
||||
reg = <0x3400 0x200>;
|
||||
interrupts = <41>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth2>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc6>;
|
||||
};
|
||||
|
||||
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
|
||||
enet_eth3: ucc@2600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <7>;
|
||||
reg = <0x2600 0x200>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth3>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc7>;
|
||||
};
|
||||
|
||||
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
|
||||
enet_eth4: ucc@3600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <8>;
|
||||
reg = <0x3600 0x200>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
phy-handle = <&phy_eth4>;
|
||||
phy-connection-type = "rmii";
|
||||
pio-handle = <&pio_ucc8>;
|
||||
};
|
||||
|
||||
mdio@3320 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3320 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
|
||||
phy_piggy2: ethernet-phy@00 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
|
||||
phy_eth1: ethernet-phy@08 {
|
||||
reg = <0x08>;
|
||||
};
|
||||
|
||||
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
|
||||
phy_eth2: ethernet-phy@09 {
|
||||
reg = <0x09>;
|
||||
};
|
||||
|
||||
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
|
||||
phy_eth3: ethernet-phy@0a {
|
||||
reg = <0x0a>;
|
||||
};
|
||||
|
||||
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
|
||||
phy_eth4: ethernet-phy@0b {
|
||||
reg = <0x0b>;
|
||||
};
|
||||
|
||||
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
|
||||
phy_estar1: ethernet-phy@10 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x10>;
|
||||
};
|
||||
|
||||
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
|
||||
phy_estar2: ethernet-phy@11 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x11>;
|
||||
};
|
||||
};
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <32 8 33 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xe0005000 0xd8>;
|
||||
ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */
|
||||
|
||||
flash@f0000000,0 {
|
||||
compatible = "cfi-flash";
|
||||
/*
|
||||
* The Intel P30 chip has 2 non-identical chips on
|
||||
* one die, so we need to define 2 seperate regions
|
||||
* that are scanned by physmap_of independantly.
|
||||
*/
|
||||
reg = <0 0x00000000 0x02000000
|
||||
0 0x02000000 0x02000000>; /* Filled in by U-Boot */
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0 0x40000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "env";
|
||||
reg = <0x40000 0x40000>;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "dtb";
|
||||
reg = <0x80000 0x20000>;
|
||||
};
|
||||
partition@a0000 {
|
||||
label = "kernel";
|
||||
reg = <0xa0000 0x300000>;
|
||||
};
|
||||
partition@3a0000 {
|
||||
label = "ramdisk";
|
||||
reg = <0x3a0000 0x800000>;
|
||||
};
|
||||
partition@ba0000 {
|
||||
label = "user";
|
||||
reg = <0xba0000 0x3460000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -17,6 +17,13 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
serial0 = &scc1;
|
||||
serial1 = &scc4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@@ -46,13 +53,13 @@
|
||||
#size-cells = <1>;
|
||||
reg = <0xf0010100 0x40>;
|
||||
|
||||
ranges = <0x0 0x0 0xfe000000 0x2000000
|
||||
ranges = <0x0 0x0 0xff800000 0x00800000
|
||||
0x1 0x0 0xf4500000 0x8000
|
||||
0x3 0x0 0xf8200000 0x8000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "jedec-flash";
|
||||
reg = <0x0 0x0 0x2000000>;
|
||||
reg = <0x0 0x0 0x00800000>;
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
};
|
||||
@@ -144,7 +151,7 @@
|
||||
reg = <0x119f0 0x10 0x115f0 0x10>;
|
||||
};
|
||||
|
||||
serial@11a00 {
|
||||
scc1: serial@11a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8272-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
@@ -155,7 +162,7 @@
|
||||
fsl,cpm-command = <0x800000>;
|
||||
};
|
||||
|
||||
serial@11a60 {
|
||||
scc4: serial@11a60 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8272-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
@@ -192,7 +199,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@11300 {
|
||||
eth0: ethernet@11300 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8272-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
@@ -205,7 +212,7 @@
|
||||
fsl,cpm-command = <0x12000300>;
|
||||
};
|
||||
|
||||
ethernet@11320 {
|
||||
eth1: ethernet@11320 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8272-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
|
||||
@@ -322,6 +322,21 @@
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
ipic-msi@7c0 {
|
||||
compatible = "fsl,ipic-msi";
|
||||
reg = <0x7c0 0x40>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <0x43 0x8
|
||||
0x4 0x8
|
||||
0x51 0x8
|
||||
0x52 0x8
|
||||
0x56 0x8
|
||||
0x57 0x8
|
||||
0x58 0x8
|
||||
0x59 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
|
||||
@@ -156,7 +156,7 @@
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
port0;
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
|
||||
@@ -153,7 +153,7 @@
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
port0;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
|
||||
@@ -155,7 +155,7 @@
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
@@ -169,7 +169,7 @@
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
@@ -155,7 +155,7 @@
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
@@ -169,7 +169,7 @@
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
@@ -153,7 +153,7 @@
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
@@ -167,7 +167,7 @@
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8379-esdhc";
|
||||
compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
@@ -24,6 +24,8 @@
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
ethernet5 = &enet5;
|
||||
ethernet7 = &enet7;
|
||||
pci1 = &pci1;
|
||||
rapidio0 = &rio0;
|
||||
};
|
||||
@@ -70,8 +72,30 @@
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
bank-width = <1>;
|
||||
device-width = <1>;
|
||||
partition@0 {
|
||||
label = "ramdisk";
|
||||
reg = <0x00000000 0x01c00000>;
|
||||
};
|
||||
partition@1c00000 {
|
||||
label = "kernel";
|
||||
reg = <0x01c00000 0x002e0000>;
|
||||
};
|
||||
partiton@1ee0000 {
|
||||
label = "dtb";
|
||||
reg = <0x01ee0000 0x00020000>;
|
||||
};
|
||||
partition@1f00000 {
|
||||
label = "firmware";
|
||||
reg = <0x01f00000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
partition@1f80000 {
|
||||
label = "u-boot";
|
||||
reg = <0x01f80000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
bcsr@1,0 {
|
||||
@@ -466,6 +490,37 @@
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy5: ethernet-phy@04 {
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x04>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy7: ethernet-phy@06 {
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x6>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
mdio@3520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3520 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
tbi0: tbi-phy@15 {
|
||||
reg = <0x15>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
mdio@3720 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3720 0x38>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
tbi1: tbi-phy@17 {
|
||||
reg = <0x17>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ucc@2200 {
|
||||
@@ -513,6 +568,36 @@
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
enet5: ucc@3400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <6>;
|
||||
reg = <0x3400 0x200>;
|
||||
interrupts = <41>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "none";
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&qe_phy5>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
enet7: ucc@3600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <8>;
|
||||
reg = <0x3600 0x200>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "none";
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&qe_phy7>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
@@ -258,34 +258,16 @@
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
/* FIXME: EEPROM */
|
||||
eeprom@52 {
|
||||
compatible = "catalyst,24c32";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
|
||||
/* This is only an example device to show the usage of gpios. It maps all available
|
||||
* gpios to the "gpio-provider" device.
|
||||
*/
|
||||
gpio {
|
||||
compatible = "gpio-provider";
|
||||
|
||||
/* mpc52xx exp.con patchfield */
|
||||
gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */
|
||||
&gpio_wkup 1 0 /* GPIO_WKUP_6 14c */
|
||||
&gpio_wkup 6 0 /* PSC2_4 43c x5-11 */
|
||||
&gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */
|
||||
&gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */
|
||||
&gpt2 0 0 /* timer2 12d x4-4 */
|
||||
&gpt3 0 0 /* timer3 13d x6-4 */
|
||||
&gpt4 0 0 /* timer4 61c x2-16 */
|
||||
&gpt5 0 0 /* timer5 44c x7-11 */
|
||||
&gpt6 0 0 /* timer6 60c x8-15 */
|
||||
&gpt7 0 0 /* timer7 36a x17-9 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
|
||||
@@ -144,7 +144,7 @@
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
port0;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
|
||||
696
arch/powerpc/boot/dts/xcalibur1501.dts
Normal file
696
arch/powerpc/boot/dts/xcalibur1501.dts
Normal file
@@ -0,0 +1,696 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
|
||||
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
|
||||
*
|
||||
* XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "xes,xcalibur1501";
|
||||
compatible = "xes,xcalibur1501", "xes,MPC8572";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8572@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xef005000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Local bus region mappings */
|
||||
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */
|
||||
1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */
|
||||
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
|
||||
3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */
|
||||
4 0 0 0xe9000000 0x100000>; /* CS4: USB */
|
||||
|
||||
nor-boot@0,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Primary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Primary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Primary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Primary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Primary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
//reg = <0xf0000000 0x08000000>; /* 128MB */
|
||||
reg = <1 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Secondary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Secondary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Secondary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Secondary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Secondary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
|
||||
* Micron MT29F8G08DAA (2x 512 MB), or Micron
|
||||
* MT29F16G08FAA (2x 1 GB), depending on the build
|
||||
* configuration
|
||||
*/
|
||||
compatible = "fsl,mpc8572-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <2 0 0x40000>;
|
||||
/* U-Boot should fix this up if chip size > 1 GB */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@4,0 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <4 0 0x100000>;
|
||||
bus-width = <32>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc8572@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
ranges = <0x0 0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2, 1M
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
temp-sensor@48 {
|
||||
compatible = "dallas,ds1631", "dallas,ds1621";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
cpu-supervisor@51 {
|
||||
compatible = "dallas,ds4510";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,at24c128b";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
pcie-switch@6a {
|
||||
compatible = "plx,pex8648";
|
||||
reg = <0x6a>;
|
||||
};
|
||||
|
||||
/* On-board signals for VID, flash, serial */
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* PMC0/XMC0 signals */
|
||||
gpio2: gpio@1c {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1c>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* PMC1/XMC1 signals */
|
||||
gpio3: gpio@1d {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1d>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* CompactPCI signals (sysen, GA[4:0]) */
|
||||
gpio4: gpio@1e {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1e>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* CompactPCI J5 GPIO and FAL/DEG/PRST */
|
||||
gpio5: gpio@1f {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1f>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 1 front panel 0 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <4 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <4 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
phy2: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
phy3: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
reg = <0x4>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 2 front panel 1 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 3 PICMG2.16 backplane port 0 */
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 4 PICMG2.16 backplane port 1 */
|
||||
enet3: ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* UART0 */
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
gpio0: gpio@f000 {
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x1000>;
|
||||
interrupts = <47 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio0 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&gpio0 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PME (pattern-matcher) */
|
||||
pme@10000 {
|
||||
compatible = "fsl,mpc8572-pme", "pme8572";
|
||||
reg = <0x10000 0x5000>;
|
||||
interrupts = <57 2 64 2 65 2 66 2 67 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@2f000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x2f000 0x1000>;
|
||||
interupts = <61 2 >;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@15000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x15000 0x1000>;
|
||||
interupts = <75 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* PCI Express controller 3 @ ef008000 is not used.
|
||||
* This would have been pci0 on other mpc85xx platforms.
|
||||
*
|
||||
* PCI Express controller 2 @ ef009000 is not used.
|
||||
* This would have been pci1 on other mpc85xx platforms.
|
||||
*/
|
||||
|
||||
/* PCI Express controller 1, wired to PEX8648 PCIe switch */
|
||||
pci2: pcie@ef00a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef00a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
466
arch/powerpc/boot/dts/xpedite5200.dts
Normal file
466
arch/powerpc/boot/dts/xpedite5200.dts
Normal file
@@ -0,0 +1,466 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
|
||||
* Based on TQM8548 device tree
|
||||
*
|
||||
* XPedite5200 PrPMC/XMC module based on MPC8548E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "xes,xpedite5200";
|
||||
compatible = "xes,xpedite5200", "xes,MPC8548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
soc@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>;
|
||||
compatible = "fsl,mpc8548-immr", "simple-bus";
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8548-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8548-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
/* On-card I2C */
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
/*
|
||||
* Board GPIO:
|
||||
* 0: BRD_CFG0 (1: P14 IO present)
|
||||
* 1: BRD_CFG1 (1: FP ethernet present)
|
||||
* 2: BRD_CFG2 (1: XMC IO present)
|
||||
* 3: XMC root complex indicator
|
||||
* 4: Flash boot device indicator
|
||||
* 5: Flash write protect enable
|
||||
* 6: PMC monarch indicator
|
||||
* 7: PMC EREADY
|
||||
*/
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9556";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* P14 GPIO */
|
||||
gpio2: gpio@19 {
|
||||
compatible = "nxp,pca9556";
|
||||
reg = <0x19>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,at24c16";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
dtt@48 {
|
||||
compatible = "maxim,max1237";
|
||||
reg = <0x34>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Off-card I2C */
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC1: Front panel port 0 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
phy2: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
phy3: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x4>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC2: Front panel port 1 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC3: Rear panel port 2 */
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC4: Rear panel port 3 */
|
||||
enet3: ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { // global utilities reg
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xef005000 0x100>; // BRx, ORx, etc.
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xfc000000 0x04000000 // NOR boot flash
|
||||
1 0x0 0xf8000000 0x04000000 // NOR expansion flash
|
||||
2 0x0 0xef800000 0x00010000 // NAND CE1
|
||||
3 0x0 0xef840000 0x00010000 // NAND CE2
|
||||
>;
|
||||
|
||||
nor-boot@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "Primary OS";
|
||||
reg = <0x00000000 0x180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "Secondary OS";
|
||||
reg = <0x00180000 0x180000>;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "User";
|
||||
reg = <0x00300000 0x3c80000>;
|
||||
};
|
||||
partition@3f80000 {
|
||||
label = "Boot firmware";
|
||||
reg = <0x03f80000 0x80000>;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <1 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "Filesystem";
|
||||
reg = <0x00000000 0x3f80000>;
|
||||
};
|
||||
partition@3f80000 {
|
||||
label = "Alternate boot firmware";
|
||||
reg = <0x03f80000 0x80000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xes,address-ctl-nand";
|
||||
reg = <2 0x0 0x10000>;
|
||||
cle-line = <0x8>; /* CLE tied to A3 */
|
||||
ale-line = <0x10>; /* ALE tied to A4 */
|
||||
|
||||
/* U-Boot should fix this up */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC interface */
|
||||
pci0: pci@ef008000 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xef008000 0x1000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
|
||||
0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
|
||||
};
|
||||
|
||||
/* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
|
||||
};
|
||||
506
arch/powerpc/boot/dts/xpedite5200_xmon.dts
Normal file
506
arch/powerpc/boot/dts/xpedite5200_xmon.dts
Normal file
@@ -0,0 +1,506 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
|
||||
* Based on TQM8548 device tree
|
||||
*
|
||||
* XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the
|
||||
* xMon boot loader memory map which differs from U-Boot's.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "xes,xpedite5200";
|
||||
compatible = "xes,xpedite5200", "xes,MPC8548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
form-factor = "PMC/XMC";
|
||||
boot-bank = <0x0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>; // Filled in by boot loader
|
||||
};
|
||||
|
||||
soc@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>;
|
||||
compatible = "fsl,mpc8548-immr", "simple-bus";
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8548-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8548-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
/* On-card I2C */
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
/*
|
||||
* Board GPIO:
|
||||
* 0: BRD_CFG0 (1: P14 IO present)
|
||||
* 1: BRD_CFG1 (1: FP ethernet present)
|
||||
* 2: BRD_CFG2 (1: XMC IO present)
|
||||
* 3: XMC root complex indicator
|
||||
* 4: Flash boot device indicator
|
||||
* 5: Flash write protect enable
|
||||
* 6: PMC monarch indicator
|
||||
* 7: PMC EREADY
|
||||
*/
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9556";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
/* P14 GPIO */
|
||||
gpio2: gpio@19 {
|
||||
compatible = "nxp,pca9556";
|
||||
reg = <0x19>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,at24c16";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
dtt@48 {
|
||||
compatible = "maxim,max1237";
|
||||
reg = <0x34>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Off-card I2C */
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8548-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC1: Front panel port 0 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
phy2: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
phy3: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x4>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC2: Front panel port 1 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC3: Rear panel port 2 */
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC4: Rear panel port 3 */
|
||||
enet3: ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <9600>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <9600>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { // global utilities reg
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xef005000 0x100>; // BRx, ORx, etc.
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xf8000000 0x08000000 // NOR boot flash
|
||||
1 0x0 0xf0000000 0x08000000 // NOR expansion flash
|
||||
2 0x0 0xe8000000 0x00010000 // NAND CE1
|
||||
3 0x0 0xe8010000 0x00010000 // NAND CE2
|
||||
>;
|
||||
|
||||
nor-boot@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "Primary OS";
|
||||
reg = <0x00000000 0x180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "Secondary OS";
|
||||
reg = <0x00180000 0x180000>;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "User";
|
||||
reg = <0x00300000 0x3c80000>;
|
||||
};
|
||||
partition@3f80000 {
|
||||
label = "Boot firmware";
|
||||
reg = <0x03f80000 0x80000>;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <1 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "Filesystem";
|
||||
reg = <0x00000000 0x3f80000>;
|
||||
};
|
||||
partition@3f80000 {
|
||||
label = "Alternate boot firmware";
|
||||
reg = <0x03f80000 0x80000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xes,address-ctl-nand";
|
||||
reg = <2 0x0 0x10000>;
|
||||
cle-line = <0x8>; /* CLE tied to A3 */
|
||||
ale-line = <0x10>; /* ALE tied to A4 */
|
||||
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC interface */
|
||||
pci0: pci@ef008000 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xef008000 0x1000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
|
||||
};
|
||||
|
||||
/* XMC PCIe */
|
||||
pci1: pcie@ef00a000 {
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x00000 0 0 1 &mpic 0 1
|
||||
0x00000 0 0 2 &mpic 1 1
|
||||
0x00000 0 0 3 &mpic 2 1
|
||||
0x00000 0 0 4 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
|
||||
clock-frequency = <33333333>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xef00a000 0x1000>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xc0000000 0x02000000 0
|
||||
0xc0000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0x01000000 0
|
||||
0x00000000 0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Needed for dtbImage boot wrapper compatibility */
|
||||
chosen {
|
||||
linux,stdout-path = &serial0;
|
||||
};
|
||||
};
|
||||
640
arch/powerpc/boot/dts/xpedite5301.dts
Normal file
640
arch/powerpc/boot/dts/xpedite5301.dts
Normal file
@@ -0,0 +1,640 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
|
||||
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
|
||||
*
|
||||
* XPedite5301 PMC/XMC module based on MPC8572E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "xes,xpedite5301";
|
||||
compatible = "xes,xpedite5301", "xes,MPC8572";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
form-factor = "PMC/XMC";
|
||||
boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8572@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xef005000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Local bus region mappings */
|
||||
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
|
||||
1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
|
||||
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
|
||||
3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
|
||||
|
||||
nor-boot@0,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Primary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Primary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Primary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Primary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Primary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
//reg = <0xf0000000 0x08000000>; /* 128MB */
|
||||
reg = <1 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Secondary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Secondary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Secondary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Secondary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Secondary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
|
||||
* Micron MT29F8G08DAA (2x 512 MB), or Micron
|
||||
* MT29F16G08FAA (2x 1 GB), depending on the build
|
||||
* configuration
|
||||
*/
|
||||
compatible = "fsl,mpc8572-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <2 0 0x40000>;
|
||||
/* U-Boot should fix this up if chip size > 1 GB */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
soc8572@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
ranges = <0x0 0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2, 1M
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
temp-sensor@48 {
|
||||
compatible = "dallas,ds1631", "dallas,ds1621";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
cpu-supervisor@51 {
|
||||
compatible = "dallas,ds4510";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,at24c128b";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
pcie-switch@70 {
|
||||
compatible = "plx,pex8518";
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio2: gpio@1c {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1c>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio3: gpio@1e {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1e>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio4: gpio@1f {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1f>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 1 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 2 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* UART0 */
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
gpio0: gpio@f000 {
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x1000>;
|
||||
interrupts = <47 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio0 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&gpio0 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PME (pattern-matcher) */
|
||||
pme@10000 {
|
||||
compatible = "fsl,mpc8572-pme", "pme8572";
|
||||
reg = <0x10000 0x5000>;
|
||||
interrupts = <57 2 64 2 65 2 66 2 67 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@2f000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x2f000 0x1000>;
|
||||
interupts = <61 2 >;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@15000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x15000 0x1000>;
|
||||
interupts = <75 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* PCI Express controller 3 @ ef008000 is not used.
|
||||
* This would have been pci0 on other mpc85xx platforms.
|
||||
*/
|
||||
|
||||
/* PCI Express controller 2, wired to XMC P15 connector */
|
||||
pci1: pcie@ef009000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef009000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xc0000000
|
||||
0x2000000 0x0 0xc0000000
|
||||
0x0 0x10000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 1, wired to PEX8112 for PMC interface */
|
||||
pci2: pcie@ef00a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef00a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
707
arch/powerpc/boot/dts/xpedite5330.dts
Normal file
707
arch/powerpc/boot/dts/xpedite5330.dts
Normal file
@@ -0,0 +1,707 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
|
||||
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
|
||||
*
|
||||
* XPedite5330 3U CompactPCI module based on MPC8572E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "xes,xpedite5330";
|
||||
compatible = "xes,xpedite5330", "xes,MPC8572";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
form-factor = "3U CompactPCI";
|
||||
boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
pmcslots {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmcslot@0 {
|
||||
cell-index = <0>;
|
||||
/*
|
||||
* boolean properties (true if defined):
|
||||
* monarch;
|
||||
* module-present;
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
xmcslots {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
xmcslot@0 {
|
||||
cell-index = <0>;
|
||||
/*
|
||||
* boolean properties (true if defined):
|
||||
* module-present;
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
cpci {
|
||||
/*
|
||||
* boolean properties (true if defined):
|
||||
* system-controller;
|
||||
*/
|
||||
system-controller;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8572@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xef005000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Local bus region mappings */
|
||||
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
|
||||
1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
|
||||
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
|
||||
3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
|
||||
|
||||
nor-boot@0,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Primary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Primary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Primary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Primary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Primary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
//reg = <0xf0000000 0x08000000>; /* 128MB */
|
||||
reg = <1 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Secondary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Secondary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Secondary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Secondary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Secondary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
|
||||
* Micron MT29F8G08DAA (2x 512 MB), or Micron
|
||||
* MT29F16G08FAA (2x 1 GB), depending on the build
|
||||
* configuration
|
||||
*/
|
||||
compatible = "fsl,mpc8572-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <2 0 0x40000>;
|
||||
/* U-Boot should fix this up if chip size > 1 GB */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
soc8572@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
ranges = <0x0 0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2, 1M
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
temp-sensor@48 {
|
||||
compatible = "dallas,ds1631", "dallas,ds1621";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
cpu-supervisor@51 {
|
||||
compatible = "dallas,ds4510";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,at24c128b";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
pcie-switch@70 {
|
||||
compatible = "plx,pex8518";
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio2: gpio@1c {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1c>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio3: gpio@1e {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1e>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio4: gpio@1f {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1f>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 1 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 2 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* UART0 */
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
gpio0: gpio@f000 {
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x1000>;
|
||||
interrupts = <47 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio0 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&gpio0 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PME (pattern-matcher) */
|
||||
pme@10000 {
|
||||
compatible = "fsl,mpc8572-pme", "pme8572";
|
||||
reg = <0x10000 0x5000>;
|
||||
interrupts = <57 2 64 2 65 2 66 2 67 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@2f000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x2f000 0x1000>;
|
||||
interupts = <61 2 >;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@15000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x15000 0x1000>;
|
||||
interupts = <75 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
|
||||
pci0: pcie@ef008000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef008000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0xe0000000
|
||||
0x02000000 0x0 0xe0000000
|
||||
0x0 0x10000000
|
||||
|
||||
0x01000000 0x0 0x0
|
||||
0x01000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 2, PMC module via PEX8112 bridge */
|
||||
pci1: pcie@ef009000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef009000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xc0000000
|
||||
0x2000000 0x0 0xc0000000
|
||||
0x0 0x10000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 1, XMC P15 */
|
||||
pci2: pcie@ef00a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef00a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
638
arch/powerpc/boot/dts/xpedite5370.dts
Normal file
638
arch/powerpc/boot/dts/xpedite5370.dts
Normal file
@@ -0,0 +1,638 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
|
||||
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
|
||||
*
|
||||
* XPedite5370 3U VPX single-board computer based on MPC8572E
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "xes,xpedite5370";
|
||||
compatible = "xes,xpedite5370", "xes,MPC8572";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8572@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
localbus@ef005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xef005000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Local bus region mappings */
|
||||
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
|
||||
1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
|
||||
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
|
||||
3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
|
||||
|
||||
nor-boot@0,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Primary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Primary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Primary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Primary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Primary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nor-alternate@1,0 {
|
||||
compatible = "amd,s29gl01gp", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
//reg = <0xf0000000 0x08000000>; /* 128MB */
|
||||
reg = <1 0 0x8000000>; /* 128MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Secondary user space";
|
||||
reg = <0x00000000 0x6f00000>; /* 111 MB */
|
||||
};
|
||||
partition@6f00000 {
|
||||
label = "Secondary kernel";
|
||||
reg = <0x6f00000 0x1000000>; /* 16 MB */
|
||||
};
|
||||
partition@7f00000 {
|
||||
label = "Secondary DTB";
|
||||
reg = <0x7f00000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f40000 {
|
||||
label = "Secondary U-Boot environment";
|
||||
reg = <0x7f40000 0x40000>; /* 256 KB */
|
||||
};
|
||||
partition@7f80000 {
|
||||
label = "Secondary U-Boot";
|
||||
reg = <0x7f80000 0x80000>; /* 512 KB */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
|
||||
* Micron MT29F8G08DAA (2x 512 MB), or Micron
|
||||
* MT29F16G08FAA (2x 1 GB), depending on the build
|
||||
* configuration
|
||||
*/
|
||||
compatible = "fsl,mpc8572-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <2 0 0x40000>;
|
||||
/* U-Boot should fix this up if chip size > 1 GB */
|
||||
partition@0 {
|
||||
label = "NAND Filesystem";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
soc8572@ef000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
ranges = <0x0 0 0xef000000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2, 1M
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
temp-sensor@48 {
|
||||
compatible = "dallas,ds1631", "dallas,ds1621";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
cpu-supervisor@51 {
|
||||
compatible = "dallas,ds4510";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "atmel,at24c128b";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00",
|
||||
"dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
pcie-switch@70 {
|
||||
compatible = "plx,pex8518";
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18 {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x18>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio2: gpio@1c {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1c>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio3: gpio@1e {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1e>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
|
||||
gpio4: gpio@1f {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1f>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
polarity = <0x00>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <76 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <77 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <78 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <79 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8572-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 1 */
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy1: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* eTSEC 2 */
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* UART0 */
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||
"fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x9fe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
gpio0: gpio@f000 {
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x1000>;
|
||||
interrupts = <47 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio0 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&gpio0 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PME (pattern-matcher) */
|
||||
pme@10000 {
|
||||
compatible = "fsl,mpc8572-pme", "pme8572";
|
||||
reg = <0x10000 0x5000>;
|
||||
interrupts = <57 2 64 2 65 2 66 2 67 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@2f000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x2f000 0x1000>;
|
||||
interupts = <61 2 >;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
tlu@15000 {
|
||||
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
|
||||
reg = <0x15000 0x1000>;
|
||||
interupts = <75 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* PCI Express controller 3 @ ef008000 is not used.
|
||||
* This would have been pci0 on other mpc85xx platforms.
|
||||
*/
|
||||
|
||||
/* PCI Express controller 2, wired to VPX P1,P2 backplane */
|
||||
pci1: pcie@ef009000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef009000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xc0000000
|
||||
0x2000000 0x0 0xc0000000
|
||||
0x0 0x10000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCI Express controller 1, wired to PEX8518 PCIe switch */
|
||||
pci2: pcie@ef00a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xef00a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
|
||||
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user