Merge branch 'clk-qcom-sdm845' into clk-next
* clk-qcom-sdm845: clk: qcom: Export clk_fabia_pll_configure() clk: qcom: Add video clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Video clock bindings clk: qcom: Add Global Clock controller (GCC) driver for SDM845 clk: qcom: Add DT bindings for SDM845 gcc clock controller clk: qcom: Configure the RCGs to a safe source as needed clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks clk: qcom: Simplify gdsc status checking logic clk: qcom: gdsc: Add support to poll CFG register to check GDSC state clk: qcom: gdsc: Add support to poll for higher timeout value clk: qcom: gdsc: Add support to reset AON and block reset logic clk: qcom: Add support for controlling Fabia PLL clk: qcom: Clear hardware clock control bit of RCG Also fixup the Kconfig mess where SDM845 GCC has msm8998 in the description and also the video Kconfig says things slightly differently from the GCC one so just make it the same.
This commit is contained in:
Stephen Boyd
@@ -226,6 +226,25 @@ config MSM_GCC_8998
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
i2c, USB, UFS, SD/eMMC, PCIe, etc.
|
||||
|
||||
config SDM_GCC_845
|
||||
tristate "SDM845 Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
depends on COMMON_CLK_QCOM
|
||||
help
|
||||
Support for the global clock controller on SDM845 devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
i2C, USB, UFS, SDDC, PCIe, etc.
|
||||
|
||||
config SDM_VIDEOCC_845
|
||||
tristate "SDM845 Video Clock Controller"
|
||||
depends on COMMON_CLK_QCOM
|
||||
select SDM_GCC_845
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the video clock controller on SDM845 devices.
|
||||
Say Y if you want to support video devices and functionality such as
|
||||
video encode and decode.
|
||||
|
||||
config SPMI_PMIC_CLKDIV
|
||||
tristate "SPMI PMIC clkdiv Support"
|
||||
depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
|
||||
|
||||
@@ -38,4 +38,6 @@ obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
|
||||
obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
|
||||
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
|
||||
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
|
||||
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
|
||||
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
|
||||
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
@@ -58,6 +58,8 @@
|
||||
#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
|
||||
#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
|
||||
#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
|
||||
#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
|
||||
#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
|
||||
|
||||
const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
|
||||
[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
|
||||
@@ -90,6 +92,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
|
||||
[PLL_OFF_TEST_CTL] = 0x1c,
|
||||
[PLL_OFF_STATUS] = 0x24,
|
||||
},
|
||||
[CLK_ALPHA_PLL_TYPE_FABIA] = {
|
||||
[PLL_OFF_L_VAL] = 0x04,
|
||||
[PLL_OFF_USER_CTL] = 0x0c,
|
||||
[PLL_OFF_USER_CTL_U] = 0x10,
|
||||
[PLL_OFF_CONFIG_CTL] = 0x14,
|
||||
[PLL_OFF_CONFIG_CTL_U] = 0x18,
|
||||
[PLL_OFF_TEST_CTL] = 0x1c,
|
||||
[PLL_OFF_TEST_CTL_U] = 0x20,
|
||||
[PLL_OFF_STATUS] = 0x24,
|
||||
[PLL_OFF_OPMODE] = 0x2c,
|
||||
[PLL_OFF_FRAC] = 0x38,
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
||||
|
||||
@@ -108,6 +122,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
||||
#define PLL_HUAYRA_N_MASK 0xff
|
||||
#define PLL_HUAYRA_ALPHA_WIDTH 16
|
||||
|
||||
#define FABIA_OPMODE_STANDBY 0x0
|
||||
#define FABIA_OPMODE_RUN 0x1
|
||||
|
||||
#define FABIA_PLL_OUT_MASK 0x7
|
||||
#define FABIA_PLL_RATE_MARGIN 500
|
||||
|
||||
#define pll_alpha_width(p) \
|
||||
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
|
||||
ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
|
||||
@@ -441,16 +461,12 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
return alpha_pll_calc_rate(prate, l, a, alpha_width);
|
||||
}
|
||||
|
||||
static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
|
||||
int (*is_enabled)(struct clk_hw *))
|
||||
|
||||
static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
|
||||
{
|
||||
int ret;
|
||||
u32 mode;
|
||||
|
||||
if (!is_enabled(&pll->clkr.hw) ||
|
||||
!(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
|
||||
return 0;
|
||||
|
||||
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
|
||||
|
||||
/* Latch the input to the PLL */
|
||||
@@ -489,6 +505,16 @@ static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
|
||||
int (*is_enabled)(struct clk_hw *))
|
||||
{
|
||||
if (!is_enabled(&pll->clkr.hw) ||
|
||||
!(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
|
||||
return 0;
|
||||
|
||||
return __clk_alpha_pll_update_latch(pll);
|
||||
}
|
||||
|
||||
static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long prate,
|
||||
int (*is_enabled)(struct clk_hw *))
|
||||
@@ -832,3 +858,265 @@ const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
|
||||
.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
|
||||
|
||||
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config)
|
||||
{
|
||||
u32 val, mask;
|
||||
|
||||
if (config->l)
|
||||
regmap_write(regmap, PLL_L_VAL(pll), config->l);
|
||||
|
||||
if (config->alpha)
|
||||
regmap_write(regmap, PLL_FRAC(pll), config->alpha);
|
||||
|
||||
if (config->config_ctl_val)
|
||||
regmap_write(regmap, PLL_CONFIG_CTL(pll),
|
||||
config->config_ctl_val);
|
||||
|
||||
if (config->post_div_mask) {
|
||||
mask = config->post_div_mask;
|
||||
val = config->post_div_val;
|
||||
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
|
||||
}
|
||||
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
|
||||
PLL_UPDATE_BYPASS);
|
||||
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
|
||||
|
||||
static int alpha_pll_fabia_enable(struct clk_hw *hw)
|
||||
{
|
||||
int ret;
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 val, opmode_val;
|
||||
struct regmap *regmap = pll->clkr.regmap;
|
||||
|
||||
ret = regmap_read(regmap, PLL_MODE(pll), &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* If in FSM mode, just vote for it */
|
||||
if (val & PLL_VOTE_FSM_ENA) {
|
||||
ret = clk_enable_regmap(hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
return wait_for_pll_enable_active(pll);
|
||||
}
|
||||
|
||||
ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Skip If PLL is already running */
|
||||
if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
|
||||
return 0;
|
||||
|
||||
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
|
||||
PLL_RESET_N);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = wait_for_pll_enable_lock(pll);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
|
||||
FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
|
||||
PLL_OUTCTRL);
|
||||
}
|
||||
|
||||
static void alpha_pll_fabia_disable(struct clk_hw *hw)
|
||||
{
|
||||
int ret;
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 val;
|
||||
struct regmap *regmap = pll->clkr.regmap;
|
||||
|
||||
ret = regmap_read(regmap, PLL_MODE(pll), &val);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* If in FSM mode, just unvote it */
|
||||
if (val & PLL_FSM_ENA) {
|
||||
clk_disable_regmap(hw);
|
||||
return;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* Disable main outputs */
|
||||
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
|
||||
0);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* Place the PLL in STANDBY */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
|
||||
}
|
||||
|
||||
static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 l, frac, alpha_width = pll_alpha_width(pll);
|
||||
|
||||
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
|
||||
regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
|
||||
|
||||
return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
|
||||
}
|
||||
|
||||
static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long prate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 val, l, alpha_width = pll_alpha_width(pll);
|
||||
u64 a;
|
||||
unsigned long rrate;
|
||||
int ret = 0;
|
||||
|
||||
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
|
||||
|
||||
/*
|
||||
* Due to limited number of bits for fractional rate programming, the
|
||||
* rounded up rate could be marginally higher than the requested rate.
|
||||
*/
|
||||
if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
|
||||
pr_err("Call set rate on the PLL with rounded rates!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
|
||||
regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
|
||||
|
||||
return __clk_alpha_pll_update_latch(pll);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_alpha_pll_fabia_ops = {
|
||||
.enable = alpha_pll_fabia_enable,
|
||||
.disable = alpha_pll_fabia_disable,
|
||||
.is_enabled = clk_alpha_pll_is_enabled,
|
||||
.set_rate = alpha_pll_fabia_set_rate,
|
||||
.recalc_rate = alpha_pll_fabia_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
|
||||
.enable = alpha_pll_fabia_enable,
|
||||
.disable = alpha_pll_fabia_disable,
|
||||
.is_enabled = clk_alpha_pll_is_enabled,
|
||||
.recalc_rate = alpha_pll_fabia_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
|
||||
|
||||
static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
|
||||
u32 i, div = 1, val;
|
||||
int ret;
|
||||
|
||||
if (!pll->post_div_table) {
|
||||
pr_err("Missing the post_div_table for the PLL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val >>= pll->post_div_shift;
|
||||
val &= BIT(pll->width) - 1;
|
||||
|
||||
for (i = 0; i < pll->num_post_div; i++) {
|
||||
if (pll->post_div_table[i].val == val) {
|
||||
div = pll->post_div_table[i].div;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (parent_rate / div);
|
||||
}
|
||||
|
||||
static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
|
||||
unsigned long rate, unsigned long *prate)
|
||||
{
|
||||
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
|
||||
|
||||
if (!pll->post_div_table) {
|
||||
pr_err("Missing the post_div_table for the PLL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return divider_round_rate(hw, rate, prate, pll->post_div_table,
|
||||
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
|
||||
}
|
||||
|
||||
static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
|
||||
unsigned long rate, unsigned long parent_rate)
|
||||
{
|
||||
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
|
||||
int i, val = 0, div, ret;
|
||||
|
||||
/*
|
||||
* If the PLL is in FSM mode, then treat set_rate callback as a
|
||||
* no-operation.
|
||||
*/
|
||||
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (val & PLL_VOTE_FSM_ENA)
|
||||
return 0;
|
||||
|
||||
if (!pll->post_div_table) {
|
||||
pr_err("Missing the post_div_table for the PLL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
|
||||
for (i = 0; i < pll->num_post_div; i++) {
|
||||
if (pll->post_div_table[i].div == div) {
|
||||
val = pll->post_div_table[i].val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
|
||||
(BIT(pll->width) - 1) << pll->post_div_shift,
|
||||
val << pll->post_div_shift);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
|
||||
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
|
||||
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
@@ -22,6 +22,7 @@ enum {
|
||||
CLK_ALPHA_PLL_TYPE_DEFAULT,
|
||||
CLK_ALPHA_PLL_TYPE_HUAYRA,
|
||||
CLK_ALPHA_PLL_TYPE_BRAMMO,
|
||||
CLK_ALPHA_PLL_TYPE_FABIA,
|
||||
CLK_ALPHA_PLL_TYPE_MAX,
|
||||
};
|
||||
|
||||
@@ -36,6 +37,8 @@ enum {
|
||||
PLL_OFF_TEST_CTL,
|
||||
PLL_OFF_TEST_CTL_U,
|
||||
PLL_OFF_STATUS,
|
||||
PLL_OFF_OPMODE,
|
||||
PLL_OFF_FRAC,
|
||||
PLL_OFF_MAX_REGS
|
||||
};
|
||||
|
||||
@@ -73,6 +76,10 @@ struct clk_alpha_pll {
|
||||
* @offset: base address of registers
|
||||
* @regs: alpha pll register map (see @clk_alpha_pll_regs)
|
||||
* @width: width of post-divider
|
||||
* @post_div_shift: shift to differentiate between odd & even post-divider
|
||||
* @post_div_table: table with PLL odd and even post-divider settings
|
||||
* @num_post_div: Number of PLL post-divider settings
|
||||
*
|
||||
* @clkr: regmap clock handle
|
||||
*/
|
||||
struct clk_alpha_pll_postdiv {
|
||||
@@ -81,6 +88,9 @@ struct clk_alpha_pll_postdiv {
|
||||
const u8 *regs;
|
||||
|
||||
struct clk_regmap clkr;
|
||||
int post_div_shift;
|
||||
const struct clk_div_table *post_div_table;
|
||||
size_t num_post_div;
|
||||
};
|
||||
|
||||
struct alpha_pll_config {
|
||||
@@ -109,7 +119,13 @@ extern const struct clk_ops clk_alpha_pll_postdiv_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_huayra_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
|
||||
|
||||
extern const struct clk_ops clk_alpha_pll_fabia_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
|
||||
|
||||
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -77,8 +77,11 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling,
|
||||
bool voted = br->halt_check & BRANCH_VOTED;
|
||||
const char *name = clk_hw_get_name(&br->clkr.hw);
|
||||
|
||||
/* Skip checking halt bit if the clock is in hardware gated mode */
|
||||
if (clk_branch_in_hwcg_mode(br))
|
||||
/*
|
||||
* Skip checking halt bit if we're explicitly ignoring the bit or the
|
||||
* clock is in hardware gated mode
|
||||
*/
|
||||
if (br->halt_check == BRANCH_HALT_SKIP || clk_branch_in_hwcg_mode(br))
|
||||
return 0;
|
||||
|
||||
if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
|
||||
|
||||
@@ -42,6 +42,7 @@ struct clk_branch {
|
||||
#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
|
||||
#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED)
|
||||
#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */
|
||||
#define BRANCH_HALT_SKIP 3 /* Don't check halt bit */
|
||||
|
||||
struct clk_regmap clkr;
|
||||
};
|
||||
|
||||
@@ -1,15 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
|
||||
|
||||
#ifndef __QCOM_CLK_RCG_H__
|
||||
#define __QCOM_CLK_RCG_H__
|
||||
@@ -144,6 +134,7 @@ extern const struct clk_ops clk_dyn_rcg_ops;
|
||||
* @cmd_rcgr: corresponds to *_CMD_RCGR
|
||||
* @mnd_width: number of bits in m/n/d values
|
||||
* @hid_width: number of bits in half integer divider
|
||||
* @safe_src_index: safe src index value
|
||||
* @parent_map: map from software's parent index to hardware's src_sel field
|
||||
* @freq_tbl: frequency table
|
||||
* @clkr: regmap clock handle
|
||||
@@ -153,6 +144,7 @@ struct clk_rcg2 {
|
||||
u32 cmd_rcgr;
|
||||
u8 mnd_width;
|
||||
u8 hid_width;
|
||||
u8 safe_src_index;
|
||||
const struct parent_map *parent_map;
|
||||
const struct freq_tbl *freq_tbl;
|
||||
struct clk_regmap clkr;
|
||||
@@ -167,5 +159,6 @@ extern const struct clk_ops clk_byte_ops;
|
||||
extern const struct clk_ops clk_byte2_ops;
|
||||
extern const struct clk_ops clk_pixel_ops;
|
||||
extern const struct clk_ops clk_gfx3d_ops;
|
||||
extern const struct clk_ops clk_rcg2_shared_ops;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,14 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
@@ -42,6 +34,7 @@
|
||||
#define CFG_MODE_SHIFT 12
|
||||
#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
|
||||
#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
|
||||
#define CFG_HW_CLK_CTRL_MASK BIT(20)
|
||||
|
||||
#define M_REG 0x8
|
||||
#define N_REG 0xc
|
||||
@@ -249,7 +242,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
|
||||
return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
|
||||
}
|
||||
|
||||
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
||||
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
||||
{
|
||||
u32 cfg, mask;
|
||||
struct clk_hw *hw = &rcg->clkr.hw;
|
||||
@@ -277,13 +270,21 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
||||
}
|
||||
|
||||
mask = BIT(rcg->hid_width) - 1;
|
||||
mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
|
||||
mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
|
||||
cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
|
||||
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
|
||||
if (rcg->mnd_width && f->n && (f->m != f->n))
|
||||
cfg |= CFG_MODE_DUAL_EDGE;
|
||||
ret = regmap_update_bits(rcg->clkr.regmap,
|
||||
rcg->cmd_rcgr + CFG_REG, mask, cfg);
|
||||
|
||||
return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
||||
mask, cfg);
|
||||
}
|
||||
|
||||
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = __clk_rcg2_configure(rcg, f);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@@ -790,3 +791,141 @@ const struct clk_ops clk_gfx3d_ops = {
|
||||
.determine_rate = clk_gfx3d_determine_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
|
||||
|
||||
static int clk_rcg2_set_force_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
const char *name = clk_hw_get_name(hw);
|
||||
int ret, count;
|
||||
|
||||
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
|
||||
CMD_ROOT_EN, CMD_ROOT_EN);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* wait for RCG to turn ON */
|
||||
for (count = 500; count > 0; count--) {
|
||||
if (clk_rcg2_is_enabled(hw))
|
||||
return 0;
|
||||
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
pr_err("%s: RCG did not turn on\n", name);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int clk_rcg2_clear_force_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
|
||||
return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
|
||||
CMD_ROOT_EN, 0);
|
||||
}
|
||||
|
||||
static int
|
||||
clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
int ret;
|
||||
|
||||
ret = clk_rcg2_set_force_enable(hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_rcg2_configure(rcg, f);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return clk_rcg2_clear_force_enable(hw);
|
||||
}
|
||||
|
||||
static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
const struct freq_tbl *f;
|
||||
|
||||
f = qcom_find_freq(rcg->freq_tbl, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* In case clock is disabled, update the CFG, M, N and D registers
|
||||
* and don't hit the update bit of CMD register.
|
||||
*/
|
||||
if (!__clk_is_enabled(hw->clk))
|
||||
return __clk_rcg2_configure(rcg, f);
|
||||
|
||||
return clk_rcg2_shared_force_enable_clear(hw, f);
|
||||
}
|
||||
|
||||
static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw,
|
||||
unsigned long rate, unsigned long parent_rate, u8 index)
|
||||
{
|
||||
return clk_rcg2_shared_set_rate(hw, rate, parent_rate);
|
||||
}
|
||||
|
||||
static int clk_rcg2_shared_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Set the update bit because required configuration has already
|
||||
* been written in clk_rcg2_shared_set_rate()
|
||||
*/
|
||||
ret = clk_rcg2_set_force_enable(hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = update_config(rcg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return clk_rcg2_clear_force_enable(hw);
|
||||
}
|
||||
|
||||
static void clk_rcg2_shared_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
u32 cfg;
|
||||
|
||||
/*
|
||||
* Store current configuration as switching to safe source would clear
|
||||
* the SRC and DIV of CFG register
|
||||
*/
|
||||
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
|
||||
|
||||
/*
|
||||
* Park the RCG at a safe configuration - sourced off of safe source.
|
||||
* Force enable and disable the RCG while configuring it to safeguard
|
||||
* against any update signal coming from the downstream clock.
|
||||
* The current parent is still prepared and enabled at this point, and
|
||||
* the safe source is always on while application processor subsystem
|
||||
* is online. Therefore, the RCG can safely switch its parent.
|
||||
*/
|
||||
clk_rcg2_set_force_enable(hw);
|
||||
|
||||
regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
||||
rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
|
||||
|
||||
update_config(rcg);
|
||||
|
||||
clk_rcg2_clear_force_enable(hw);
|
||||
|
||||
/* Write back the stored configuration corresponding to current rate */
|
||||
regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_rcg2_shared_ops = {
|
||||
.enable = clk_rcg2_shared_enable,
|
||||
.disable = clk_rcg2_shared_disable,
|
||||
.get_parent = clk_rcg2_get_parent,
|
||||
.set_parent = clk_rcg2_set_parent,
|
||||
.recalc_rate = clk_rcg2_recalc_rate,
|
||||
.determine_rate = clk_rcg2_determine_rate,
|
||||
.set_rate = clk_rcg2_shared_set_rate,
|
||||
.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
|
||||
|
||||
3465
drivers/clk/qcom/gcc-sdm845.c
Normal file
3465
drivers/clk/qcom/gcc-sdm845.c
Normal file
File diff soppresso perché troppo grande
Carica Diff
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
@@ -31,6 +31,12 @@
|
||||
#define HW_CONTROL_MASK BIT(1)
|
||||
#define SW_COLLAPSE_MASK BIT(0)
|
||||
#define GMEM_CLAMP_IO_MASK BIT(0)
|
||||
#define GMEM_RESET_MASK BIT(4)
|
||||
|
||||
/* CFG_GDSCR */
|
||||
#define GDSC_POWER_UP_COMPLETE BIT(16)
|
||||
#define GDSC_POWER_DOWN_COMPLETE BIT(15)
|
||||
#define CFG_GDSCR_OFFSET 0x4
|
||||
|
||||
/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
|
||||
#define EN_REST_WAIT_VAL (0x2 << 20)
|
||||
@@ -40,20 +46,50 @@
|
||||
#define RETAIN_MEM BIT(14)
|
||||
#define RETAIN_PERIPH BIT(13)
|
||||
|
||||
#define TIMEOUT_US 100
|
||||
#define TIMEOUT_US 500
|
||||
|
||||
#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
|
||||
|
||||
static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
|
||||
enum gdsc_status {
|
||||
GDSC_OFF,
|
||||
GDSC_ON
|
||||
};
|
||||
|
||||
/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
|
||||
static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
|
||||
{
|
||||
unsigned int reg;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
if (sc->flags & POLL_CFG_GDSCR)
|
||||
reg = sc->gdscr + CFG_GDSCR_OFFSET;
|
||||
else if (sc->gds_hw_ctrl)
|
||||
reg = sc->gds_hw_ctrl;
|
||||
else
|
||||
reg = sc->gdscr;
|
||||
|
||||
ret = regmap_read(sc->regmap, reg, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return !!(val & PWR_ON_MASK);
|
||||
if (sc->flags & POLL_CFG_GDSCR) {
|
||||
switch (status) {
|
||||
case GDSC_ON:
|
||||
return !!(val & GDSC_POWER_UP_COMPLETE);
|
||||
case GDSC_OFF:
|
||||
return !!(val & GDSC_POWER_DOWN_COMPLETE);
|
||||
}
|
||||
}
|
||||
|
||||
switch (status) {
|
||||
case GDSC_ON:
|
||||
return !!(val & PWR_ON_MASK);
|
||||
case GDSC_OFF:
|
||||
return !(val & PWR_ON_MASK);
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int gdsc_hwctrl(struct gdsc *sc, bool en)
|
||||
@@ -63,34 +99,33 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
|
||||
return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
|
||||
}
|
||||
|
||||
static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
|
||||
static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
|
||||
{
|
||||
ktime_t start;
|
||||
|
||||
start = ktime_get();
|
||||
do {
|
||||
if (gdsc_is_enabled(sc, reg) == en)
|
||||
if (gdsc_check_status(sc, status))
|
||||
return 0;
|
||||
} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
|
||||
|
||||
if (gdsc_is_enabled(sc, reg) == en)
|
||||
if (gdsc_check_status(sc, status))
|
||||
return 0;
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int gdsc_toggle_logic(struct gdsc *sc, bool en)
|
||||
static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
|
||||
{
|
||||
int ret;
|
||||
u32 val = en ? 0 : SW_COLLAPSE_MASK;
|
||||
unsigned int status_reg = sc->gdscr;
|
||||
u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
|
||||
|
||||
ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* If disabling votable gdscs, don't poll on status */
|
||||
if ((sc->flags & VOTABLE) && !en) {
|
||||
if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
|
||||
/*
|
||||
* Add a short delay here to ensure that an enable
|
||||
* right after it was disabled does not put it in an
|
||||
@@ -101,7 +136,6 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
|
||||
}
|
||||
|
||||
if (sc->gds_hw_ctrl) {
|
||||
status_reg = sc->gds_hw_ctrl;
|
||||
/*
|
||||
* The gds hw controller asserts/de-asserts the status bit soon
|
||||
* after it receives a power on/off request from a master.
|
||||
@@ -115,7 +149,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
return gdsc_poll_status(sc, status_reg, en);
|
||||
return gdsc_poll_status(sc, status);
|
||||
}
|
||||
|
||||
static inline int gdsc_deassert_reset(struct gdsc *sc)
|
||||
@@ -166,6 +200,14 @@ static inline void gdsc_assert_clamp_io(struct gdsc *sc)
|
||||
GMEM_CLAMP_IO_MASK, 1);
|
||||
}
|
||||
|
||||
static inline void gdsc_assert_reset_aon(struct gdsc *sc)
|
||||
{
|
||||
regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
|
||||
GMEM_RESET_MASK, 1);
|
||||
udelay(1);
|
||||
regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
|
||||
GMEM_RESET_MASK, 0);
|
||||
}
|
||||
static int gdsc_enable(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct gdsc *sc = domain_to_gdsc(domain);
|
||||
@@ -174,10 +216,19 @@ static int gdsc_enable(struct generic_pm_domain *domain)
|
||||
if (sc->pwrsts == PWRSTS_ON)
|
||||
return gdsc_deassert_reset(sc);
|
||||
|
||||
if (sc->flags & CLAMP_IO)
|
||||
gdsc_deassert_clamp_io(sc);
|
||||
if (sc->flags & SW_RESET) {
|
||||
gdsc_assert_reset(sc);
|
||||
udelay(1);
|
||||
gdsc_deassert_reset(sc);
|
||||
}
|
||||
|
||||
ret = gdsc_toggle_logic(sc, true);
|
||||
if (sc->flags & CLAMP_IO) {
|
||||
if (sc->flags & AON_RESET)
|
||||
gdsc_assert_reset_aon(sc);
|
||||
gdsc_deassert_clamp_io(sc);
|
||||
}
|
||||
|
||||
ret = gdsc_toggle_logic(sc, GDSC_ON);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@@ -222,8 +273,6 @@ static int gdsc_disable(struct generic_pm_domain *domain)
|
||||
|
||||
/* Turn off HW trigger mode if supported */
|
||||
if (sc->flags & HW_CTRL) {
|
||||
unsigned int reg;
|
||||
|
||||
ret = gdsc_hwctrl(sc, false);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
@@ -235,8 +284,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)
|
||||
*/
|
||||
udelay(1);
|
||||
|
||||
reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
|
||||
ret = gdsc_poll_status(sc, reg, true);
|
||||
ret = gdsc_poll_status(sc, GDSC_ON);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
@@ -244,7 +292,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)
|
||||
if (sc->pwrsts & PWRSTS_OFF)
|
||||
gdsc_clear_mem_on(sc);
|
||||
|
||||
ret = gdsc_toggle_logic(sc, false);
|
||||
ret = gdsc_toggle_logic(sc, GDSC_OFF);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@@ -258,7 +306,6 @@ static int gdsc_init(struct gdsc *sc)
|
||||
{
|
||||
u32 mask, val;
|
||||
int on, ret;
|
||||
unsigned int reg;
|
||||
|
||||
/*
|
||||
* Disable HW trigger: collapse/restore occur based on registers writes.
|
||||
@@ -274,13 +321,12 @@ static int gdsc_init(struct gdsc *sc)
|
||||
|
||||
/* Force gdsc ON if only ON state is supported */
|
||||
if (sc->pwrsts == PWRSTS_ON) {
|
||||
ret = gdsc_toggle_logic(sc, true);
|
||||
ret = gdsc_toggle_logic(sc, GDSC_ON);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
|
||||
on = gdsc_is_enabled(sc, reg);
|
||||
on = gdsc_check_status(sc, GDSC_ON);
|
||||
if (on < 0)
|
||||
return on;
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
@@ -53,7 +53,10 @@ struct gdsc {
|
||||
#define VOTABLE BIT(0)
|
||||
#define CLAMP_IO BIT(1)
|
||||
#define HW_CTRL BIT(2)
|
||||
#define ALWAYS_ON BIT(3)
|
||||
#define SW_RESET BIT(3)
|
||||
#define AON_RESET BIT(4)
|
||||
#define POLL_CFG_GDSCR BIT(5)
|
||||
#define ALWAYS_ON BIT(6)
|
||||
struct reset_controller_dev *rcdev;
|
||||
unsigned int *resets;
|
||||
unsigned int reset_count;
|
||||
|
||||
358
drivers/clk/qcom/videocc-sdm845.c
Normal file
358
drivers/clk/qcom/videocc-sdm845.c
Normal file
@@ -0,0 +1,358 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-pll.h"
|
||||
#include "gdsc.h"
|
||||
|
||||
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_CORE_BI_PLL_TEST_SE,
|
||||
P_VIDEO_PLL0_OUT_EVEN,
|
||||
P_VIDEO_PLL0_OUT_MAIN,
|
||||
P_VIDEO_PLL0_OUT_ODD,
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
|
||||
{ P_VIDEO_PLL0_OUT_EVEN, 2 },
|
||||
{ P_VIDEO_PLL0_OUT_ODD, 3 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 4 },
|
||||
};
|
||||
|
||||
static const char * const video_cc_parent_names_0[] = {
|
||||
"bi_tcxo",
|
||||
"video_pll0",
|
||||
"video_pll0_out_even",
|
||||
"video_pll0_out_odd",
|
||||
"core_bi_pll_test_se",
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_pll0_config = {
|
||||
.l = 0x10,
|
||||
.alpha = 0xaaab,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll video_pll0 = {
|
||||
.offset = 0x42c,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_pll0",
|
||||
.parent_names = (const char *[]){ "bi_tcxo" },
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_fabia_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
|
||||
F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
|
||||
F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
|
||||
F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_venus_clk_src = {
|
||||
.cmd_rcgr = 0x7f0,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_video_cc_venus_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_venus_clk_src",
|
||||
.parent_names = video_cc_parent_names_0,
|
||||
.num_parents = 5,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_apb_clk = {
|
||||
.halt_reg = 0x990,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x990,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_apb_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_at_clk = {
|
||||
.halt_reg = 0x9f0,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9f0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_at_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_qdss_trig_clk = {
|
||||
.halt_reg = 0x970,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x970,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_qdss_trig_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_qdss_tsctr_div8_clk = {
|
||||
.halt_reg = 0x9d0,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9d0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_qdss_tsctr_div8_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_vcodec0_axi_clk = {
|
||||
.halt_reg = 0x930,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x930,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_vcodec0_axi_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_vcodec0_core_clk = {
|
||||
.halt_reg = 0x890,
|
||||
.halt_check = BRANCH_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x890,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_vcodec0_core_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"video_cc_venus_clk_src",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_vcodec1_axi_clk = {
|
||||
.halt_reg = 0x950,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x950,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_vcodec1_axi_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_vcodec1_core_clk = {
|
||||
.halt_reg = 0x8d0,
|
||||
.halt_check = BRANCH_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8d0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_vcodec1_core_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"video_cc_venus_clk_src",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_venus_ahb_clk = {
|
||||
.halt_reg = 0x9b0,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9b0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_venus_ahb_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_venus_ctl_axi_clk = {
|
||||
.halt_reg = 0x910,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x910,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_venus_ctl_axi_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_venus_ctl_core_clk = {
|
||||
.halt_reg = 0x850,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x850,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_venus_ctl_core_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"video_cc_venus_clk_src",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc venus_gdsc = {
|
||||
.gdscr = 0x814,
|
||||
.pd = {
|
||||
.name = "venus_gdsc",
|
||||
},
|
||||
.cxcs = (unsigned int []){ 0x850, 0x910 },
|
||||
.cxc_count = 2,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct gdsc vcodec0_gdsc = {
|
||||
.gdscr = 0x874,
|
||||
.pd = {
|
||||
.name = "vcodec0_gdsc",
|
||||
},
|
||||
.cxcs = (unsigned int []){ 0x890, 0x930 },
|
||||
.cxc_count = 2,
|
||||
.flags = HW_CTRL | POLL_CFG_GDSCR,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct gdsc vcodec1_gdsc = {
|
||||
.gdscr = 0x8b4,
|
||||
.pd = {
|
||||
.name = "vcodec1_gdsc",
|
||||
},
|
||||
.cxcs = (unsigned int []){ 0x8d0, 0x950 },
|
||||
.cxc_count = 2,
|
||||
.flags = HW_CTRL | POLL_CFG_GDSCR,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct clk_regmap *video_cc_sdm845_clocks[] = {
|
||||
[VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
|
||||
[VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,
|
||||
[VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,
|
||||
[VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,
|
||||
[VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
|
||||
[VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
|
||||
[VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr,
|
||||
[VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr,
|
||||
[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
|
||||
[VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
|
||||
[VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
|
||||
[VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
|
||||
[VIDEO_PLL0] = &video_pll0.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *video_cc_sdm845_gdscs[] = {
|
||||
[VENUS_GDSC] = &venus_gdsc,
|
||||
[VCODEC0_GDSC] = &vcodec0_gdsc,
|
||||
[VCODEC1_GDSC] = &vcodec1_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config video_cc_sdm845_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0xb90,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc video_cc_sdm845_desc = {
|
||||
.config = &video_cc_sdm845_regmap_config,
|
||||
.clks = video_cc_sdm845_clocks,
|
||||
.num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
|
||||
.gdscs = video_cc_sdm845_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id video_cc_sdm845_match_table[] = {
|
||||
{ .compatible = "qcom,sdm845-videocc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table);
|
||||
|
||||
static int video_cc_sdm845_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver video_cc_sdm845_driver = {
|
||||
.probe = video_cc_sdm845_probe,
|
||||
.driver = {
|
||||
.name = "sdm845-videocc",
|
||||
.of_match_table = video_cc_sdm845_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init video_cc_sdm845_init(void)
|
||||
{
|
||||
return platform_driver_register(&video_cc_sdm845_driver);
|
||||
}
|
||||
subsys_initcall(video_cc_sdm845_init);
|
||||
|
||||
static void __exit video_cc_sdm845_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&video_cc_sdm845_driver);
|
||||
}
|
||||
module_exit(video_cc_sdm845_exit);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Fai riferimento in un nuovo problema
Block a user