Merge branch 'tegra/dma-reset-rework' into next/dt
Bringing in the tegra dma/reset framework cleanup as a base for the DT changes. * tegra/dma-reset-rework: (320 commits) spi: tegra: checking for ERR_PTR instead of NULL ASoC: tegra: update module reset list for Tegra124 clk: tegra: remove bogus PCIE_XCLK clk: tegra: remove legacy reset APIs ARM: tegra: remove legacy DMA entries from DT ARM: tegra: remove legacy clock entries from DT USB: EHCI: tegra: use reset framework Input: tegra-kbc - use reset framework serial: tegra: convert to standard DMA DT bindings serial: tegra: use reset framework spi: tegra: convert to standard DMA DT bindings spi: tegra: use reset framework staging: nvec: use reset framework i2c: tegra: use reset framework ASoC: tegra: convert to standard DMA DT bindings ASoC: tegra: allocate AHUB FIFO during probe() not startup() ASoC: tegra: call pm_runtime APIs around register accesses ASoC: tegra: use reset framework dma: tegra: register as an OF DMA controller dma: tegra: use reset framework ... Signed-off-by: Olof Johansson <olof@lixom.net>
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@@ -8,6 +8,8 @@ Required properties:
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- compatible : should be "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 4 interrupts; one per timer channel.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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Example:
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@@ -18,4 +20,5 @@ timer {
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0 1 0x04
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0 41 0x04
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0 42 0x04>;
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clocks = <&tegra_car 132>;
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};
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@@ -10,6 +10,8 @@ Required properties:
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 6 interrupts; one per each of timer channels 1
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through 5, and one for the shared interrupt for the remaining channels.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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timer {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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@@ -20,4 +22,5 @@ timer {
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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clocks = <&tegra_car 214>;
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};
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