drm/i915: add power monitoring support
Add power monitoring support to the i915 driver for use by the IPS driver. Export the available power info to the IPS driver through a few new inter-driver hooks. When used together, the IPS driver and this patch can significantly increase graphics performance on Ironlake class chips. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: Fixed 32-bit compile. stupid obfuscating div_u64()] Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Jesse Barnes
@@ -4459,6 +4459,8 @@ static void intel_idle_update(struct work_struct *work)
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mutex_lock(&dev->struct_mutex);
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i915_update_gfx_val(dev_priv);
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if (IS_I945G(dev) || IS_I945GM(dev)) {
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DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
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I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
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@@ -5045,10 +5047,32 @@ err_unref:
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return NULL;
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}
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bool ironlake_set_drps(struct drm_device *dev, u8 val)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u16 rgvswctl;
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rgvswctl = I915_READ16(MEMSWCTL);
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if (rgvswctl & MEMCTL_CMD_STS) {
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DRM_DEBUG("gpu busy, RCS change rejected\n");
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return false; /* still busy with another command */
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}
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rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
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(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
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I915_WRITE16(MEMSWCTL, rgvswctl);
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POSTING_READ16(MEMSWCTL);
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rgvswctl |= MEMCTL_CMD_STS;
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I915_WRITE16(MEMSWCTL, rgvswctl);
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return true;
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}
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void ironlake_enable_drps(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
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u32 rgvmodectl = I915_READ(MEMMODECTL);
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u8 fmax, fmin, fstart, vstart;
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int i = 0;
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@@ -5067,13 +5091,21 @@ void ironlake_enable_drps(struct drm_device *dev)
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fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
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fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
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MEMMODE_FSTART_SHIFT;
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fstart = fmax;
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vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
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PXVFREQ_PX_SHIFT;
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dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
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dev_priv->fmax = fstart; /* IPS callback will increase this */
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dev_priv->fstart = fstart;
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dev_priv->max_delay = fmax;
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dev_priv->min_delay = fmin;
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dev_priv->cur_delay = fstart;
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DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
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fstart);
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I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
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/*
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@@ -5095,20 +5127,19 @@ void ironlake_enable_drps(struct drm_device *dev)
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}
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msleep(1);
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rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
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(fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
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I915_WRITE(MEMSWCTL, rgvswctl);
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POSTING_READ(MEMSWCTL);
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ironlake_set_drps(dev, fstart);
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rgvswctl |= MEMCTL_CMD_STS;
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I915_WRITE(MEMSWCTL, rgvswctl);
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dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
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I915_READ(0x112e0);
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dev_priv->last_time1 = jiffies_to_msecs(jiffies);
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dev_priv->last_count2 = I915_READ(0x112f4);
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getrawmonotonic(&dev_priv->last_time2);
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}
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void ironlake_disable_drps(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 rgvswctl;
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u8 fstart;
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u16 rgvswctl = I915_READ16(MEMSWCTL);
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/* Ack interrupts, disable EFC interrupt */
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I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
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@@ -5118,11 +5149,7 @@ void ironlake_disable_drps(struct drm_device *dev)
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I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
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/* Go back to the starting frequency */
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fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
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MEMMODE_FSTART_SHIFT;
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rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
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(fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
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I915_WRITE(MEMSWCTL, rgvswctl);
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ironlake_set_drps(dev, dev_priv->fstart);
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msleep(1);
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rgvswctl |= MEMCTL_CMD_STS;
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I915_WRITE(MEMSWCTL, rgvswctl);
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@@ -5130,6 +5157,92 @@ void ironlake_disable_drps(struct drm_device *dev)
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}
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static unsigned long intel_pxfreq(u32 vidfreq)
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{
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unsigned long freq;
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int div = (vidfreq & 0x3f0000) >> 16;
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int post = (vidfreq & 0x3000) >> 12;
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int pre = (vidfreq & 0x7);
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if (!pre)
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return 0;
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freq = ((div * 133333) / ((1<<post) * pre));
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return freq;
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}
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void intel_init_emon(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 lcfuse;
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u8 pxw[16];
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int i;
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/* Disable to program */
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I915_WRITE(ECR, 0);
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POSTING_READ(ECR);
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/* Program energy weights for various events */
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I915_WRITE(SDEW, 0x15040d00);
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I915_WRITE(CSIEW0, 0x007f0000);
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I915_WRITE(CSIEW1, 0x1e220004);
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I915_WRITE(CSIEW2, 0x04000004);
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for (i = 0; i < 5; i++)
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I915_WRITE(PEW + (i * 4), 0);
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for (i = 0; i < 3; i++)
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I915_WRITE(DEW + (i * 4), 0);
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/* Program P-state weights to account for frequency power adjustment */
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for (i = 0; i < 16; i++) {
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u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
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unsigned long freq = intel_pxfreq(pxvidfreq);
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unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
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PXVFREQ_PX_SHIFT;
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unsigned long val;
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val = vid * vid;
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val *= (freq / 1000);
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val *= 255;
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val /= (127*127*900);
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if (val > 0xff)
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DRM_ERROR("bad pxval: %ld\n", val);
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pxw[i] = val;
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}
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/* Render standby states get 0 weight */
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pxw[14] = 0;
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pxw[15] = 0;
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for (i = 0; i < 4; i++) {
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u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
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(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
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I915_WRITE(PXW + (i * 4), val);
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}
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/* Adjust magic regs to magic values (more experimental results) */
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I915_WRITE(OGW0, 0);
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I915_WRITE(OGW1, 0);
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I915_WRITE(EG0, 0x00007f00);
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I915_WRITE(EG1, 0x0000000e);
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I915_WRITE(EG2, 0x000e0000);
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I915_WRITE(EG3, 0x68000300);
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I915_WRITE(EG4, 0x42000000);
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I915_WRITE(EG5, 0x00140031);
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I915_WRITE(EG6, 0);
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I915_WRITE(EG7, 0);
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for (i = 0; i < 8; i++)
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I915_WRITE(PXWL + (i * 4), 0);
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/* Enable PMON + select events */
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I915_WRITE(ECR, 0x80000019);
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lcfuse = I915_READ(LCFUSE02);
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dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
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}
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void intel_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@@ -5376,8 +5489,10 @@ void intel_modeset_init(struct drm_device *dev)
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intel_init_clock_gating(dev);
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if (IS_IRONLAKE_M(dev))
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if (IS_IRONLAKE_M(dev)) {
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ironlake_enable_drps(dev);
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intel_init_emon(dev);
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}
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INIT_WORK(&dev_priv->idle_work, intel_idle_update);
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setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
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