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Merge branch 'ingenic-tcu-v5.4' into mips-next

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Merge the Ingenic TCU patchset from the ingenic-tcu-v5.4 branch which
was created to enable follow-on changes in other subsystems.

Signed-off-by: Paul Burton <paul.burton@mips.com>
This commit is contained in:
Paul Burton
2019-08-08 15:33:16 -07:00
parent 6393e60644 abc552284f
commit 75b7329a4f
27 changed files with 1421 additions and 206 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/mips/boot/dts/ingenic/ci20.dts
View File

@@ -2,6 +2,7 @@
/dts-v1/;
#include "jz4780.dtsi"
#include <dt-bindings/clock/ingenic,tcu.h>
#include <dt-bindings/gpio/gpio.h>
/ {
@@ -238,3 +239,9 @@
bias-disable;
};
};
&tcu {
/* 3 MHz for the system timer and clocksource */
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
assigned-clock-rates = <3000000>, <3000000>;
};

10
arch/mips/boot/dts/ingenic/gcw0.dts
View File

@@ -2,6 +2,7 @@
/dts-v1/;
#include "jz4770.dtsi"
#include <dt-bindings/clock/ingenic,tcu.h>
/ {
compatible = "gcw,zero", "ingenic,jz4770";
@@ -60,3 +61,12 @@
/* The WiFi module is connected to the UHC. */
status = "okay";
};
&tcu {
/* 750 kHz for the system timer and clocksource */
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
assigned-clock-rates = <750000>, <750000>;
/* PWM1 is in use, so reserve channel #2 for the clocksource */
ingenic,pwm-channels-mask = <0xfa>;
};

22
arch/mips/boot/dts/ingenic/jz4740.dtsi
View File

@@ -53,6 +53,28 @@
clock-names = "rtc";
};
tcu: timer@10002000 {
compatible = "ingenic,jz4740-tcu", "simple-mfd";
reg = <0x10002000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10002000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu JZ4740_CLK_RTC
&cgu JZ4740_CLK_EXT
&cgu JZ4740_CLK_PCLK
&cgu JZ4740_CLK_TCU>;
clock-names = "rtc", "ext", "pclk", "tcu";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <23 22 21>;
};
rtc_dev: rtc@10003000 {
compatible = "ingenic,jz4740-rtc";
reg = <0x10003000 0x40>;

21
arch/mips/boot/dts/ingenic/jz4770.dtsi
View File

@@ -46,6 +46,27 @@
#clock-cells = <1>;
};
tcu: timer@10002000 {
compatible = "ingenic,jz4770-tcu", "simple-mfd";
reg = <0x10002000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10002000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu JZ4770_CLK_RTC
&cgu JZ4770_CLK_EXT
&cgu JZ4770_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <27 26 25>;
};
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4770-pinctrl";
reg = <0x10010000 0x600>;

23
arch/mips/boot/dts/ingenic/jz4780.dtsi
View File

@@ -46,6 +46,29 @@
#clock-cells = <1>;
};
tcu: timer@10002000 {
compatible = "ingenic,jz4780-tcu",
"ingenic,jz4770-tcu",
"simple-mfd";
reg = <0x10002000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10002000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu JZ4780_CLK_RTCLK
&cgu JZ4780_CLK_EXCLK
&cgu JZ4780_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <27 26 25>;
};
rtc_dev: rtc@10003000 {
compatible = "ingenic,jz4780-rtc";
reg = <0x10003000 0x4c>;

8
arch/mips/boot/dts/ingenic/qi_lb60.dts
View File

@@ -2,10 +2,10 @@
/dts-v1/;
#include "jz4740.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/adc/ingenic,adc.h>
#include <dt-bindings/clock/ingenic,tcu.h>
#include <dt-bindings/input/input.h>
#define KEY_QI_QI KEY_F13
@@ -350,3 +350,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pins_mmc>;
};
&tcu {
/* 750 kHz for the system timer and clocksource */
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
assigned-clock-rates = <750000>, <750000>;
};

151
arch/mips/jz4740/time.c
View File

@@ -4,161 +4,14 @@
* JZ4740 platform time support
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/time.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/sched_clock.h>
#include <asm/mach-jz4740/irq.h>
#include <asm/mach-jz4740/timer.h>
#include <asm/time.h>
#define TIMER_CLOCKEVENT 0
#define TIMER_CLOCKSOURCE 1
static uint16_t jz4740_jiffies_per_tick;
static u64 jz4740_clocksource_read(struct clocksource *cs)
{
return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
}
static struct clocksource jz4740_clocksource = {
.name = "jz4740-timer",
.rating = 200,
.read = jz4740_clocksource_read,
.mask = CLOCKSOURCE_MASK(16),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static u64 notrace jz4740_read_sched_clock(void)
{
return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
}
static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
{
struct clock_event_device *cd = devid;
jz4740_timer_ack_full(TIMER_CLOCKEVENT);
if (!clockevent_state_periodic(cd))
jz4740_timer_disable(TIMER_CLOCKEVENT);
cd->event_handler(cd);
return IRQ_HANDLED;
}
static int jz4740_clockevent_set_periodic(struct clock_event_device *evt)
{
jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
jz4740_timer_enable(TIMER_CLOCKEVENT);
return 0;
}
static int jz4740_clockevent_resume(struct clock_event_device *evt)
{
jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
jz4740_timer_enable(TIMER_CLOCKEVENT);
return 0;
}
static int jz4740_clockevent_shutdown(struct clock_event_device *evt)
{
jz4740_timer_disable(TIMER_CLOCKEVENT);
return 0;
}
static int jz4740_clockevent_set_next(unsigned long evt,
struct clock_event_device *cd)
{
jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
jz4740_timer_enable(TIMER_CLOCKEVENT);
return 0;
}
static struct clock_event_device jz4740_clockevent = {
.name = "jz4740-timer",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = jz4740_clockevent_set_next,
.set_state_shutdown = jz4740_clockevent_shutdown,
.set_state_periodic = jz4740_clockevent_set_periodic,
.set_state_oneshot = jz4740_clockevent_shutdown,
.tick_resume = jz4740_clockevent_resume,
.rating = 200,
#ifdef CONFIG_MACH_JZ4740
.irq = JZ4740_IRQ_TCU0,
#endif
#if defined(CONFIG_MACH_JZ4770) || defined(CONFIG_MACH_JZ4780)
.irq = JZ4780_IRQ_TCU2,
#endif
};
static struct irqaction timer_irqaction = {
.handler = jz4740_clockevent_irq,
.flags = IRQF_PERCPU | IRQF_TIMER,
.name = "jz4740-timerirq",
.dev_id = &jz4740_clockevent,
};
void __init plat_time_init(void)
{
int ret;
uint32_t clk_rate;
uint16_t ctrl;
struct clk *ext_clk;
of_clk_init(NULL);
jz4740_timer_init();
ext_clk = clk_get(NULL, "ext");
if (IS_ERR(ext_clk))
panic("unable to get ext clock");
clk_rate = clk_get_rate(ext_clk) >> 4;
clk_put(ext_clk);
jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
clockevent_set_clock(&jz4740_clockevent, clk_rate);
jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
jz4740_clockevent.min_delta_ticks = 100;
jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
jz4740_clockevent.max_delta_ticks = 0xffff;
jz4740_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&jz4740_clockevent);
ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
if (ret)
printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
sched_clock_register(jz4740_read_sched_clock, 16, clk_rate);
setup_irq(jz4740_clockevent.irq, &timer_irqaction);
ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
jz4740_timer_enable(TIMER_CLOCKEVENT);
jz4740_timer_enable(TIMER_CLOCKSOURCE);
timer_probe();
}