MIPS: Add support for FTLBs
The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6139/
这个提交包含在：
Leonid Yegoshin
@@ -163,6 +163,25 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
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static char unknown_isa[] = KERN_ERR \
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"Unsupported ISA type, c0.config0: %d.";
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static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
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{
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unsigned int config6;
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/*
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* Config6 is implementation dependent and it's currently only
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* used by proAptiv
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*/
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if (c->cputype == CPU_PROAPTIV) {
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config6 = read_c0_config6();
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if (enable)
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/* Enable FTLB */
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write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
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else
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/* Disable FTLB */
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write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
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back_to_back_c0_hazard();
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}
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}
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static inline unsigned int decode_config0(struct cpuinfo_mips *c)
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{
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unsigned int config0;
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@@ -170,8 +189,13 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
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config0 = read_c0_config();
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if (((config0 & MIPS_CONF_MT) >> 7) == 1)
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/*
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* Look for Standard TLB or Dual VTLB and FTLB
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*/
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if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
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(((config0 & MIPS_CONF_MT) >> 7) == 4))
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c->options |= MIPS_CPU_TLB;
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isa = (config0 & MIPS_CONF_AT) >> 13;
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switch (isa) {
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case 0:
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@@ -226,8 +250,11 @@ static inline unsigned int decode_config1(struct cpuinfo_mips *c)
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c->options |= MIPS_CPU_FPU;
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c->options |= MIPS_CPU_32FPR;
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}
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if (cpu_has_tlb)
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if (cpu_has_tlb) {
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c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
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c->tlbsizevtlb = c->tlbsize;
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c->tlbsizeftlbsets = 0;
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}
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return config1 & MIPS_CONF_M;
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}
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@@ -281,16 +308,50 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
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static inline unsigned int decode_config4(struct cpuinfo_mips *c)
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{
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unsigned int config4;
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unsigned int newcf4;
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unsigned int mmuextdef;
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unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
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config4 = read_c0_config4();
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if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
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&& cpu_has_tlb)
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c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
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if (cpu_has_tlb) {
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if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
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c->options |= MIPS_CPU_TLBINV;
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mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
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switch (mmuextdef) {
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case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
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c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
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c->tlbsizevtlb = c->tlbsize;
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break;
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case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
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c->tlbsizevtlb +=
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((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
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MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
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c->tlbsize = c->tlbsizevtlb;
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ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
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/* fall through */
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case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
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newcf4 = (config4 & ~ftlb_page) |
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(page_size_ftlb(mmuextdef) <<
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MIPS_CONF4_FTLBPAGESIZE_SHIFT);
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write_c0_config4(newcf4);
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back_to_back_c0_hazard();
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config4 = read_c0_config4();
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if (config4 != newcf4) {
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pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
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PAGE_SIZE, config4);
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/* Switch FTLB off */
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set_ftlb_enable(c, 0);
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break;
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}
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c->tlbsizeftlbsets = 1 <<
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((config4 & MIPS_CONF4_FTLBSETS) >>
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MIPS_CONF4_FTLBSETS_SHIFT);
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c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
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MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
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c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
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break;
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}
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}
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c->kscratch_mask = (config4 >> 16) & 0xff;
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@@ -319,6 +380,9 @@ static void decode_configs(struct cpuinfo_mips *c)
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c->scache.flags = MIPS_CACHE_NOT_PRESENT;
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/* Enable FTLB if present */
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set_ftlb_enable(c, 1);
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ok = decode_config0(c); /* Read Config registers. */
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BUG_ON(!ok); /* Arch spec violation! */
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if (ok)
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@@ -682,7 +746,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
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{
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decode_configs(c);
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switch (c->processor_id & PRID_IMP_MASK) {
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case PRID_IMP_4KC:
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c->cputype = CPU_4KC;
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@@ -756,6 +819,8 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
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break;
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}
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decode_configs(c);
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spram_config();
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}
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@@ -476,6 +476,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
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BUILD_HANDLER ov ov sti silent /* #12 */
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BUILD_HANDLER tr tr sti silent /* #13 */
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BUILD_HANDLER fpe fpe fpe silent /* #15 */
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BUILD_HANDLER ftlb ftlb none silent /* #16 */
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BUILD_HANDLER mdmx mdmx sti silent /* #22 */
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#ifdef CONFIG_HARDWARE_WATCHPOINTS
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/*
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@@ -78,6 +78,7 @@ extern asmlinkage void handle_cpu(void);
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extern asmlinkage void handle_ov(void);
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extern asmlinkage void handle_tr(void);
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extern asmlinkage void handle_fpe(void);
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extern asmlinkage void handle_ftlb(void);
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extern asmlinkage void handle_mdmx(void);
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extern asmlinkage void handle_watch(void);
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extern asmlinkage void handle_mt(void);
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@@ -1460,6 +1461,34 @@ asmlinkage void cache_parity_error(void)
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panic("Can't handle the cache error!");
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}
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asmlinkage void do_ftlb(void)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned int reg_val;
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/* For the moment, report the problem and hang. */
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if (cpu_has_mips_r2 &&
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((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {
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pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
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read_c0_ecc());
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pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
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reg_val = read_c0_cacheerr();
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pr_err("c0_cacheerr == %08x\n", reg_val);
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if ((reg_val & 0xc0000000) == 0xc0000000) {
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pr_err("Decoded c0_cacheerr: FTLB parity error\n");
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} else {
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pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
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reg_val & (1<<30) ? "secondary" : "primary",
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reg_val & (1<<31) ? "data" : "insn");
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}
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} else {
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pr_err("FTLB error exception\n");
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}
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/* Just print the cacheerr bits for now */
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cache_parity_error();
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}
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/*
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* SDBBP EJTAG debug exception handler.
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* We skip the instruction and return to the next instruction.
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@@ -2009,6 +2038,7 @@ void __init trap_init(void)
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if (cpu_has_fpu && !cpu_has_nofpuex)
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set_except_vector(15, handle_fpe);
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set_except_vector(16, handle_ftlb);
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set_except_vector(22, handle_mdmx);
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if (cpu_has_mcheck)
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