octeontx2-af: Configure block LF's MSIX vector offset
Firmware configures a certain number of MSIX vectors to each of enabled RVU PF/VF. When a block LF is attached to a PF/VF, number of MSIX vectors needed by that LF are set aside (out of PF/VF's total MSIX vectors) and LF's msix_offset is configured in HW. Also added support for a RVU PF/VF to retrieve that block LF's MSIX vector offset information from AF via mbox. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sunil Goutham
committed by
David S. Miller
David S. Miller
parent
746ea74241
commit
756051e23c
@@ -122,6 +122,7 @@ static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
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M(READY, 0x001, msg_req, ready_msg_rsp) \
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M(ATTACH_RESOURCES, 0x002, rsrc_attach, msg_rsp) \
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M(DETACH_RESOURCES, 0x003, rsrc_detach, msg_rsp) \
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M(MSIX_OFFSET, 0x004, msg_req, msix_offset_rsp) \
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/* CGX mbox IDs (range 0x200 - 0x3FF) */ \
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/* NPA mbox IDs (range 0x400 - 0x5FF) */ \
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/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
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@@ -190,4 +191,21 @@ struct rsrc_detach {
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u8 cptlfs:1;
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};
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#define MSIX_VECTOR_INVALID 0xFFFF
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#define MAX_RVU_BLKLF_CNT 256
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struct msix_offset_rsp {
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struct mbox_msghdr hdr;
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u16 npa_msixoff;
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u16 nix_msixoff;
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u8 sso;
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u8 ssow;
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u8 timlfs;
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u8 cptlfs;
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u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
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u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
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u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
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u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
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};
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#endif /* MBOX_H */
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@@ -24,6 +24,11 @@
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static int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
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static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
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struct rvu_block *block, int lf);
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static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
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struct rvu_block *block, int lf);
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/* Supported devices */
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static const struct pci_device_id rvu_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) },
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@@ -74,6 +79,45 @@ int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
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return id;
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}
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static int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
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{
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int start;
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if (!rsrc->bmap)
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return -EINVAL;
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start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
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if (start >= rsrc->max)
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return -ENOSPC;
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bitmap_set(rsrc->bmap, start, nrsrc);
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return start;
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}
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static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)
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{
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if (!rsrc->bmap)
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return;
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if (start >= rsrc->max)
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return;
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bitmap_clear(rsrc->bmap, start, nrsrc);
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}
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static bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
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{
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int start;
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if (!rsrc->bmap)
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return false;
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start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
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if (start >= rsrc->max)
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return false;
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return true;
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}
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void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id)
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{
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if (!rsrc->bmap)
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@@ -102,6 +146,26 @@ int rvu_alloc_bitmap(struct rsrc_bmap *rsrc)
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return 0;
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}
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/* Get block LF's HW index from a PF_FUNC's block slot number */
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int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot)
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{
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u16 match = 0;
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int lf;
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spin_lock(&rvu->rsrc_lock);
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for (lf = 0; lf < block->lf.max; lf++) {
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if (block->fn_map[lf] == pcifunc) {
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if (slot == match) {
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spin_unlock(&rvu->rsrc_lock);
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return lf;
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}
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match++;
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}
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}
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spin_unlock(&rvu->rsrc_lock);
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return -ENODEV;
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}
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/* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E.
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* Some silicon variants of OcteonTX2 supports
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* multiple blocks of same type.
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@@ -236,6 +300,16 @@ inline int rvu_get_pf(u16 pcifunc)
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return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
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}
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void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf)
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{
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u64 cfg;
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/* Get numVFs attached to this PF and first HWVF */
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cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
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*numvfs = (cfg >> 12) & 0xFF;
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*hwvf = cfg & 0xFFF;
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}
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static int rvu_get_hwvf(struct rvu *rvu, int pcifunc)
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{
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int pf, func;
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@@ -330,20 +404,150 @@ static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block)
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pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF);
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rvu_update_rsrc_map(rvu, pfvf, block,
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(cfg >> 8) & 0xFFFF, lf, true);
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/* Set start MSIX vector for this LF within this PF/VF */
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rvu_set_msix_offset(rvu, pfvf, block, lf);
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}
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}
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static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf)
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{
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int min_vecs;
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if (!vf)
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goto check_pf;
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if (!nvecs) {
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dev_warn(rvu->dev,
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"PF%d:VF%d is configured with zero msix vectors, %d\n",
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pf, vf - 1, nvecs);
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}
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return;
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check_pf:
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if (pf == 0)
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min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT;
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else
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min_vecs = RVU_PF_INT_VEC_CNT;
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if (!(nvecs < min_vecs))
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return;
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dev_warn(rvu->dev,
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"PF%d is configured with too few vectors, %d, min is %d\n",
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pf, nvecs, min_vecs);
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}
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static int rvu_setup_msix_resources(struct rvu *rvu)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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int pf, vf, numvfs, hwvf, err;
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struct rvu_pfvf *pfvf;
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int nvecs, offset;
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u64 cfg;
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for (pf = 0; pf < hw->total_pfs; pf++) {
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cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
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/* If PF is not enabled, nothing to do */
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if (!((cfg >> 20) & 0x01))
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continue;
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rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
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pfvf = &rvu->pf[pf];
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/* Get num of MSIX vectors attached to this PF */
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cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf));
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pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1;
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rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0);
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/* Alloc msix bitmap for this PF */
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err = rvu_alloc_bitmap(&pfvf->msix);
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if (err)
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return err;
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/* Allocate memory for MSIX vector to RVU block LF mapping */
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pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max,
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sizeof(u16), GFP_KERNEL);
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if (!pfvf->msix_lfmap)
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return -ENOMEM;
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/* For PF0 (AF) firmware will set msix vector offsets for
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* AF, block AF and PF0_INT vectors, so jump to VFs.
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*/
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if (!pf)
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goto setup_vfmsix;
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/* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors.
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* These are allocated on driver init and never freed,
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* so no need to set 'msix_lfmap' for these.
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*/
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cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf));
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nvecs = (cfg >> 12) & 0xFF;
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cfg &= ~0x7FFULL;
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offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
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rvu_write64(rvu, BLKADDR_RVUM,
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RVU_PRIV_PFX_INT_CFG(pf), cfg | offset);
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setup_vfmsix:
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/* Alloc msix bitmap for VFs */
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for (vf = 0; vf < numvfs; vf++) {
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pfvf = &rvu->hwvf[hwvf + vf];
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/* Get num of MSIX vectors attached to this VF */
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cfg = rvu_read64(rvu, BLKADDR_RVUM,
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RVU_PRIV_PFX_MSIX_CFG(pf));
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pfvf->msix.max = (cfg & 0xFFF) + 1;
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rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1);
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/* Alloc msix bitmap for this VF */
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err = rvu_alloc_bitmap(&pfvf->msix);
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if (err)
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return err;
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pfvf->msix_lfmap =
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devm_kcalloc(rvu->dev, pfvf->msix.max,
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sizeof(u16), GFP_KERNEL);
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if (!pfvf->msix_lfmap)
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return -ENOMEM;
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/* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors.
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* These are allocated on driver init and never freed,
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* so no need to set 'msix_lfmap' for these.
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*/
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cfg = rvu_read64(rvu, BLKADDR_RVUM,
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RVU_PRIV_HWVFX_INT_CFG(hwvf + vf));
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nvecs = (cfg >> 12) & 0xFF;
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cfg &= ~0x7FFULL;
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offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
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rvu_write64(rvu, BLKADDR_RVUM,
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RVU_PRIV_HWVFX_INT_CFG(hwvf + vf),
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cfg | offset);
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}
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}
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return 0;
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}
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static void rvu_free_hw_resources(struct rvu *rvu)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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struct rvu_block *block;
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struct rvu_pfvf *pfvf;
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int id;
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/* Free all bitmaps */
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/* Free block LF bitmaps */
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for (id = 0; id < BLK_COUNT; id++) {
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block = &hw->block[id];
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kfree(block->lf.bmap);
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}
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/* Free MSIX bitmaps */
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for (id = 0; id < hw->total_pfs; id++) {
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pfvf = &rvu->pf[id];
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kfree(pfvf->msix.bmap);
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}
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for (id = 0; id < hw->total_vfs; id++) {
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pfvf = &rvu->hwvf[id];
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kfree(pfvf->msix.bmap);
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}
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}
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static int rvu_setup_hw_resources(struct rvu *rvu)
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@@ -499,6 +703,12 @@ init:
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if (!rvu->hwvf)
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return -ENOMEM;
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spin_lock_init(&rvu->rsrc_lock);
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err = rvu_setup_msix_resources(rvu);
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if (err)
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return err;
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for (blkid = 0; blkid < BLK_COUNT; blkid++) {
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block = &hw->block[blkid];
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if (!block->lf.bmap)
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@@ -516,8 +726,6 @@ init:
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rvu_scan_block(rvu, block);
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}
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spin_lock_init(&rvu->rsrc_lock);
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return 0;
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}
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@@ -603,6 +811,9 @@ static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype)
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/* Free the resource */
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rvu_free_rsrc(&block->lf, lf);
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/* Clear MSIX vector offset for this LF */
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rvu_clear_msix_offset(rvu, pfvf, block, lf);
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}
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}
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@@ -696,6 +907,9 @@ static void rvu_attach_block(struct rvu *rvu, int pcifunc,
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(lf << block->lfshift), cfg);
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rvu_update_rsrc_map(rvu, pfvf, block,
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pcifunc, lf, true);
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/* Set start MSIX vector for this LF within this PF/VF */
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rvu_set_msix_offset(rvu, pfvf, block, lf);
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}
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}
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@@ -871,6 +1085,119 @@ exit:
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return err;
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}
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static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
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int blkaddr, int lf)
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{
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u16 vec;
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if (lf < 0)
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return MSIX_VECTOR_INVALID;
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for (vec = 0; vec < pfvf->msix.max; vec++) {
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if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf))
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return vec;
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}
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return MSIX_VECTOR_INVALID;
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}
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static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
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struct rvu_block *block, int lf)
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{
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u16 nvecs, vec, offset;
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u64 cfg;
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cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
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(lf << block->lfshift));
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nvecs = (cfg >> 12) & 0xFF;
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/* Check and alloc MSIX vectors, must be contiguous */
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if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs))
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return;
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offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
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/* Config MSIX offset in LF */
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rvu_write64(rvu, block->addr, block->msixcfg_reg |
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(lf << block->lfshift), (cfg & ~0x7FFULL) | offset);
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/* Update the bitmap as well */
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for (vec = 0; vec < nvecs; vec++)
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pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf);
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}
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static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
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struct rvu_block *block, int lf)
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{
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u16 nvecs, vec, offset;
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u64 cfg;
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cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
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(lf << block->lfshift));
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nvecs = (cfg >> 12) & 0xFF;
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/* Clear MSIX offset in LF */
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rvu_write64(rvu, block->addr, block->msixcfg_reg |
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(lf << block->lfshift), cfg & ~0x7FFULL);
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offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf);
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/* Update the mapping */
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for (vec = 0; vec < nvecs; vec++)
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pfvf->msix_lfmap[offset + vec] = 0;
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/* Free the same in MSIX bitmap */
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rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset);
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}
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static int rvu_mbox_handler_MSIX_OFFSET(struct rvu *rvu, struct msg_req *req,
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struct msix_offset_rsp *rsp)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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u16 pcifunc = req->hdr.pcifunc;
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struct rvu_pfvf *pfvf;
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int lf, slot;
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pfvf = rvu_get_pfvf(rvu, pcifunc);
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if (!pfvf->msix.bmap)
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return 0;
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/* Set MSIX offsets for each block's LFs attached to this PF/VF */
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lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0);
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rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf);
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lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NIX0], pcifunc, 0);
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rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NIX0, lf);
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rsp->sso = pfvf->sso;
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for (slot = 0; slot < rsp->sso; slot++) {
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lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot);
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rsp->sso_msixoff[slot] =
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rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf);
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}
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rsp->ssow = pfvf->ssow;
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for (slot = 0; slot < rsp->ssow; slot++) {
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lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot);
|
||||
rsp->ssow_msixoff[slot] =
|
||||
rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf);
|
||||
}
|
||||
|
||||
rsp->timlfs = pfvf->timlfs;
|
||||
for (slot = 0; slot < rsp->timlfs; slot++) {
|
||||
lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot);
|
||||
rsp->timlf_msixoff[slot] =
|
||||
rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf);
|
||||
}
|
||||
|
||||
rsp->cptlfs = pfvf->cptlfs;
|
||||
for (slot = 0; slot < rsp->cptlfs; slot++) {
|
||||
lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot);
|
||||
rsp->cptlf_msixoff[slot] =
|
||||
rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rvu_process_mbox_msg(struct rvu *rvu, int devid,
|
||||
struct mbox_msghdr *req)
|
||||
{
|
||||
|
||||
@@ -65,6 +65,11 @@ struct rvu_pfvf {
|
||||
u16 ssow;
|
||||
u16 cptlfs;
|
||||
u16 timlfs;
|
||||
|
||||
/* Block LF's MSIX vector info */
|
||||
struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
|
||||
#define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
|
||||
u16 *msix_lfmap; /* Vector to block LF mapping */
|
||||
};
|
||||
|
||||
struct rvu_hwinfo {
|
||||
@@ -126,7 +131,9 @@ void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
|
||||
int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
|
||||
int rvu_get_pf(u16 pcifunc);
|
||||
struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
|
||||
void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
|
||||
bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
|
||||
int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
|
||||
int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
|
||||
int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
|
||||
|
||||
|
||||
@@ -54,6 +54,7 @@ enum rvu_af_int_vec_e {
|
||||
RVU_AF_INT_VEC_PFME = 0x2,
|
||||
RVU_AF_INT_VEC_GEN = 0x3,
|
||||
RVU_AF_INT_VEC_MBOX = 0x4,
|
||||
RVU_AF_INT_VEC_CNT = 0x5,
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -67,6 +68,7 @@ enum rvu_pf_int_vec_e {
|
||||
RVU_PF_INT_VEC_VFPF_MBOX0 = 0x4,
|
||||
RVU_PF_INT_VEC_VFPF_MBOX1 = 0x5,
|
||||
RVU_PF_INT_VEC_AFPF_MBOX = 0x6,
|
||||
RVU_PF_INT_VEC_CNT = 0x7,
|
||||
};
|
||||
|
||||
#endif /* RVU_STRUCT_H */
|
||||
|
||||
Reference in New Issue
Block a user