gpu: host1x: Add host1x driver
Add host1x, the driver for host1x and its client unit 2D. The Tegra host1x module is the DMA engine for register access to Tegra's graphics- and multimedia-related modules. The modules served by host1x are referred to as clients. host1x includes some other functionality, such as synchronization. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Erik Faye-Lund <kusmabite@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
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committed by
Thierry Reding

parent
e1adc78caf
commit
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96
drivers/gpu/host1x/dev.h
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96
drivers/gpu/host1x/dev.h
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/*
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* Copyright (c) 2012-2013, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HOST1X_DEV_H
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#define HOST1X_DEV_H
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include "syncpt.h"
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struct host1x_syncpt;
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struct host1x_syncpt_ops {
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void (*restore)(struct host1x_syncpt *syncpt);
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void (*restore_wait_base)(struct host1x_syncpt *syncpt);
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void (*load_wait_base)(struct host1x_syncpt *syncpt);
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u32 (*load)(struct host1x_syncpt *syncpt);
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void (*cpu_incr)(struct host1x_syncpt *syncpt);
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int (*patch_wait)(struct host1x_syncpt *syncpt, void *patch_addr);
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};
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struct host1x_info {
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int nb_channels; /* host1x: num channels supported */
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int nb_pts; /* host1x: num syncpoints supported */
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int nb_bases; /* host1x: num syncpoints supported */
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int nb_mlocks; /* host1x: number of mlocks */
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int (*init)(struct host1x *); /* initialize per SoC ops */
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int sync_offset;
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};
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struct host1x {
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const struct host1x_info *info;
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void __iomem *regs;
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struct host1x_syncpt *syncpt;
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struct device *dev;
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struct clk *clk;
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const struct host1x_syncpt_ops *syncpt_op;
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};
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void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v);
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u32 host1x_sync_readl(struct host1x *host1x, u32 r);
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static inline void host1x_hw_syncpt_restore(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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host->syncpt_op->restore(sp);
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}
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static inline void host1x_hw_syncpt_restore_wait_base(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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host->syncpt_op->restore_wait_base(sp);
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}
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static inline void host1x_hw_syncpt_load_wait_base(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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host->syncpt_op->load_wait_base(sp);
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}
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static inline u32 host1x_hw_syncpt_load(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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return host->syncpt_op->load(sp);
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}
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static inline void host1x_hw_syncpt_cpu_incr(struct host1x *host,
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struct host1x_syncpt *sp)
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{
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host->syncpt_op->cpu_incr(sp);
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}
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static inline int host1x_hw_syncpt_patch_wait(struct host1x *host,
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struct host1x_syncpt *sp,
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void *patch_addr)
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{
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return host->syncpt_op->patch_wait(sp, patch_addr);
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}
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#endif
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