Merge branch 'i2c-embedded/for-next' of git://git.pengutronix.de/git/wsa/linux
Pull i2c-embedded changes from Wolfram Sang: - CBUS driver (an I2C variant) - continued rework of the omap driver - s3c2410 gets lots of fixes and gains pinctrl support - at91 gains DMA support - the GPIO muxer gains devicetree probing - typical fixes and additions all over * 'i2c-embedded/for-next' of git://git.pengutronix.de/git/wsa/linux: (45 commits) i2c: omap: Remove the OMAP_I2C_FLAG_RESET_REGS_POSTIDLE flag i2c: at91: add dma support i2c: at91: change struct members indentation i2c: at91: fix compilation warning i2c: mxs: Do not disable the I2C SMBus quick mode i2c: mxs: Handle i2c DMA failure properly i2c: s3c2410: Remove recently introduced performance overheads i2c: ocores: Move grlib set/get functions into #ifdef CONFIG_OF block i2c: s3c2410: Add fix for i2c suspend/resume i2c: s3c2410: Fix code to free gpios i2c: i2c-cbus-gpio: introduce driver i2c: ocores: Add support for the GRLIB port of the controller and use function pointers for getreg and setreg functions i2c: ocores: Add irq support for sparc i2c: omap: Move the remove constraint ARM: dts: cfa10049: Add the i2c muxer buses to the CFA-10049 i2c: s3c2410: do not special case HDMIPHY stuck bus detection i2c: s3c2410: use exponential back off while polling for bus idle i2c: s3c2410: do not generate STOP for QUIRK_HDMIPHY i2c: s3c2410: grab adapter lock while changing i2c clock i2c: s3c2410: Add support for pinctrl ...
Este commit está contenido en:
Linus Torvalds
@@ -38,6 +38,7 @@
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#include <linux/io.h>
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#include <linux/of_i2c.h>
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#include <linux/of_gpio.h>
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#include <linux/pinctrl/consumer.h>
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#include <asm/irq.h>
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@@ -49,6 +50,9 @@
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#define QUIRK_HDMIPHY (1 << 1)
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#define QUIRK_NO_GPIO (1 << 2)
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/* Max time to wait for bus to become idle after a xfer (in us) */
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#define S3C2410_IDLE_TIMEOUT 5000
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/* i2c controller state */
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enum s3c24xx_i2c_state {
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STATE_IDLE,
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@@ -59,7 +63,6 @@ enum s3c24xx_i2c_state {
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};
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struct s3c24xx_i2c {
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spinlock_t lock;
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wait_queue_head_t wait;
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unsigned int quirks;
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unsigned int suspended:1;
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@@ -78,11 +81,11 @@ struct s3c24xx_i2c {
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void __iomem *regs;
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struct clk *clk;
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struct device *dev;
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struct resource *ioarea;
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struct i2c_adapter adap;
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struct s3c2410_platform_i2c *pdata;
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int gpios[2];
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struct pinctrl *pctrl;
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block freq_transition;
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#endif
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@@ -235,8 +238,47 @@ static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
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dev_dbg(i2c->dev, "STOP\n");
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/* stop the transfer */
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iicstat &= ~S3C2410_IICSTAT_START;
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/*
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* The datasheet says that the STOP sequence should be:
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* 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
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* 2) I2CCON.4 = 0 - Clear IRQPEND
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* 3) Wait until the stop condition takes effect.
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* 4*) I2CSTAT.4 = 0 - Clear TXRXEN
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*
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* Where, step "4*" is only for buses with the "HDMIPHY" quirk.
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*
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* However, after much experimentation, it appears that:
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* a) normal buses automatically clear BUSY and transition from
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* Master->Slave when they complete generating a STOP condition.
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* Therefore, step (3) can be done in doxfer() by polling I2CCON.4
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* after starting the STOP generation here.
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* b) HDMIPHY bus does neither, so there is no way to do step 3.
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* There is no indication when this bus has finished generating
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* STOP.
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*
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* In fact, we have found that as soon as the IRQPEND bit is cleared in
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* step 2, the HDMIPHY bus generates the STOP condition, and then
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* immediately starts transferring another data byte, even though the
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* bus is supposedly stopped. This is presumably because the bus is
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* still in "Master" mode, and its BUSY bit is still set.
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*
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* To avoid these extra post-STOP transactions on HDMI phy devices, we
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* just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
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* instead of first generating a proper STOP condition. This should
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* float SDA & SCK terminating the transfer. Subsequent transfers
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* start with a proper START condition, and proceed normally.
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*
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* The HDMIPHY bus is an internal bus that always has exactly two
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* devices, the host as Master and the HDMIPHY device as the slave.
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* Skipping the STOP condition has been tested on this bus and works.
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*/
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if (i2c->quirks & QUIRK_HDMIPHY) {
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/* Stop driving the I2C pins */
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iicstat &= ~S3C2410_IICSTAT_TXRXEN;
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} else {
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/* stop the transfer */
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iicstat &= ~S3C2410_IICSTAT_START;
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}
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writel(iicstat, i2c->regs + S3C2410_IICSTAT);
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i2c->state = STATE_STOP;
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@@ -490,13 +532,6 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
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unsigned long iicstat;
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int timeout = 400;
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/* the timeout for HDMIPHY is reduced to 10 ms because
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* the hangup is expected to happen, so waiting 400 ms
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* causes only unnecessary system hangup
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*/
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if (i2c->quirks & QUIRK_HDMIPHY)
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timeout = 10;
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while (timeout-- > 0) {
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iicstat = readl(i2c->regs + S3C2410_IICSTAT);
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@@ -506,16 +541,61 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
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msleep(1);
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}
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/* hang-up of bus dedicated for HDMIPHY occurred, resetting */
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if (i2c->quirks & QUIRK_HDMIPHY) {
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writel(0, i2c->regs + S3C2410_IICCON);
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writel(0, i2c->regs + S3C2410_IICSTAT);
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writel(0, i2c->regs + S3C2410_IICDS);
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return -ETIMEDOUT;
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}
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return 0;
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/* s3c24xx_i2c_wait_idle
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*
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* wait for the i2c bus to become idle.
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*/
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static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
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{
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unsigned long iicstat;
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ktime_t start, now;
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unsigned long delay;
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int spins;
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/* ensure the stop has been through the bus */
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dev_dbg(i2c->dev, "waiting for bus idle\n");
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start = now = ktime_get();
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/*
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* Most of the time, the bus is already idle within a few usec of the
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* end of a transaction. However, really slow i2c devices can stretch
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* the clock, delaying STOP generation.
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*
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* On slower SoCs this typically happens within a very small number of
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* instructions so busy wait briefly to avoid scheduling overhead.
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*/
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spins = 3;
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iicstat = readl(i2c->regs + S3C2410_IICSTAT);
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while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
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cpu_relax();
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iicstat = readl(i2c->regs + S3C2410_IICSTAT);
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}
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return -ETIMEDOUT;
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/*
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* If we do get an appreciable delay as a compromise between idle
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* detection latency for the normal, fast case, and system load in the
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* slow device case, use an exponential back off in the polling loop,
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* up to 1/10th of the total timeout, then continue to poll at a
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* constant rate up to the timeout.
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*/
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delay = 1;
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while ((iicstat & S3C2410_IICSTAT_START) &&
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ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
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usleep_range(delay, 2 * delay);
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if (delay < S3C2410_IDLE_TIMEOUT / 10)
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delay <<= 1;
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now = ktime_get();
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iicstat = readl(i2c->regs + S3C2410_IICSTAT);
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}
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if (iicstat & S3C2410_IICSTAT_START)
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dev_warn(i2c->dev, "timeout waiting for bus idle\n");
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}
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/* s3c24xx_i2c_doxfer
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@@ -526,8 +606,7 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
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static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
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struct i2c_msg *msgs, int num)
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{
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unsigned long iicstat, timeout;
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int spins = 20;
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unsigned long timeout;
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int ret;
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if (i2c->suspended)
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@@ -540,8 +619,6 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
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goto out;
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}
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spin_lock_irq(&i2c->lock);
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i2c->msg = msgs;
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i2c->msg_num = num;
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i2c->msg_ptr = 0;
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@@ -550,7 +627,6 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
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s3c24xx_i2c_enable_irq(i2c);
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s3c24xx_i2c_message_start(i2c, msgs);
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spin_unlock_irq(&i2c->lock);
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timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
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@@ -564,24 +640,11 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
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else if (ret != num)
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dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
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/* ensure the stop has been through the bus */
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/* For QUIRK_HDMIPHY, bus is already disabled */
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if (i2c->quirks & QUIRK_HDMIPHY)
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goto out;
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dev_dbg(i2c->dev, "waiting for bus idle\n");
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/* first, try busy waiting briefly */
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do {
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cpu_relax();
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iicstat = readl(i2c->regs + S3C2410_IICSTAT);
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} while ((iicstat & S3C2410_IICSTAT_START) && --spins);
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/* if that timed out sleep */
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if (!spins) {
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msleep(1);
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iicstat = readl(i2c->regs + S3C2410_IICSTAT);
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}
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if (iicstat & S3C2410_IICSTAT_START)
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dev_warn(i2c->dev, "timeout waiting for bus idle\n");
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s3c24xx_i2c_wait_idle(i2c);
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out:
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return ret;
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@@ -740,7 +803,6 @@ static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
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unsigned long val, void *data)
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{
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struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
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unsigned long flags;
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unsigned int got;
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int delta_f;
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int ret;
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@@ -754,9 +816,9 @@ static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
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if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
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(val == CPUFREQ_PRECHANGE && delta_f > 0)) {
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spin_lock_irqsave(&i2c->lock, flags);
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i2c_lock_adapter(&i2c->adap);
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ret = s3c24xx_i2c_clockrate(i2c, &got);
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spin_unlock_irqrestore(&i2c->lock, flags);
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i2c_unlock_adapter(&i2c->adap);
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if (ret < 0)
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dev_err(i2c->dev, "cannot find frequency\n");
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@@ -858,14 +920,6 @@ static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
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pdata = i2c->pdata;
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/* inititalise the gpio */
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if (pdata->cfg_gpio)
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pdata->cfg_gpio(to_platform_device(i2c->dev));
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else
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if (s3c24xx_i2c_parse_dt_gpio(i2c))
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return -EINVAL;
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/* write slave address */
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writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
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@@ -963,7 +1017,6 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
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i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
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i2c->tx_setup = 50;
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spin_lock_init(&i2c->lock);
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init_waitqueue_head(&i2c->wait);
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/* find the clock and enable it */
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@@ -989,36 +1042,38 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
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goto err_clk;
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}
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i2c->ioarea = request_mem_region(res->start, resource_size(res),
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pdev->name);
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if (i2c->ioarea == NULL) {
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dev_err(&pdev->dev, "cannot request IO\n");
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ret = -ENXIO;
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goto err_clk;
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}
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i2c->regs = ioremap(res->start, resource_size(res));
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i2c->regs = devm_request_and_ioremap(&pdev->dev, res);
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if (i2c->regs == NULL) {
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dev_err(&pdev->dev, "cannot map IO\n");
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ret = -ENXIO;
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goto err_ioarea;
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goto err_clk;
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}
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dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
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i2c->regs, i2c->ioarea, res);
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dev_dbg(&pdev->dev, "registers %p (%p)\n",
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i2c->regs, res);
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/* setup info block for the i2c core */
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i2c->adap.algo_data = i2c;
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i2c->adap.dev.parent = &pdev->dev;
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i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
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/* inititalise the i2c gpio lines */
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if (i2c->pdata->cfg_gpio) {
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i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
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} else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) {
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ret = -EINVAL;
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goto err_clk;
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}
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/* initialise the i2c controller */
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ret = s3c24xx_i2c_init(i2c);
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if (ret != 0)
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goto err_iomap;
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goto err_clk;
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/* find the IRQ for this unit (note, this relies on the init call to
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* ensure no current IRQs pending
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@@ -1027,7 +1082,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
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i2c->irq = ret = platform_get_irq(pdev, 0);
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if (ret <= 0) {
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dev_err(&pdev->dev, "cannot find IRQ\n");
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goto err_iomap;
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goto err_clk;
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}
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ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0,
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@@ -1035,7 +1090,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
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if (ret != 0) {
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dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
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goto err_iomap;
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goto err_clk;
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}
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ret = s3c24xx_i2c_register_cpufreq(i2c);
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@@ -1075,13 +1130,6 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
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err_irq:
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free_irq(i2c->irq, i2c);
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err_iomap:
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iounmap(i2c->regs);
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err_ioarea:
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release_resource(i2c->ioarea);
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kfree(i2c->ioarea);
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err_clk:
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clk_disable_unprepare(i2c->clk);
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clk_put(i2c->clk);
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@@ -1110,16 +1158,13 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev)
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clk_disable_unprepare(i2c->clk);
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clk_put(i2c->clk);
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iounmap(i2c->regs);
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release_resource(i2c->ioarea);
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s3c24xx_i2c_dt_gpio_free(i2c);
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kfree(i2c->ioarea);
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if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
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s3c24xx_i2c_dt_gpio_free(i2c);
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return 0;
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}
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#ifdef CONFIG_PM
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#ifdef CONFIG_PM_SLEEP
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static int s3c24xx_i2c_suspend_noirq(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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@@ -1142,10 +1187,14 @@ static int s3c24xx_i2c_resume(struct device *dev)
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return 0;
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}
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#endif
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#ifdef CONFIG_PM
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static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
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#ifdef CONFIG_PM_SLEEP
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.suspend_noirq = s3c24xx_i2c_suspend_noirq,
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.resume = s3c24xx_i2c_resume,
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#endif
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};
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#define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
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Block a user